JP2891809B2 - Time management method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time management system for an apparatus for measuring the number of fixed-length data such as ATM cells generated within a predetermined time.

[0002]

2. Description of the Related Art ATM (Asynchronous T)
In a transfer mode network, a user declares a band to be transmitted to the network. Therefore, if the user sends an ATM cell (hereinafter abbreviated as "cell") exceeding the declared value, cells exceeding the band allocated in advance will flow in, and this will affect the service quality of other calls. Will have an effect.

For this reason, it is necessary to monitor a cell exceeding a user's declared value so as not to flow into the network by a function of monitoring a user's declared band. Hereinafter, the function of monitoring the user's declared bandwidth is referred to as policing.
An example of this polishing method is shown below. This method is
It has a monitoring time width Tm which is a time unit for monitoring the number of cells transmitted from the user as a monitoring parameter, a maximum number of cells Xm allowed to exist during Tm, and X within the time Tm.
When more than m cells are input, the input cells are regarded as violating cells, and violating cell processing is performed.

Here, policing control in the case of a single user will be considered. FIG. 8 is a conceptual diagram of a cell format,
FIG. 9 is a policing control time chart for a single user when Tm = 5 and Xm = 2, and FIG. 10 is an operation flowchart thereof. As shown in FIG. 8, the cell has a fixed length of 53 bytes. The 5-byte header has cell destination information, which can also be used as a user identifier. The 48-byte information section is composed of information (audio, image, data) to be transferred to the destination. The cell sync is a signal that occurs periodically once every one cell time.

The cells are input to a policing circuit (not shown) in synchronization with a cell sink. The policing control in the policing circuit is performed by a clock counter that manages the monitoring time width Tm of the user, a cell number counter that manages the maximum number of cells Xm allowed to exist in Tm, and a control unit that controls these. . The clock counter counts up in synchronization with the cell sync, and when the clock counter value is T
Reset when it reaches m. The cell number counter is counted up when an input cell is present, and is reset when the clock counter is reset. An input cell is regarded as a violating cell if the cell number counter value at that time is Xm, and is processed as a violating cell. The violating cell processing includes, for example, "Broadband ISDN-compatible ATM communication technology" supervised by Masatake Nagai, p.
126, as described in Triqueps Co., Ltd., issued on November 29, 1990, there are various processing methods. Here, an unconditional discard method (cells determined as violating cells are discarded unconditionally) Is done).

As described above, the policing control for a single user can be easily performed.

[0007]

However, if policing control is performed on a plurality of users by the above-mentioned conventional method, a policing control function corresponding to the number of users is required.
There is a problem that the hardware scale becomes very large and the cost increases. SUMMARY OF THE INVENTION The present invention solves the above problems, and in a device for measuring the number of occurrences of a plurality of types of fixed-length data within a predetermined time for each type of fixed data, a clock counter for managing time for each fixed-length data. It is another object of the present invention to provide a time management method which does not require a data number counter for managing the number of fixed-length data, and therefore can greatly reduce the cost and the scale of hardware. It is another object of the present invention to provide a time management method that enables measurement of the number of occurrences of the same type of fixed-length data even if the same type of fixed-length data does not occur for one or more cycles of the clock counter.

[0008]

According to the present invention, in order to achieve the above object, there are provided U types (where U is an integer of 2 or more).
For measuring the number of occurrences of fixed-length data within a predetermined time for each type of fixed-length data, wherein a first timing signal generated for each data length of fixed-length data is input, and A clock counter for counting time in a cycle equal to or longer than the minimum value n of the specified value Tm of the monitoring time width of the fixed-length data set for each type of data, and a first timing signal and a clock signal synchronized therewith are input. A second timing signal having a speed twice as high as U / n of the first timing signal (rounded up if not an integer), and a timing generation circuit for outputting a counter value obtained by counting the second timing signal as a clock input. Monitoring of the arrival time tp of the previous fixed-length data and the fixed-length data is started using the data indicating the type of the input fixed-length data as an address. Elapsed time and tm, the number xm fixed length data generated during the elapsed time tm from specified value T
m, a memory containing the maximum number Xm of fixed-length data permitted to exist in a specified value Tm set in advance for each type of fixed-length data, a clock counter, a timing creation circuit, and a memory. The control unit is provided and the second
When the timing signal is detected, the contents of the memory are referred to using the counter value of the timing generation circuit as an address, and xm is set to 0.
If not, the counter value of the watch counter -tp + tm is calculated, and if it is equal to or greater than Tm, a value obtained by subtracting Tm from the counter value of the watch counter -tp + tm is newly set to tm, and the counter value of the watch counter is newly set to tp. If not more than Tm, the counter value of the clock counter−t
It is configured such that p + tm is newly set to tm and the counter value of the clock counter is set to tp.

[0009]

According to the present invention, since the time management system is configured as described above, the control unit refers to the contents of the memory using the counter value of the timing generation circuit as an address when the second timing signal is detected, and determines the value of xm. If it is not 0, the counter value of the clock counter -tp + tm is calculated. If it is equal to or greater than Tm, the monitoring time has elapsed, and a value obtained by subtracting Tm from the counter value of the clock counter -tp + tm is newly calculated as tm. And the counter value of the clock counter is newly set to tp. If the counter value is not equal to or greater than Tm, the counter value of the clock counter−tp + tm is set to tm, and the counter value of the clock counter is set to tp.

Therefore, the time update processing is performed at least once during Tm for any fixed-length data, and even if the fixed-length data does not occur for more than the period of the clock counter, the number of occurrences of the fixed-length data is reduced. Measurement becomes possible.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a time management system according to an embodiment of the present invention, which comprises a clock counter 1, a timing creation circuit 2, a cell arrival history memory 3, and a control unit 4.

The clock counter 1 receives a cell sync and counts up. Then, the counter value is reset when one cycle elapses, and starts counting up again. The timing creation circuit 2 receives a cell sync and a clock synchronized with the cell sync, and creates a timing for performing a time update process described later and a logical channel number LCN of a user who should perform the time update process. The cell arrival history memory 3 uses the logical channel number LCN of the input cell as an address, the previous cell arrival time tp, the monitoring elapsed time tm, the number of cells xm in the tm, and the maximum allowed to exist in the monitoring time width Tm, Tm. The data has the number of cells Xm. However, the address ranges from 0 to the number of users (U) -1. The control unit 4
A normal process for determining a violating cell and a time updating process provided for dealing with a case where there is no input cell for one cycle (Tck) of the clock counter are performed. These two processes may be performed serially (with no order relationship) or in parallel.

FIGS. 2 and 3 are flowcharts of the normal processing of the time management system according to the embodiment of the present invention. here,
Violation cell processing was unconditionally discarded. In FIG.
First, it is determined in step 11 whether or not there is a cell sync. If there is a cell sync, the process proceeds to step 12, and if the input cell is an empty cell in step 12, this processing is not performed. If it is not an empty cell, the cell arrival history memory 3 is read using the logical channel number LCN of the input cell as an address as shown in step 13. Then, in step 14, the monitoring elapsed time tm
If the number xm of cells in the cell is 0, xm in the cell arrival history memory 3 is set to 1 in step 15 in order to enter the monitoring state.
In step 16, the previous cell arrival time tp in the cell arrival history memory 3 is set to the clock counter value CTs. Further, if xm is not 0 in step 14, it is in the monitoring state, and the process proceeds to step 17 in FIG.

In step 17, (CTs-tp) + t
If m ≧ Tm, it means that the monitoring elapsed time has become equal to or longer than the monitoring time width.
p) + tm｝ −Tm is newly set as tm in the cell arrival history memory 3. In step 19, xm in the cell arrival history memory 3 is set to 1, and in step 20, tp is set to CTs. On the other hand, in step 17, (CTs-tp) + tm <T
If it is m, the monitoring elapsed time is less than the monitoring time width, so that the violating cell determination is performed in step 21. Where xm
If +1> Xm, it is regarded as a violation cell, and step 25
Is processed. In step 21, xm + 1
If ≤Xm, the cell is not regarded as a violation cell, so (CTs-tp) + tm is set to tm in step 22 and step 2
In step 3, xm + 1 is newly set to xm. Step 2
In step 4, CTs is set to tp. Here, as shown in the conceptual diagram of the arriving cell elapsed time in consideration of the counter cycle in FIG. 4, CTs-tp is CTs-tp>CTs-tp> 0
tp may be used, but when CTs−tp <0, CTs−tp
+ Tck. When CTs = tp, this value is regarded as Tck. Actually, two's complement of CTs and tp may be added.

By the way, if there is no input cell for at least one cycle of the clock counter by the normal processing alone, the monitoring elapsed time cannot be determined, and the policing processing becomes impossible. Therefore, a time update process is performed. The processing timing and the logical channel number LCN of the user who should perform the processing are as follows:
Created by the timing creation circuit. FIG. 5 is a block diagram showing a configuration of the timing generation circuit in the embodiment of the present invention.

1 cell time (1 cell hold time on line =
The number of times the time update process is performed during the cell sync interval)
If U is the number of users and n is the minimum value of the monitoring time width Tm for each user, it can be obtained by U / n. However, if this value is not an integer, it is rounded up to an integer. The cell sync and the clock are input to the timing pulse generation circuit 31 of FIG. 5, and a pulse synchronized with the cell sync is generated at a speed U / n times the speed of the cell sync. This is a pulse corresponding to the timing at which the time update process is performed. And
This pulse is used as a clock input to the counter 32 to create a logical channel number LCN of the user who performs the time update process.
However, the counter value is from 0 to U-1. As described above, the time update process is performed at least once during the monitoring time width Tm in any user cell.

In practice, the functions of the clock counter 1 and the timing creation circuit 2 in FIG. 1 can be handled as the same function. For example, U = 4096, n = 204
8. When Tck = 4096, generate a pulse at twice the speed synchronized with the cell sync, make a counter that repeats from 0 to 8102 using this pulse as a clock input, and output the counter excluding the upper 1 bit to the time update process. If the output of the counter excluding the lower 1 bit is used as a clock counter, two functions of the clock counter and the timing generation circuit can be performed with one function. However, for the sake of simplicity, the function is divided into two functions.

FIG. 6 is a flowchart of a time update process of the time management system according to the embodiment of the present invention. Hereinafter, the time update processing operation will be described with reference to FIG. 1, FIG. 5, and FIG. First, if there is an output pulse from the pulse generation circuit 31 in step 41 of FIG. 6, the time update process is performed by reading the cell arrival history memory 3 in step 42 using the counter value of the counter 32 as an address. In step 43, if xm = 0 in the cell arrival history memory 3, this processing is not performed because there is no previous cell arrival. If xm ≠ 0, (CTs−tp) + tm ≧ Tm in step 44
It is determined whether or not the monitoring time has passed. If this is the case, it is determined in step 45 that ｛(CTs-tp)
+ Tm｝ −Tm as tm in the cell arrival history memory 3,
Let CTs be tp. On the other hand, if the above condition is not satisfied, (CTs-tp) + tm is set to tm in step 46, and CTs is set to tp. By the above processing, the violating cell can be determined even if no cell is generated for the period Tck of the clock counter 1. However, Tck ≧ the minimum value of Tm for each user must be satisfied.

FIG. 7 shows the number of users U = 3, the period of the clock counter Tck = 8, and the monitoring time widths Tm1, Tm2, Tm3 of the users u1, u2, u3 are 2, 3, 4, and Tm, respectively.
Maximum number of cells X allowed to exist in 1, Tm2, Tm3
6 is a control time chart when m1, Xm2, and Xm3 are all set to 1 (therefore, U / n = 3/2 →
2). Hereinafter, the normal process and the time update process for the cell of the user u1 will be described. However, cell C1 of user u1
Are the cells of the user u1 to be input first, and the cells C1 to
C3 is not an empty cell. In addition, the counter values 0, 1, and 2 of the timing creation circuit are used by the users u1, u, respectively.
2 and u3.

First, when the cell C1 is input to the control unit 4 in FIG. 1, normal processing is performed. At this time, since YES is determined in both Step 11 and Step 12 in FIG. Here, the cell arrival history memory 3 is read using the logical channel number LCN of the user u1 as an address. However, since it is the first input cell, NO is determined in step 14 and xm = 1 in the cell arrival history memory 3 is set in step 15; In step 16, tp = CTs = 7
And

Next, when the counter value of the timing generation circuit of FIG. 7 becomes the second zero, a time update process is performed on the user u1. At this time, YES is determined in step 41 of FIG. 6, and in step 42, the cell arrival history memory is read using the counter value = 0 of the timing generation circuit as an address. Since xm = 1 has already been set, step 43 becomes YES and the process proceeds to step 44. here,
(CTs-tp) + tm = 1 (CTs = 0, tp = 7,
(since tm = 0), the answer is NO, and the routine proceeds to step 46. Here, tm = 1 and tp = 0.

Next, when the cell C2 is input, normal processing is performed in the same manner as described above, and xm = 1, CTs = 1, and tm =
1, since tp = 0, YES in step 17 of FIG.
Tm = 0, xm = 1, tp = 1 in step 18
And Next, when the counter value of the timing generation circuit of FIG. 7 becomes the third zero, the time updating process is performed on the user u1 in the same manner as described above. xm = 1, CTs = 1,
Since tp = 1 and tm = 0, YES in step 43 of FIG. 6, NO in step 43, and step 4
In step 6, tm = 0 and tp = 1.

Next, when cell C3 is input, normal processing is performed in the same manner as described above, and xm = 1, CTs = 2, and tm =
0, tp = 1, so NO in step 17 of FIG.
In the step 21, the result is NO, and in the step 25, the cell C3 is discarded. Hereinafter, the normal processing and the time management processing are similarly performed, and the normal processing and the time update processing are similarly performed in the cells of the user u2 and the user u3.

It should be noted that the present invention is not limited to the above-described embodiment, and various modifications are possible based on the gist of the present invention, and they are not excluded from the scope of the present invention.

[0025]

As described above in detail, according to the present invention, in an apparatus for measuring the number of occurrences of a plurality of types of fixed length data within a predetermined time for each type of fixed length data, Even if the fixed-length data does not occur for one cycle or more of the clock counter, the number of occurrences can be measured.

Therefore, if the present invention is applied to policing control of ATM cells having a plurality of users, even if cells having the same destination do not occur for one cycle or more of the clock counter,
Policing control becomes possible. Further, even if a clock counter is not prepared for each user, the clock counter 1 as a reference can be used.
In other words, since control is possible only by preparing a cell arrival history memory and a cell arrival time memory, the hardware scale and cost are greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a time management system according to an embodiment of the present invention.

FIG. 2 is a part of a normal processing flowchart of a time management method according to an embodiment of the present invention.

FIG. 3 is a part of a normal processing flowchart of a time management method according to the embodiment of the present invention.

FIG. 4 is a conceptual diagram of an arrival cell elapsed time in an embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a timing generation circuit according to the embodiment of the present invention.

FIG. 6 is a time update processing flowchart of a time management method according to an embodiment of the present invention.

FIG. 7 is an operation time chart of the time management system according to the embodiment of the present invention.

FIG. 8 is a conceptual diagram of a cell format.

FIG. 9 is an example of a conventional policing control time chart for a single user.

FIG. 10 is an example of a conventional policing control operation flowchart for a single user.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Clock counter 2 Timing creation circuit 3 Cell arrival history memory 4 Control part

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-247145 (JP, A) JP-A-3-143138 (JP, A) JP-A-5-110585 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H04L 12/28 H04L 12/56

Claims (2)

(57) [Claims] 1. An apparatus for measuring, for each type of fixed-length data, the number of occurrences of U types (where U is an integer of 2 or more) of fixed-length data within a predetermined time, (a) the fixed-length data First generated for each data length of
(B) a clock counter which receives the timing signal of (1) and counts the time in a cycle equal to or more than the minimum value n of the specified value Tm of the monitoring time width of the fixed length data set in advance for each type of fixed length data; 2.) The first timing signal and a clock signal synchronized with the first timing signal are input, and the second timing is U / n (rounded up if not an integer) times the first timing signal. A timing generating circuit for outputting a counter value obtained by counting the signal and the second timing signal as a clock input; and (c) an arrival time of the previous fixed-length data using data indicating the type of the input fixed-length data as an address. tp, the time tm elapsed since the monitoring of the fixed length data was started,
A number xm of the fixed-length data generated during the elapsed time;
A memory containing the specified value Tm and the maximum number Xm of the fixed-length data permitted to exist in the specified value Tm preset for each type of fixed-length data; and (d) the clock counter. A control unit for controlling a timing generation circuit and a memory, wherein when the second timing signal is detected, the contents of the memory are referred to by using a counter value of the timing generation circuit as an address. Is calculated, and if it is equal to or greater than Tm, a value obtained by subtracting Tm from the counter value -tp + tm of the clock counter is newly set to tm, and the counter value of the clock counter is newly set to tp. If not, the counter value of the clock counter -tp + tm is newly set to tm, and
A time management method characterized by newly setting a counter value of a clock counter to tp. 2. The time management system according to claim 1, wherein the U types of fixed-length data are ATM cells having different destinations, and the first timing signal is a cell sync.