JP2895656B2 - Active matrix type liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device in which a thin film transistor is provided corresponding to a pixel, and a voltage is written to and held in a liquid crystal cell by using the switching action of the thin film transistor.

[0002]

2. Description of the Related Art An active matrix display device uses liquid crystal as a display medium and is used as a thin display device for an information terminal like a simple matrix display device. An active matrix display device can be operated as if a large number of pixels are individually driven. Therefore, even if the number of pixels increases with an increase in the display capacity, the duty ratio does not change as in the simple matrix type. And the problems such as a decrease in contrast and a decrease in viewing angle do not occur. For this reason, the active matrix type liquid crystal display device can obtain color display comparable to that of a cathode ray tube (CRT), and its use as a thin flat display is expanding.

As a method capable of realizing a high production yield and a beautiful full-color display, a method disclosed in Japanese Patent Application No. 2-218966 is disclosed.
), A thin film transistor (TFT-C) for compensating for a DC level shift that causes an afterimage
There has been proposed a facing matrix type active matrix type display device provided with. The proposed active matrix display device will be described with reference to FIG.

A display electrode 1 is provided on one of two insulating substrates 1 opposed to each other via a liquid crystal (not shown).
4 are arranged in a matrix. Display electrode 14 in FIG.
A reference potential supply bus line 16 is formed at the center between the display electrodes 14 in the row direction. Two scan bus lines 12 having common terminals are formed in parallel on both sides of the reference potential supply bus line 16 between the display electrodes 14.

The display electrode 14 includes one of a source and a drain of an address thin film transistor (TFT-A) 20 and a compensation thin film transistor (TFT-C) 22 for compensating for a DC level shift and providing redundancy. Source·
One of the drains is connected. The other of the source and the drain of the TFT-A 20 and the other of the source and the drain of the TFT-C 22 are connected to the reference potential supply bus line 16.
It is connected to the.

[0006] One of the two scan bus lines 12
The gate of the TFT-A20 is connected to the book, and the gate of the TFT-C22 is connected to the other book. These two
The two thin film transistors are operated by configuring the drive waveform of the scan bus line 12 with an address pulse and a compensation pulse. On the other insulating substrate (not shown) sandwiching the liquid crystal, stripe-shaped data bus lines 10 are formed facing the display electrodes 14 in the column direction of the display electrodes 14 in the figure.

The display is performed by controlling the voltage applied between the data bus line 10 and the display electrode 14. With such a configuration, a high yield is obtained because the scan bus line 12 and the data bus line 10 do not intersect on the TFT substrate 1, and a beautiful display can be realized by compensation of the DC level shift.

Further, the reference potential supply bus line 16
By using two electrode layers of the FT-A20 and the TFT-C22, ie, the electrode constituting the source / drain and the electrode constituting the gate, the structure can be completely multi-layered, so that a structure in which a disconnection defect hardly occurs. Can be.

[0009]

However, the scan bus line 12 can be partially formed into a multilayer structure by using these two electrode layers.
The connection portion between the TFT 20 and the TFT-C 22 needs to be constituted only by the gate layer, and cannot have a multi-layer structure.

[0010] Further, since two parallel scan bus lines 12 are connected only at the terminal section, if any one of the scan bus lines 12 is broken, it is displayed as a line defect. As described above, in the active matrix type display device, T
Since the FT must be formed, the structure becomes complicated,
There is a problem that the above-mentioned defects are easily generated in the manufacturing process. Further, when attempting to manufacture a large-screen active matrix display device, a large-sized manufacturing apparatus is required, which increases the equipment cost, and at the same time, the above-described defects lower the manufacturing yield. is there. Therefore, there is a problem that its practical use is currently limited to those having a relatively small screen size.

An object of the present invention is to provide an active matrix type display device which can realize a high production yield at low cost even with a large screen.

[0012]

An object of the present invention is to provide two insulating substrates opposed to each other via a liquid crystal, and a plurality of display electrodes formed in a matrix on one of the two insulating substrates. A reference potential supply bus line formed between rows of the plurality of display electrodes, and between the plurality of display electrode rows,
A pair of scan bus lines formed in parallel on both sides of the reference potential supply bus line, a gate connected to one of the pair of scan bus lines, the display electrode or the reference potential; An address thin-film transistor having a drain connected to one of the supply bus lines and a source connected to the other of the display electrode or the reference potential supply bus line; and a thin-film transistor for addressing the pair of scan bus lines. A connected gate, a drain connected to one of the other display electrodes or the reference potential supply bus line disposed opposite to the display electrode with respect to the reference potential supply bus line, and the other display electrode or A compensating thin film transistor having a source connected to the other of the reference potential supply bus lines, and a display electrode provided on the other of the two insulating substrates. Oppositely, in the active matrix type liquid crystal display device of the opposite matrix format and a data bus line stripe formed in a column direction of the display electrode, the scan bus lines, the address
Thin film transistor for compensation and / or thin film transistor for compensation
Multi-layering in areas other than areas where the transistors are formed
The active matrix type liquid crystal display device is characterized in that the address thin film transistor and the compensation thin film transistor are provided at positions obliquely facing each other across the reference potential supply bus line. .

The above object is also achieved by providing two insulating substrates opposed to each other via a liquid crystal, a plurality of display electrodes formed in a matrix on one of the two insulating substrates, A reference potential supply bus line formed between rows of display electrodes, a pair of scan bus lines formed between the plurality of display electrode rows and in parallel on both sides of the reference potential supply bus line, and A gate connected to one of the pair of scan bus lines, a drain connected to one of the display electrode or the reference potential supply bus line, and a drain connected to the other of the display electrode or the reference potential supply bus line. An address thin-film transistor having a source connected thereto, a gate connected to the other of the pair of scan bus lines, and the display potential with respect to the reference potential supply bus line. A drain connected to one of the other display electrodes or the reference potential supply bus line, and a source connected to the other display electrode or the other of the reference potential supply bus lines. An active matrix liquid crystal of a facing matrix type having a compensating thin film transistor and a stripe-shaped data bus line formed in the column direction of the display electrode on the other of the two insulating substrates so as to face the display electrode. In the display device, the present invention is achieved by an active matrix liquid crystal display device having a connection portion connecting each scan bus line of the pair of scan bus lines between rows of the display electrodes.

[0014]

According to the present invention, it is possible to realize a multi-layer structure of two scan bus lines formed in parallel on both sides of the reference potential supply bus line, and it is possible to suppress the occurrence of line defects in the scan bus lines. A large screen active matrix display device can be realized, and a high production yield can be realized at low cost.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An active matrix type liquid crystal display according to a first embodiment of the present invention will be described with reference to FIG. A plurality of display electrodes 14 are formed in a matrix on one of two insulating substrates 1 opposed to each other via a liquid crystal (not shown).

A reference potential supply bus line 16 is formed between rows of the plurality of display electrodes 14. Multiple display electrodes 14
, And a pair of scan bus lines 12 are formed in parallel on both sides of the reference potential supply bus line 16. The gate is connected to one scan bus line 12 of the set of scan bus lines 12, and the display electrode 14
And an address thin film transistor TFT-A20 connected between the reference potential supply bus line 16 and the reference potential supply bus line 16.

A gate is connected to another scan bus line 12 of the set of scan bus lines 12,
A compensation thin film transistor TFT-C22 connected between the other display electrode 14 and the reference potential supply bus line 16 is formed. Address thin film transistor TFT-A2
0 is a set of display electrodes 14 arranged adjacent to each other, and the compensation thin film transistor TFT-C22 is
The other display electrodes 14 which are provided on the opposite side via the reference potential supply bus line 16 and are adjacent to each other form a set, and are compensated for on the reference potential supply bus line 16 by a set of address thin film transistors TFT-A20. Of thin film transistors TFT-C22 are alternately arranged.

A stripe-shaped data bus line (not shown) is formed on another insulating substrate (not shown) in the column direction of the display electrodes 14 so as to face the display electrodes 14. Display is performed by controlling the voltage applied between the data bus line and the display electrode 14. As in the active matrix type liquid crystal display device according to the present embodiment, the TF
If T is arranged, the position of the portion where the scan bus line 12 is formed only of the gate electrode layer of the TFT (the TFT portion and its vicinity) becomes far between the two scan bus lines 12, so that, for example, Even when a large foreign substance is mixed in the formation of the gate electrode layer in the manufacturing process of the matrix type liquid crystal display device and the gate electrode corresponding layer portions of the two scan bus lines 12 are disconnected at the same time, the two scan bus lines 12 At least one of the scan bus lines 12 is multilayered and does not become a line defect of the scan bus line 12. In other words, the source / source of one multi-layer scan bus line 12
This means that they are connected by the drain electrode corresponding layer.

A method of manufacturing an active matrix type liquid crystal display device according to a first embodiment of the present invention will be described with reference to FIGS. 2 to 5 show bottom patterns of the substrate of the active matrix type liquid crystal display device of the present embodiment, and FIGS.
(A)-(d) shows the schematic sectional drawing in XX of FIGS. 2-5. First, in order to form a display electrode 31 which is a transparent electrode on the glass substrate 1, an ITO 30 is formed to a thickness of 50 nm by a sputtering method. Next, n ⁺ a-
Plasma CVD for ohmic contact layer 32 of Si layer
After a thickness of 30 nm is formed by a method, the source / drain electrodes, the display electrodes 31, and the openings 34 for connecting the scan bus lines 12 are patterned. The hatched portions in the figures are the source / drain and electrode patterns (FIGS. 2 and 6).
(A)).

Then, a 30 nm thick a-S
i is grown and patterned to form a semiconductor layer 36. After a first-layer gate insulating film 38 of a SiN layer is formed on the semiconductor layer 36 by a plasma CVD method with a thickness of about 50 nm, patterning for element isolation is performed. The hatched portion in FIG. 3 is an element isolation pattern (FIG. 3, FIG. 6B). continue,
Plasma CVD of the second gate insulating film 40 of the SiN layer
After a thickness of about 250 nm is formed by the method, an opening 42 is formed (FIGS. 4 and 6C).

Furthermore, Al is sputtered to a thickness of 60
After forming only 0 nm, the scan bus line 12 and the reference voltage supply bus line 16 are patterned. FIG.
Middle shaded portions are bus line patterns (FIGS. 5 and 6).
(D)). By doing so, the reference potential supply bus line 16 and the scan bus line 12 are made of ITO as the source / drain electrode material and Al as the gate electrode material.
Thereby, each can be multilayered.

An active matrix type liquid crystal display device according to a second embodiment of the present invention will be described with reference to FIG. A plurality of display electrodes 14 are formed in a matrix on one of two insulating substrates 1 opposed to each other via a liquid crystal (not shown). A reference potential supply bus line 16 is formed between rows of the plurality of display electrodes 14. A set of two scan bus lines 1 is provided between rows of the plurality of display electrodes 14 and in parallel on both sides of the reference potential supply bus line 16.
2 are formed. The gate is connected to one scan bus line 12 of the set of scan bus lines 12, and an address thin film transistor TFT-A20 connected between the display electrode 14 and the reference potential supply bus line 16 is formed.

A gate is connected to another scan bus line 12 of the set of scan bus lines 12,
A compensation thin film transistor TFT-C22 connected between the other display electrode 14 and the reference potential supply bus line 16 is formed. The thin-film transistor TFT-A20 for addressing the display electrode 14 in a certain row and the display electrode 14 in an adjacent row
The compensation thin film transistor TFT-C22 is symmetrically connected to the reference potential supply bus line 16.

Each of the pair of scan bus lines 12 is connected by a connection portion 50 at the center in the figure. A stripe-shaped data bus line (not shown) is formed on the other one of the insulating substrates (not shown) so as to face the display electrodes 14 in the column direction of the display electrodes 14. Display is performed by controlling the voltage applied between the data bus line and the display electrode 14.

By doing so, a drive voltage can be supplied to the gates of all the TFTs even if there is a disconnection portion, unless there are two or more disconnection portions between adjacent connection portions, causing display defects. Nothing. In particular, when the TFT forming the matrix has a top gate stagger structure, the same conductive layer as the drain and source of the TFT is used as the conductive layer connecting the two scan bus lines 12 to supply the reference potential when connected. The influence of the intersection with the bus line 16 can be minimized.
That is, the cross-sectional structure of the intersection can be made the same as the cross-sectional structure of the overlapping portion of the source / drain and the gate of the TFT, and the increase in the overlapping area due to the connection of the two scan bus lines 12 is small. For example, if the panel is 480x64
Considering the case of 0-color pixel (stripe configuration), where the overlap of the gate and drain per TFT in the channel direction is 5 μm (the overlap in the vertical direction with the channel is 20 μm), the overlap of the gate and drain per scan bus line is as follows. 5 × 20 × 640 × 3 = 192000 μm ² .

On the other hand, two scan bus lines 1
In the case where 10 connection points are provided per line, the overlap at this point is 10 lines per scan bus line.
× 10 × 10 = 1000 μm ² , and the increase in overlap is suppressed to 1% or less. As described above, according to the present embodiment, the multiplexing of the scan bus lines 12 is performed by connecting two scan bus lines 12 provided in parallel on both sides of the reference potential supply bus line 16 in the display area. And the yield for disconnection display defects can be significantly improved.

A method of manufacturing an active matrix type liquid crystal display device according to a second embodiment of the present invention will be described with reference to FIGS. FIGS. 8 to 11 show substrate bottom patterns of the active matrix type liquid crystal display device of this embodiment, FIGS. 12 (a) to 12 (d) are schematic sectional views taken along line XX, and FIGS. d ') shows a schematic sectional view along the line YY.
First, in order to form the display electrode 31 which is a transparent electrode on the glass substrate 1, an ITO having a thickness of 50 nm is formed by a sputtering method.
Form 30. Next, after forming an ohmic contact layer 32 of an n ⁺ a-Si layer on the ITO 30 by a thickness of 30 nm by a plasma CVD method, patterning of a source / drain electrode, a display electrode 31, and an opening for scan bus connection is performed. . The hatched portions in FIG. 8 indicate the source / drain and electrode patterns (FIGS. 8, 12A and 12A).

Next, a 30 nm thick a-S
i is grown and patterned to form a semiconductor layer 36. After a first-layer gate insulating film 38 of a SiN layer is formed on the semiconductor layer 36 by a plasma CVD method with a thickness of about 50 nm, patterning for element isolation is performed. The hatched portions in FIG. 9 are the element isolation patterns (FIGS. 9 and 12B,
(B ')).

Subsequently, after the gate insulating films 40 and 43 of the second layer of the SiN layer are formed to a thickness of about 250 nm by the plasma CVD method, openings 42 and 44 are formed.
(FIG. 12 (c), (c ')). Further, after Al is formed to a thickness of 600 nm by sputtering, the scan bus line 12 and the reference voltage supply bus line 16 are patterned. The hatched portions in FIG. 11 are bus line patterns. At this time, the two scan bus lines 12 are connected by the connection electrode (ITO) 30 via the opening 44 already formed (FIGS. 11 and 12).
(D), (d ')).

As described above, according to the present embodiment, multiplexing of scan bus lines can be realized by connecting two scan bus lines, so that a high yield and a low-cost TFT liquid crystal display can be manufactured. Becomes An active matrix liquid crystal display according to a third embodiment of the present invention will be described with reference to FIG.

A plurality of display electrodes 14 are formed in a matrix on one of the two insulating substrates opposed to each other via a liquid crystal (not shown). A reference potential supply bus line 16 is formed between rows of the plurality of display electrodes 14. A set of two scan bus lines 12 is formed between rows of the plurality of display electrodes 14 and in parallel on both sides of the reference potential supply bus line 16.

A gate is connected to one scan bus line 12 of the set of scan bus lines 12, and an address thin film transistor TFT-A20 connected between the display electrode 14 and the reference potential supply bus line 16 is formed. I have. In addition, a gate is connected to another scan bus line 12 of one set of scan bus lines 12, and a compensating thin film transistor TFT-C22 connected between another display electrode 14 and the reference potential supply bus line 16 is formed. Have been.

Address thin film transistor TFT-A2
0 is a set of display electrodes 14 arranged adjacent to each other, and the compensation thin film transistor TFT-C22 is
The other display electrodes 14 which are provided on the opposite side via the reference potential supply bus line 16 and are adjacent to each other form a set, and are compensated for on the reference potential supply bus line 16 by a set of address thin film transistors TFT-A20. Of thin film transistors TFT-C22 are alternately arranged.

Each of the pair of scan bus lines 12 is connected by a connection section 50 at the center in the drawing. A stripe-shaped data bus line (not shown) is formed on the other one of the insulating substrates (not shown) so as to face the display electrodes 14 in the column direction of the display electrodes 14. Display is performed by controlling the voltage applied between the data bus line and the display electrode 14.

A method of manufacturing an active matrix type liquid crystal display according to a third embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. 14 to 17 show substrate bottom patterns of the active matrix type liquid crystal display device of this embodiment, and FIGS. 18 (a) to 18 (d) are schematic cross-sectional views taken along line XX.
(A ') to (d') are schematic sectional views taken along the line YY.

First, in order to form a display electrode 31 which is a transparent electrode on the glass substrate 1, a thickness of 50 mm is formed by a sputtering method.
An ITO 30 nm is formed. Next, n
After forming an ohmic contact layer 32 of ⁺ a-Si layer with a thickness of 30 nm by a plasma CVD method, patterning of a source / drain electrode, a display electrode 31 and an opening 34 for connecting a scan bus is performed. The hatched portions in FIG. 14 indicate source / drain and electrode patterns (FIGS. 14 and 18).
(A), (a ')).

Next, a 30 nm thick a-S
i is grown and patterned to form a semiconductor layer 36. After a first-layer gate insulating film 38 of a SiN layer is formed on the semiconductor layer 36 by a plasma CVD method with a thickness of about 50 nm, patterning for element isolation is performed. The hatched portions in FIG. 15 are element isolation patterns (FIGS. 15 and 18B,
(B ')).

Subsequently, after the gate insulating films 40 and 43 of the second layer of the SiN layer are formed to a thickness of about 250 nm by the plasma CVD method, openings 42 and 44 are formed.
FIG. 18 (c), (c ′)). Further, after Al is formed to a thickness of 600 nm by sputtering, the scan bus line 12 and the reference voltage supply bus line 16 are patterned. The hatched portions in FIG. 17 are bus line patterns. At this time, the two scan bus lines 12 are connected by the connection electrode (ITO) 30 through the opening 44 already formed (FIGS. 17 and 18).
(D), (d ')).

As described above, according to this embodiment, the multiplexing of two scan bus lines and the multi-layering can be effectively combined, so that the yield is high even on a large screen, and a low-cost TFT liquid crystal display can be realized. Manufacturing becomes possible.

[0040]

As described above, according to the present invention, it is possible to suppress the occurrence of line defects in scan bus lines, and to manufacture a TFT liquid crystal display with a high yield and a low cost even on a large screen.

[Brief description of the drawings]

FIG. 1 is a diagram showing an active matrix type liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a view showing a manufacturing process of the active matrix type liquid crystal display device according to the first embodiment of the present invention.

FIG. 3 is a view showing a manufacturing process of the active matrix type liquid crystal display device according to the first embodiment of the present invention.

FIG. 4 is a view showing a manufacturing process of the active matrix type liquid crystal display device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a manufacturing process of the active matrix type liquid crystal display device according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a manufacturing process of the active matrix type liquid crystal display device according to the first embodiment of the present invention.

FIG. 7 is a diagram showing an active matrix type liquid crystal display device according to a second embodiment of the present invention.

FIG. 8 is a diagram illustrating a manufacturing process of an active matrix liquid crystal display device according to a second embodiment of the present invention.

FIG. 9 is a view illustrating a manufacturing process of an active matrix liquid crystal display device according to a second embodiment of the present invention.

FIG. 10 is a diagram illustrating a manufacturing process of an active matrix liquid crystal display device according to a second embodiment of the present invention.

FIG. 11 is a view showing a manufacturing process of the active matrix type liquid crystal display device according to the second embodiment of the present invention.

FIG. 12 is a diagram showing a manufacturing process of the active matrix type liquid crystal display device according to the second embodiment of the present invention.

FIG. 13 is a view showing an active matrix type liquid crystal display device according to a third embodiment of the present invention.

FIG. 14 is a view showing a manufacturing process of the active matrix type liquid crystal display device according to the third embodiment of the present invention.

FIG. 15 is a view showing a manufacturing process of the active matrix type liquid crystal display device according to the third embodiment of the present invention.

FIG. 16 is a diagram illustrating a manufacturing process of the active matrix type liquid crystal display device according to the third embodiment of the present invention.

FIG. 17 is a diagram illustrating a manufacturing process of the active matrix liquid crystal display device according to the third embodiment of the present invention.

FIG. 18 is a diagram showing a manufacturing process of the active matrix type liquid crystal display device according to the third embodiment of the present invention.

FIG. 19 is a diagram showing a proposed active matrix liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 10 ... Data bus line 12 ... Scan bus line 14 ... Display electrode 16 ... Reference potential supply bus line 20 ... Thin film transistor (TFT-A) 22 ... Thin film transistor (TFT-C) 30 ... ITO 31 ... Display electrode 32 ... ohmic contact layer 34 ... opening 36 ... semiconductor layer 38 ... gate insulating film 40 ... gate insulating film 42 ... opening 43 ... gate insulating film 44 ... opening 50 ... connecting part

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koji Ogata 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Co., Ltd. (56) References JP-A-4-102825 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02F 1/136 G09F 9/30

Claims (4)

(57) [Claims] 1. Two insulating substrates opposed to each other via a liquid crystal, a plurality of display electrodes formed in a matrix on one of the two insulating substrates, and a space between rows of the plurality of display electrodes. A pair of scan bus lines formed between the plurality of display electrode rows and in parallel on both sides of the reference potential supply bus line; A gate connected to one of the scan bus lines, a drain connected to one of the display electrode or the reference potential supply bus line, and a source connected to the other of the display electrode or the reference potential supply bus line An address thin-film transistor comprising: a gate connected to the other of the pair of scan bus lines; and a gate connected to the display electrode with respect to the reference potential supply bus line. A drain connected to one of the other display electrodes or the reference potential supply bus line, and a compensation thin film transistor including a source connected to the other display electrode or the other of the reference potential supply bus lines, wherein said display electrodes and facing the two insulating the other substrate, the active matrix type liquid crystal display device of the opposite matrix format and a data bus line stripe formed in a column direction of the display electrodes, wherein The canvas line is the thin film transformer for the address.
Forming a transistor and / or the compensating thin film transistor.
The address thin film transistor and the compensation thin film transistor are provided at positions obliquely opposed to each other with the reference potential supply bus line interposed therebetween. Active matrix type liquid crystal display device. 2. The active matrix type liquid crystal display device according to claim 1, wherein a pair of the addressing thin film transistors of the display electrodes arranged adjacent to each other in a row direction is on the opposite side via the reference potential supply bus line. And a pair of the compensating thin film transistors of the other display electrodes arranged adjacent to each other are connected alternately to the reference potential supply bus line. . 3. Two insulating substrates opposed to each other via a liquid crystal; a plurality of display electrodes formed in a matrix on one of the two insulating substrates; and a space between the plurality of display electrodes. A pair of scan bus lines formed between the plurality of display electrode rows and in parallel on both sides of the reference potential supply bus line; A gate connected to one of the scan bus lines, a drain connected to one of the display electrode or the reference potential supply bus line, and a source connected to the other of the display electrode or the reference potential supply bus line An address thin-film transistor comprising: a gate connected to the other of the pair of scan bus lines; and a gate connected to the display electrode with respect to the reference potential supply bus line. A drain connected to one of the other display electrodes or the reference potential supply bus line, and a compensation thin film transistor including a source connected to the other display electrode or the other of the reference potential supply bus lines, In a facing matrix type active matrix liquid crystal display device having a stripe-shaped data bus line formed in a column direction of the display electrodes on the other of the two insulating substrates so as to face the display electrodes, An active matrix type liquid crystal display device comprising a connection portion for connecting each scan bus line of the pair of scan bus lines between rows of display electrodes. 4. The active matrix type liquid crystal display device according to claim 1, further comprising a connection unit for connecting each scan bus line of the pair of scan bus lines between rows of the display electrodes. An active matrix type liquid crystal display device characterized by the following.