JP2897687B2 - Flash memory data eraser - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to erasing data in a flash memory, and more particularly to a data erasing device for preventing over-erasing of a flash memory.

[0002]

2. Description of the Related Art Generally, when erasing data in a flash memory, it is necessary to confirm that the contents of the entire area of the flash memory are "0" in order to prevent destruction due to over-erasure. For example, Japanese Patent Application Laid-Open No. 4-228193 discloses a circuit in which the output of a read sense amplifier of a flash EEPROM is connected to a verify / erase control circuit, and an erase voltage is applied after performing an erase verify.

[0003]

However, in a system in which a flash memory and a processor are connected by a bus line and the processor controls the flash memory,
If an error occurs on the data bus line or control line for any reason, the processor mistakenly recognizes that all the read data is '0' and executes the data erase even though the read data from the flash memory is not '0'. Overerasing may cause destruction.

It is an object of the present invention to provide a flash memory data erasing device capable of reliably preventing over-erasing.

[0005]

A data erasing device according to the present invention is connected to a data input / output terminal and a control signal input terminal of a flash memory, and receives data read from the flash memory and a control signal inputted from a control circuit to the control signal input terminal. First bit determining means for determining whether all bits of the signal are at a constant level, and data received from the flash memory connected to the data input terminal and the control signal output terminal of the control circuit and output from the control signal output terminal The second bit determining means for determining whether or not all bits of the set control signal are at the constant level, the determination result of the first bit determining means does not match the determination result of the second bit determining means. Erasure prohibiting means for sometimes prohibiting erasure of data in the flash memory.

[0006]

According to the present invention, it is determined whether or not all the read data and control signals from the flash memory are at a constant level, and whether or not all of the read data and control signals of the flash memory received by the control circuit are at the constant level. Are compared, and when a mismatch is detected, the data erasing process is prohibited. Therefore, for example, even when the read data and the control signal of the control circuit are all “0” due to the abnormality of the data bus line and / or the control line, the read data and the control signal of the flash memory side are other than “0”. If it contains bits, the data erasure process is prohibited,
Over-erasure is reliably prevented.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a flash memory access circuit according to the present invention. The data input / output terminal of the flash memory 101 is a bus buffer 1
02, a bus line 103, and a bus buffer 104 are connected to a data input / output terminal of a control circuit (CPU) 105.

As is well known, the flash memory 101 has a built-in data erasing means, and erases stored data according to a data erasing command received from the CPU 105 through the bus line 103.

The CPU 105 includes a flash memory 101
A read signal (RD) is output through a control line, and an address is output through an address bus. The address bus is connected to the address decoder 110, and the address decoder 110 outputs a chip select signal (CS) to the flash memory 101 through a control line.

All bit lines of the bus line on the flash memory 101 side and all bit lines of the control line (read signal RD and chip select signal CS) are connected to the NOR gate 10.
6 is connected. On the other hand, all the bit lines of the bus lines on the CPU 105 side and all the bit lines of the control lines (the read signal RD and the chip select signal CS) are connected to the NOR gate 107. NOR gates 106 and 10
7 is input to an exclusive OR (ExOR) gate 108, and the output of the ExOR gate 108 is input to an interrupt terminal of the CPU 105 via a flip-flop circuit 109.

In such a configuration, when the CPU 105 performs read access to the flash memory 101, the chip select signal CS output from the address decoder 110 is set to low (L) level, and the read signal RD is set to L level. . As a result, the read data is output from the flash memory 101 to the CPU 105 through the bus line 103.

When the read data bits of the data input / output terminals of the flash memory 101 are all "0", N
Since all the L-level signals are input to the OR gate 106, the NOR gate 106 outputs a high (H) level. Conversely, when at least one '1' exists in the read data bit, the output of the NOR gate 106 goes to L level.

Similarly, when all the data bits of the data input / output terminals of the CPU 105 are "0", since all the L level signals are inputted to the NOR gate 107, the NOR gate 107 outputs a high (H) level. Conversely, when there is at least one "1" in the data bit, the output of the NOR gate 107 goes low.

Therefore, if there is no abnormality in the bus line 103 transmitting the read data and the control line transmitting the control signal, the outputs of the NOR gates 106 and 107 always coincide. If the data bit or the control signal bit changes due to some abnormality in the bus line or the control line, the NOR gates 106 and 1
07 no longer matches. Further, when the bus line is disconnected or the flash memory 101 cannot be normally accessed, the CPU 105 may read “1” in the read data on the flash memory 101 side.
Are all "0", and the NOR gate 106
And 107 no longer match.

Such NOR gates 106 and 107
Is detected by the ExOR gate 108. If the outputs of the NOR gates 106 and 107 match, the ExOR gate 108 sets the L level to
If they do not match, an H level is output. When the output of the ExOR gate 108 is at L level, the bus buffer 102
Since there is no change in the data bits between
The interrupt processing of the PU 105 is not executed. When the output of the ExOR gate 108 becomes H level, an abnormality occurs and the CPU 105 cannot acquire correct read data. Therefore, an interrupt is executed to the CPU 13 and the execution of the data erase program is immediately stopped.

As described above, the CPU 105 can reliably determine that the data read from the flash memory 101 is all "0", and even a single bit is "0".
If data other than the above exists, the erasing process can be prohibited to prevent the flash memory 101 from being over-erased.

In this embodiment, the flash memory 1
In order to detect a match / mismatch not only with the storage data 01 but also with a control signal such as a read signal RD and a chip select signal CS output from the CPU 105 to the flash memory 101, a failure of the control line is also detected. Over-erasing of the flash memory 101 can be prevented.

[0019]

As described above, the data erasing device for a flash memory according to the present invention can determine whether the read data output from the flash memory is all "0" or not and determine whether the control circuit has received the data. The result of the determination as to whether or not all the read data is '0' is compared with each other, and if a mismatch is detected, the data erasing process is prohibited. Therefore, even when the read data of the control circuit is all “0”, when the read data on the flash memory side includes bits other than “0” due to an abnormality of the data bus line and / or the control line, the data erasing process is performed. Is forbidden. As a result, over-erasing of the flash memory is reliably prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory access circuit incorporating one embodiment of a data erasing device according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Flash memory 102 Bus buffer 103 Bus line 104 Bus buffer 105 CPU 106 NOR gate 107 NOR gate 108 ExOR gate 109 Flip-flop 110 Address decoder

Claims (3)

(57) [Claims] 1. A data erasing device comprising a flash memory and a control circuit, wherein the data erasing device is connected to a data input / output terminal of the flash memory and a control signal input terminal, and receives read data of the flash memory and the control signal input terminal from the control circuit. First bit determining means for determining whether all bits of the control signal input to the control circuit are at a constant level, and data received from the flash memory connected to a data input terminal and a control signal output terminal of the control circuit. A second bit determination unit that determines whether all bits of the control signal output from the control signal output terminal are at the constant level, and a determination result of the first bit determination unit and the second bit determination unit. An erasure prohibiting means for prohibiting erasure of data in the flash memory when the determination result of the bit determination means does not match. A data erasing device for a flash memory, comprising: a stage; 2. The flash memory data erasing device according to claim 1, wherein said control signal comprises a chip select signal of said flash memory and a read control signal. 3. The flash memory data erasing device according to claim 1, wherein the flash memory and the control circuit are connected by a bus line.