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JP2900669B2 - Semiconductor device - Google Patents
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JP2900669B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2900669B2
JP2900669B2 JP3303673A JP30367391A JP2900669B2 JP 2900669 B2 JP2900669 B2 JP 2900669B2 JP 3303673 A JP3303673 A JP 3303673A JP 30367391 A JP30367391 A JP 30367391A JP 2900669 B2 JP2900669 B2 JP 2900669B2
Authority
JP
Japan
Prior art keywords
brazing material
matching circuit
side wall
internal matching
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3303673A
Other languages
Japanese (ja)
Other versions
JPH05206192A (en
Inventor
慶太 岡平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP3303673A priority Critical patent/JP2900669B2/en
Publication of JPH05206192A publication Critical patent/JPH05206192A/en
Application granted granted Critical
Publication of JP2900669B2 publication Critical patent/JP2900669B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/013Manufacture or treatment of die-attach connectors
    • H10W72/01308Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07311Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5445Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はL帯(390〜1500
MHZ )以上のマイクロ波帯で用いられる、内部整合回
路を内蔵した高出力トランジスタに関するものである。
The present invention relates to an L band (390-1500
MH Z) used in the above microwave band, to a high power transistor with a built-in internal matching circuit.

【0002】[0002]

【従来の技術】従来のマイクロ波帯用高出力トランジス
タについて、図3(a)〜(d)を参照して説明する。
2. Description of the Related Art A conventional high output transistor for a microwave band will be described with reference to FIGS.

【0003】図3(a)に示すように、放熱板1に溶接
された突起12にろう材14を介して半導体チップ15
がマウントされる。
[0003] As shown in FIG. 3 (a), a semiconductor chip 15 is attached to a projection 12 welded to the heat sink 1 through a brazing material 14.
Is mounted.

【0004】通常、ろう材14が流れ出さないように、
側壁や溝が設けられる。
Usually, in order to prevent the brazing material 14 from flowing out,
Side walls and grooves are provided.

【0005】第1の方法は図3(b)に示すように、放
熱板1のマウント用の突起12に導電性の側壁13a,
13bが形成されて、ろう材14が放熱板1に流れ込ま
ないようにしている。
In the first method, as shown in FIG. 3 (b), conductive side walls 13a,
13 b is formed to prevent the brazing material 14 from flowing into the heat sink 1.

【0006】第2の方法は図3(c)に示すように、放
熱板1のマウント用の突起12に幅0.15mm、厚さ
50μmの絶縁膜16a,16bがコーティングされ
て、ろう材14が放熱板1に流れ出してもはじく役割を
果たす。
In the second method, as shown in FIG. 3C, the mounting projections 12 of the heat sink 1 are coated with insulating films 16a and 16b having a width of 0.15 mm and a thickness of 50 μm, and the brazing material 14 is formed. Plays a repelling role even if it flows out to the heat sink 1.

【0007】第3の方法は図3(d)に示すように、放
熱板1に溝18を設けて、ろう材が流れて拡がるのを防
いでいる。
In the third method, as shown in FIG. 3D, a groove 18 is provided in the heat sink 1 to prevent the brazing material from flowing and expanding.

【0008】[0008]

【発明が解決しようとする課題】図3(b)のように導
電性の側壁13a,13bが形成されているとボンディ
ングワイヤ17が接触してショートする恐れがある。た
るみを小さくして(最短距離で)ワイヤボンディングで
きないという問題がある。
When the conductive side walls 13a and 13b are formed as shown in FIG. 3 (b), there is a possibility that the bonding wire 17 comes into contact and short-circuits. There is a problem that the wire bonding cannot be performed with a small sag (the shortest distance).

【0009】図3(c)のようにコーティングされた絶
縁膜16a,16bはろう材14をはじくが、波打った
り途切れないよう均一に厚さ50μmのコーティングを
行なうのは難しい。
The insulating films 16a and 16b coated as shown in FIG. 3 (c) repel the brazing material 14, but it is difficult to apply a uniform coating of 50 μm thickness so as not to be wavy or interrupted.

【0010】図3(d)のように溝18を設けて下から
のはい上りは防いでも、上からの流れ出しは防げない。
そのため内部整合回路(チップコンデンサ)をマウント
するときの位置ずれの原因になるという問題がある。
As shown in FIG. 3 (d), even if a groove 18 is provided to prevent a rise from below, a flow from above cannot be prevented.
For this reason, there is a problem that a position shift occurs when the internal matching circuit (chip capacitor) is mounted.

【0011】[0011]

【課題を解決するための手段】本発明の半導体装置は、
放熱板の一主面上にマイクロ波帯用半導体チップ搭載部
を囲んで、上面に絶縁膜を形成した前記チップのマウン
トろう材流れ防止側壁が形成され、前記ろう材流れ防止
側壁の外側に入力側および出力側に対応した内部整合回
路が形成され、前記半導体チップおよび前記内部整合回
路が前記放熱板の一主面を覆うキャップによって封止さ
れたものである。
According to the present invention, there is provided a semiconductor device comprising:
On one main surface of the heat radiating plate, a mounting brazing material flow preventing side wall of the chip having an insulating film formed on the upper surface is formed so as to surround the microwave band semiconductor chip mounting portion, and an input is provided outside the brazing material flow preventing side wall. An internal matching circuit corresponding to the side and the output side is formed, and the semiconductor chip and the internal matching circuit are sealed with a cap covering one main surface of the heat sink.

【0012】[0012]

【実施例】本発明の第1の実施例について、図1(a)
の平面図およびそのA−B断面図である図1(b)を参
照して説明する。
FIG. 1 (a) shows a first embodiment of the present invention.
This will be described with reference to a plan view of FIG.

【0013】銅などからなる放熱効果および導電性の優
れた放熱板1上に半導体チップであるトランジスタ7を
マウント(搭載)するための突起12が設けられてい
る。ろう材11の流れ防止用に幅0.15mm、高さ5
0μmの側壁10a,10bの上に絶縁膜9a,9bが
形成されている。幅0.15μm、高さ20μmの絶縁
膜9a,9bは液化したテフロンまたはシリコーンを刷
毛塗りによりコーティングすることができる。
A projection 12 for mounting the transistor 7 as a semiconductor chip is provided on the heat dissipation plate 1 made of copper or the like and having excellent heat dissipation effect and conductivity. 0.15 mm width and 5 height to prevent the flow of brazing material 11
Insulating films 9a and 9b are formed on 0 μm side walls 10a and 10b. The insulating films 9a and 9b having a width of 0.15 μm and a height of 20 μm can be coated with liquefied Teflon or silicone by brush coating.

【0014】トランジスタ7の入力側および出力側に
は、それぞれ誘電体4c,4dが取り付けられている。
入力側の誘電体4c上には入力側内部整合回路8aを形
成し、出力側の誘電体4d上には出力側内部整合回路8
bを形成する。
On the input side and output side of the transistor 7, dielectrics 4c and 4d are attached, respectively.
An input side internal matching circuit 8a is formed on the input side dielectric 4c, and an output side internal matching circuit 8a is formed on the output side dielectric 4d.
b is formed.

【0015】トランジスタ7の入力側および出力側に
は、容器側壁2を貫通してそれぞれ誘電体4a,4b,
4e,4fを形成し、その上にリード引出電極6a,6
bを形成する。リード引出電極6a,6bは整合回路8
a,8bに対応して容器側壁2の内側で金線からなるボ
ンディングワイヤ3c,3dで電気的に接続する。
On the input side and the output side of the transistor 7, dielectrics 4a, 4b,
4e and 4f are formed, and lead extraction electrodes 6a and 6f are formed thereon.
b is formed. The lead extraction electrodes 6a and 6b are connected to the matching circuit 8
Electrical connection is made by bonding wires 3c and 3d made of gold wires inside the container side wall 2 corresponding to a and 8b.

【0016】それぞれのリード引出電極5a,5bの容
器側壁2の外側にはリード電極6a,6bがろう付けさ
れている。容器側壁2とリード引出電極5a,5bとの
間はそれぞれ誘電体4g,4hで絶縁している。
The lead electrodes 6a and 6b are brazed to the outside of the container side wall 2 of each of the lead extraction electrodes 5a and 5b. The space between the container side wall 2 and the lead extraction electrodes 5a and 5b is insulated by dielectrics 4g and 4h, respectively.

【0017】つぎに本発明の第2の実施例について図2
を参照して説明する。
Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

【0018】本実施例は半導体チップであるトランジス
タ7を2個実装したもので、トランジスタ7間のろう材
の流れを防ぐため、絶縁膜9a,9bと9cとが同時に
コーティングされている。
In this embodiment, two transistors 7 which are semiconductor chips are mounted, and insulating films 9a, 9b and 9c are simultaneously coated to prevent the flow of brazing material between the transistors 7.

【0019】[0019]

【発明の効果】半導体チップであるトランジスタをマウ
ントするための、突起部の金属導体からなる側壁を低く
して、その上に絶縁膜をコーティングした。その結果ボ
ンディングワイヤが容器の金属導体と電気的に接触して
ショートする恐れがなくなり、流れたろう材を絶縁膜で
はじいて防ぐことができる。
According to the present invention, the side wall made of a metal conductor at the protrusion for mounting a transistor as a semiconductor chip is lowered, and an insulating film is coated thereon. As a result, there is no danger that the bonding wire will make electrical contact with the metal conductor of the container and cause a short circuit, and the flowing brazing material can be prevented from being repelled by the insulating film.

【0020】コーティングにより最小幅0.15μm、
最低高さ20μmの薄い絶縁膜を容易に形成することが
できる。
The minimum width is 0.15 μm by coating,
A thin insulating film having a minimum height of 20 μm can be easily formed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)は本発明の第1の実施例を示す断面図で
ある。(b)は(a)のA−B断面図である。
FIG. 1A is a cross-sectional view showing a first embodiment of the present invention. (B) is AB sectional drawing of (a).

【図2】本発明の第2の実施例を示す断面図である。FIG. 2 is a sectional view showing a second embodiment of the present invention.

【図3】従来のトランジスタチップがマウントされた状
態を示す断面図である。
FIG. 3 is a cross-sectional view showing a state where a conventional transistor chip is mounted.

【符号の説明】[Explanation of symbols]

1 放熱板 2 容器側壁 3a,3b,3c,3d ボンディングワイヤ 4a,4b,4c,4d,4e,4f,4g,4h
誘電体 5a,5b リード引出電極 6a,6b リード電極 7 マイクロ波帯用トランジスタ 8a 入力用内部整合回路 8b 出力用内部整合回路 9a,9b,9c コーティングされた絶縁膜 10a,10b 側壁 11 ろう材 12 チップマウント用突起 13 側壁 14 ろう材 15 マイクロ波帯用トランジスタ 16a,16b コーティングされた絶縁膜 17 ボンディングワイヤ 18 マウントろう材流れ防止溝
DESCRIPTION OF SYMBOLS 1 Heat sink 2 Container side wall 3a, 3b, 3c, 3d Bonding wire 4a, 4b, 4c, 4d, 4e, 4f, 4g, 4h
Dielectric 5a, 5b Lead extraction electrode 6a, 6b Lead electrode 7 Transistor for microwave band 8a Internal matching circuit for input 8b Internal matching circuit for output 9a, 9b, 9c Coated insulating film 10a, 10b Side wall 11 Brazing material 12 Chip Mounting projection 13 Side wall 14 Brazing material 15 Transistor for microwave band 16a, 16b Coated insulating film 17 Bonding wire 18 Mounting brazing material flow prevention groove

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 放熱板の一主面上にマイクロ波帯用半導
体チップ搭載部を囲んで、上面に絶縁膜を形成した前記
チップのマウントろう材流れ防止側壁が形成され、前記
ろう材流れ防止側壁の外側に入力側および出力側に対応
した内部整合回路が形成され、前記半導体チップおよび
前記内部整合回路が前記放熱板の一主面を覆うキャップ
によって封止された半導体装置。
1. A mounting brazing material flow preventing side wall of a chip having an insulating film formed on an upper surface surrounding a semiconductor chip mounting portion for a microwave band on one main surface of a heat radiating plate. A semiconductor device in which an internal matching circuit corresponding to an input side and an output side is formed outside a side wall, and the semiconductor chip and the internal matching circuit are sealed with a cap covering one main surface of the heat sink.
JP3303673A 1991-11-20 1991-11-20 Semiconductor device Expired - Fee Related JP2900669B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3303673A JP2900669B2 (en) 1991-11-20 1991-11-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3303673A JP2900669B2 (en) 1991-11-20 1991-11-20 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH05206192A JPH05206192A (en) 1993-08-13
JP2900669B2 true JP2900669B2 (en) 1999-06-02

Family

ID=17923855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3303673A Expired - Fee Related JP2900669B2 (en) 1991-11-20 1991-11-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2900669B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4895777B2 (en) * 2006-01-27 2012-03-14 京セラ株式会社 WIRING BOARD FOR LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE

Also Published As

Publication number Publication date
JPH05206192A (en) 1993-08-13

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