JP2900974B2 - Phase ambiguity remover - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulation system which is resistant to noise on a communication channel by introducing a predetermined correlation into a signal column using an error correction coding technique, and particularly to 8PSK on a receiving side. The present invention relates to a phase ambiguity remover for a communication system that removes phase uncertainty that occurs when synchronously detecting a modulated wave.

[0002]

2. Description of the Related Art In a conventional digital communication system, modulation and error correction coding functions are separately designed.
Ungerbeck proposed a technique to map convolutional codes cleverly, and to create a system with a simple code and a multi-level modulation format to significantly increase the performance gain (Unge
rboech, "Channel Coding with Multilevel / phase Sign
als ", IEEE Transactions on Information Theory, vo
l. IT-28, 1982) Ungerbeck's coding approach transmits "n" user information bits per symbol coded with a rate "n / n + 1" code using a (2n + 1) -point modulated signal construction. Things. For example, a code having a coding rate of 2/3 performs 3-bit coding in order to transmit 2 information bits by an 8-phase phase shift keying (8PSK) modulator. Ungerbeck explains how to choose the code for this data format and publishes the best code for many constraint lengths. These codes differed from the classic binary convolutional codes used for traditional BPSK and QPSK modulation. Viterbi proposed that a constrained length of 7 and a coding rate of 1/2 convolutional code, which is often used as an error correction in satellite communications, can be replaced by Ungerbeck's best code with a small loss of performance. (Viterbi et al, "A Pramatic Approach toT
rellis-Coded Modulation ", IEEE Communications Maga
zine, vol. 27, 1989). The Viterbi algorithm is used as a well-known decoding method for convolutional codes (Forney, "The Vitabi Algorithm", IEEE Transacti
ons on Information Theory, vol. IT-U). Hereinafter, the method proposed by Viterbi will be described.

FIG. 3 is a diagram showing a conventional circuit proposed by Viterbi, and is a block diagram of an 8PSK coded modulation transmitting apparatus. As shown in FIG. 3, the 8PSK coded modulation transmitting apparatus includes a serial / parallel converter (hereinafter, referred to as a serial / parallel converter) 12 connected to an input terminal 11, a differential encoder 13,
A convolutional encoder 14, differential encoders 15 and 16,
It has a selector 17 and an 8PSK modulator 18 connected to an output terminal 19. These differential encoder 13, convolutional encoder 14, differential encoders 15 and 16, and selector 1
7 constitute the correction code section 6. Then, the serial / parallel converter 12 converts the input bit sequence into two types of signals of an a-bit sequence and a b-bit sequence. Differential encoder 1
3 comprises an exclusive OR circuit 21 and a register 22;
A differential code signal c obtained by performing a differential operation on the bit sequence signal is output. The convolutional encoder 14 performs convolutional encoding on the differential code signal c from the differential encoder 13 and outputs a convolutional encoded signal of a bit sequence of ENC0 and ENC1. The differential encoders 15 and 16 include exclusive OR circuits 23 and 25 and registers 24 and 26, respectively, and convert an a-bit sequence signal into one of two sequences according to the current output of ENC1. The differential code signal subjected to the differential is output. The selector 17 selects the selected differential encoder 15 or 1
A selection encoding signal of 6 bits ENC2 is output. 8P
The SK modulator 18 is (ENC2, ENC1, ENC0)
, And a modulated wave signal is output from the output terminal 19.

FIG. 4 is a diagram similar to that of FIG. 3 proposed by Viterbi.
FIG. 9 is a block diagram of a conventional 8PSK coded modulation receiving unit corresponding to a PKS coded modulation transmitting apparatus. As shown in FIG.
The modulation receiver includes an 8PSK demodulator 32 connected to an input terminal 31, a phase converter 33, a synchronization determination circuit 34,
A first discriminator 35, a first delay circuit 36, and a second discriminator 3
7, a second delay circuit 38, a branch metric generator 39, a Viterbi decoder 41, a differential decoder 42, a convolutional encoder 43, a first selector 44, and a pair of different differential decoders. 45 and 46, a second selector 47, and a parallel / serial converter (hereinafter, referred to as a parallel / serial converter) 48 connected to an output terminal 49. These phase converter 33, synchronization determination circuit 34, first discriminator 35, first delay circuit 36, second discriminator 37, second delay circuit 38, branch metric generator 39, Viterbi decoder 41, and differential decoder The correction decoding unit 7 includes the reference numeral 42, the convolutional encoder 43, the first selector 44, the pair of differential decoders 45 and 46, and the second selector 47. The 8PSK demodulator 32 demodulates an eight-phase phase modulated wave by synchronous detection and outputs a demodulated signal. The phase converter 33 is 8PSK
The demodulated signals (｛P ₀ , P ₁ ,...,
P _L ｝, {Q ₀ , Q ₁ ,..., Q _L ｝) ( L is an integer of 3 or more) is output as it is, or logical conversion is applied , and the vector set shown in the following equation 15 is output. Is selected according to the instruction of the control signal of the synchronization determination circuit 34.

[0005]

(Equation 15)

[0006] The first discriminator 35 outputs a first estimation signal obtained by estimating (ENC1, ENC0) from the phase conversion signal output of the phase converter 33. The first delay circuit 36 delays the first estimation signal of the 2-bit output sequence of the first discriminator 35 by an appropriate time, and outputs the result to the synchronization determination circuit 34 as a first delay signal. The second classifier 37 is (ENC1, ENC0)
Corresponding to the set (0,0) (0,1) (1,0) (1,1), and outputs a second estimated signal. The second delay circuit 38 delays the second estimation signal of the 4-bit output sequence of the second discriminator 37 by an appropriate time and outputs a second delay signal. Branch metric generator 39
Is (0,0) according to the phase conversion signal of the phase converter 33.
A branch metric signal which is a 4-series (m is an integer of 3 or more) of m branch metric corresponding to (0, 1) (1, 0) (1, 1) is output. Viterbi decoder 41
Estimates the transmission bit b based on the branch metric signal from the branch metric generator 39 and outputs a third estimated signal. The differential decoder 42 includes an exclusive OR circuit 52 and a register 51, and the third decoder of the Viterbi decoder 41
Differentially decode the estimated signal. The convolutional encoder 43 outputs a re-encoded signal obtained by re-encoding the third estimated signal of the Viterbi decoder 41. The selector 44 is connected to the second delay circuit 38
And the output of the re-encoded signal of the convolutional encoder 43 (0,0) (0,1) (1,
0) The one corresponding to the set of (1, 1) is selected and output as a selection signal. The differential decoders 45 and 46 include exclusive OR circuits 54 and 56 and registers 53 and 55, respectively.
According to one output of the re-encoded signal from the convolutional encoder 43, the selection signal output bit sequence of the selector 44 is
Apply differential in one of the two series. The selector 47 outputs the bit of the selected differential encoder. Parallel-to-serial converter 4
8 converts the differential signal from the selector 47 and the differential decoded signal from the differential decoder 42 from parallel to serial and outputs them from an output terminal 49.

Next, the operation of the conventional 8PSK coded modulation communication system will be specifically described.

Referring to FIG. 3, a bit sequence input from input terminal 11 is converted by a serial-to-parallel converter 12 into a (n) and b (b).
(n) are separated into a 2-bit sequence. This b (n) sequence is subjected to the following differential encoding. B (n) at the current time
Is subjected to an exclusive OR operation with the output c (n-1) of the exclusive OR circuit 21 one time earlier, and the differentially coded signal c (n) as the operation result is stored in the register 22. You. The differentially coded signal of the c (n) sequence is converted by the convolutional encoder 14 into
A convolutional code with a coding rate of 1/2 and a constraint length of 7 is applied,
The convolutional encoded signal ENC0 shown in the following equation ( 16 )
And ENC1 are output.

[0009]

(Equation 16)

Here, the logical sum circuit + performs the operation of MOD2. The thing to note here is $ ENC0 (n)
, ENC1 (n)} is a code sequence (convolutional encoder 14
Is a matter of course, but the following equation 1
The expression shown in Expression 7 is also a code sequence, and the input of the convolutional encoder 14 when this sequence is output is that shown in Expression 18 below.

[0011]

[Equation 17]

[0012]

(Equation 18)

On the other hand, the a (n) series is the convolutional encoder 1
5, differential encoding is performed by a differential encoder 15 or 16 selected according to ENC1 which is one of the convolutional encoded signal outputs, and a differential code selected from among these differential encoders The selector 17 outputs the selected encoded signal from the selector 17. The inside of the differential encoders 15 and 16
Exclusive OR circuit 2 having the same configuration as differential encoder 13
3 and 25, and registers 24 and 26.
The set of (ENC2, ENC1, ENC0) is 8P in FIG.
8PSK modulation is performed by the 8PSK modulator 18 according to the encoder output mapping point for SK modulation, and this modulated wave signal is output from the output terminal 19.

Referring to FIG. 4, in the receiving apparatus, a modulated wave is input from input terminal 31, and synchronous detection is performed by 8PSK demodulator 32 to obtain received data as a demodulated signal.

Here, in the case of a communication system using 8PSK without an absolute phase reference like a conventional communication system, the phase of the modulator and the phase of the demodulator are different, and phase ambiguity occurs. Therefore, data must be decoded while removing this phase ambiguity. 8PSK
In the case of modulation, an uncertainty of 45 ° × k (an integer of 0 ≦ k ≦ 7) occurs due to a difference in the phase of the reference carrier between the transmitting device and the receiving device. In this conventional method, the Viterbi decoder 41
Can first remove the uncertainties of 90 °, 180 °, and 270 °. Here, consider the case where (0, 0, 0) is used as a reference. At 90 °, (0, 1, 1) is a state in which the transmitted code sequence is all inverted, and for this reason is also a code sequence, and the Viterbi decoder 41 becomes decodable and the convolution of the transmission device is performed. The output of the encoder 14 is obtained by inverting the entire input sequence. Since differential coding is performed before the convolutional encoder 14, if the Viterbi decoded signal output of the Viterbi decoder 41 is differentially decoded by the differential decoder 42, a correct estimated sequence b as a differential decoded signal is obtained.
(n) is obtained.

At 180 °, (1, 0, 0) becomes
Since it is the same code sequence as the transmitted code sequence, it is equal to 0 °. At 270 °, (1,1,1) is the same process as at 90 °. Next, the remaining 45 °, 135 ° 225 °
The uncertainty of 315 ° can be removed by logically converting the output (P, Q) of the demodulated signal of the 8PSK demodulator 32 as shown in the following equation ( 19 ).

[0017]

[Equation 19]

Control of (P, Q) and the output expressed by the above equation ( 19 ) is performed by a synchronization determination circuit 34. For the synchronization determination circuit 34, refer to the references (Yasuda et al.,
“Study on Code Synchronization Method in Vidabi Decoding”,
It uses the method of re-encoding the decoded data and checking the correlation with the received data as described in IEICE Technical Report, Communication System, cs82-1982). That is, the first classifier 35
The estimated data represented by the following equation (20) restored by the above is adjusted by the first delay circuit 36 by the decoding delay of Viterbi decoding and the delay generated by the convolutional code, and this first delayed signal is input to the synchronization determination circuit 34. Similarly, the Viterbi decoder 41
Is re-encoded by the convolutional encoder 43 to obtain a re-encoded signal represented by the following equation (21).
Enter 4

[0019]

(Equation 20)

[0020]

(Equation 21)

The synchronization determination circuit 34 matches the two sets of data whose times coincide with each other for a certain section, and determines synchronous or asynchronous according to whether the degree of coincidence is smaller or larger than a predetermined threshold. ing. If it is determined to be asynchronous,
A control signal is output so as to output another phase to the phase converter 33. Although the phase uncertainty for the sequence represented by the following Expression 22 has been removed, the phase uncertainty of 90 °, 180 °, and 270 ° for the remaining sequence represented by Expression 23 is removed.

[0022]

(Equation 22)

[0023]

(Equation 23)

The second discriminator 37 decodes a 4-bit set which is a candidate for estimation data represented by the following equation (24) to obtain a second estimation signal.

[0025]

(Equation 24)

For example, it is assumed that the output of the 8PSK demodulator 32, that is, the receiving point is at the point r in the 0 selector on the PQ plane shown in FIG. At this time, A = ｛(0,0,
0), (1, 0, 0)}, B = {(0, 0, 1),
(1,0,1)}, C = {(0,1,1), (1,1,1)
1) 4 of {, D = {(0, 1, 0), (1, 1, 0)}
Consider group A, and, for group A, compare the Euclidean distance between transmission point (0,0,0) and reception point r and the Euclidean distance between transmission point (1,0,0) and reception point r and find the smaller one. It is a candidate represented by the following equation ( 25 ). Here, it becomes as shown by Formula 26 .

[0027]

(Equation 25)

[0028]

(Equation 26)

Hereinafter, when the same operation is performed for the sets B, C, and D, the following equations (27), (28), and (29) are obtained.

[0030]

[Equation 27]

[0031]

[Equation 28]

[0032]

(Equation 29)

A set of (i, j) in the following equation ( 30 ) represents 2 bits of the re-encoded signal output of the convolutional encoder 43.

[0034]

[Equation 30]

The data sequence c (n) estimated by the Viterbi decoder 41 outputs a re-encoded signal of a set of 2 bits which is convolutionally coded by the convolutional coder 43 again. The 2-bit pair (i, j) is represented by the following Expression 31 Expression adjusted delayed by the first delay circuit 36 4
The corresponding bit among the bits is output from the selector 44 as a selection signal.

[0036]

(Equation 31)

In the transmitting apparatus, the fact that the signal is differentially encoded by one of the two differential encoders by the ENC1 means that the uncertainty of 180 ° can be removed by each differential code, This means that the phase uncertainties of °, 180 °, and 270 ° have been removed. The selection signal output of the selector 44 is subjected to differential decoding to one of the differential decoders 45 and 46 in accordance with the bit of the current time represented by the following equation 32 , and is output as a differential signal. The differential decoders 45 and 46 are configured such that exclusive OR circuits 54 and 56 take the exclusive OR of the outputs of the registers 53 and 55 which hold the data at the current time and the data at one time before. Has become. The bit selected by the differential decoders 45 and 46 is output from the selector 47 as a differential signal. The following equation 32 of the estimated data in this differential signal
The series represented by the expression and Expression 33 is subjected to parallel / serial conversion by the parallel / serial converter 48 and output from the output terminal 49.

[0038]

(Equation 32)

[0039]

[Equation 33]

[0040]

However, when the sequence of the selected coded signal ENC2 (n) is expressed by the following equation ( 34 ), on the receiving side, the data of the estimated equation ( 35) is converted to the above (n + 2) Up to the time)
At the time of (n + 3), the error is changed from “0” to “1”,
+4) After that, if it is correct, the data series represented by the following equation ( 36 ) after differential decoding is represented by the following equation ( 37) , and the estimation of the data represented by the following equation ( 38 ) is incorrect by one bit. For example, the estimated data represented by the following Expression 39 is data a (n + 3), a (n +
4), a (n + 5) and a (n + 6) are erroneous.

[0041]

(Equation 34)

[0042]

(Equation 35)

[0043]

[Equation 36]

[0044]

(37)

[0045]

(38)

[0046]

[Equation 39]

Therefore, the conventional phase ambiguity remover has a problem that the error is increased and the bit error rate of the transmission path is deteriorated.

Therefore, the technical problems of the present invention are, for example,
One of the two information bits is convolutionally coded with a coding rate of 1/2 constraint length 7, and the three coded bits are combined with the remaining non-coded bits using PSK modulation such as 8PSK coded modulation. Provided is a phase ambiguity remover capable of performing correct data transmission by removing a phase uncertainty caused by a difference in a phase reference from a transmitting device in a receiving device, and a transmitting device and a receiving device using the same. Is to do.

[0049]

A phase ambiguity remover according to the present invention comprises: a serial-to-parallel converter for serially converting a bit sequence into a (n) and b (n) sequences on the transmitting side; ) The sequence is differentially encoded, and convolutionally encoded signal E
A code that outputs the NC0 (n) and ENC1 (n) sequences and outputs a coded signal ENC2 that performs differential coding on the a (n) sequence in the direction specified by the value of ENC1 (0 or 1). A correction unit, and a PSK modulator that performs a phase modulation corresponding to a set of the convolutional coded signal and the coded signal (ENC0, ENC1, ENC2) and outputs a modulated wave signal. PSK demodulator for synchronous detection and demodulation, and L-bit outputs P and Q of PSK demodulator
Or a phase converter that outputs as a phase modulation signal by replacing the L-bit outputs P and Q, a synchronization determination circuit that outputs a control signal for controlling this phase converter, and an output of the phase converter. A first discriminator for restoring the estimated data of ENC0 and ENC1 and outputting a first estimated signal, and a delay circuit for delaying the first estimated signal of the first discriminator and outputting it as a first delayed signal to the synchronization determination circuit And (0,0) (0,1) (1,0) (1,
A branch metric generator that generates a branch metric signal composed of four sets of branch metrics corresponding to 1), a Viterbi decoder that executes a Viterbi algorithm based on the branch metric generation signal and outputs a Viterbi decoded signal, and the Viterbi decoding A convolutional encoder for re-encoding the signal and outputting it as a re-decoded signal to the synchronization determination circuit, and a second discriminator for restoring four candidate bits of the following equation 40 based on the phase conversion signal: the second delay circuit and, following several 41 four second delay signal output of the second delay circuit based on the re-coded signal to output a second delayed signal by delaying the output of the second discriminator a selector for outputting a selection signal to select the bit corresponding to the formula, the value of those shown the selection signal by the following expression 42 formula (0 or 1) Outputs a differential signal performs differential decoding in the way that is constant, and the differential decoding unit for outputting a differential decoding signal sequence represented the Viterbi decoded signal by the following formula 43, the differential decoding And a parallel-to-serial converter for performing parallel-to-serial conversion on the output of the section, the differential encoding section performs the n-time conversion of the two serial-to-parallel converted sequences for the purpose of removing the ambiguity of ENC2. Of the value I _{n, 2} ,
In _{n, 1} is processed by the following equation ( 44) , and after operation I ′
_{n, 2} , I ′ _{n, 1,} and the differential decoding unit is configured to remove the ambiguity of ENC2 and to provide a value J _{n, 2} of the output sequence of the selector at time _n and a Viterbi decoder. N of the output sequence of
Treated represented by the following formula 45 to a value J _{n, 1} of the two sequences of time, the post-operation _{J'n, 2,} as characterized by comprising a differential decoder to obtain the J'n, ₁ I have.

[0050]

(Equation 40)

[0051]

[Equation 41]

[0052]

(Equation 42)

[0053]

[Equation 43]

[0054]

[Equation 44]

[0055]

[Equation 45]

[0056]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an 8PSK coded modulation transmission apparatus according to an embodiment of the present invention. In the following description, portions having the same names as those in the conventional example are denoted by the same reference numerals. As shown in FIG. 1, an 8PSK coded modulation transmitting apparatus 1
0 is the serial-parallel converter 12 connected to the input terminal 11,
An operation encoder 13, a convolutional encoder 14, and an 8PSK modulator 18 connected to an output terminal 19 are provided.
The operating encoder 13 and the convolutional encoder 14 constitute a correction encoder 8.

FIG. 2 is a block diagram of an 8PSK coded modulation receiving apparatus according to an embodiment of the present invention. As shown in FIG. 2, an 8PSK demodulator 32 connected to an input terminal 31, a phase converter 33, a synchronization determination circuit 34, and a first discriminator 35
, A first delay circuit 36, a second discriminator 37, a second delay circuit 38, a branch metric generator 39, a Viterbi decoder 41, a differential decoder 42, and a convolutional encoder 4
3, a selector 44, and a parallel / serial converter 48 connected to an output terminal 49. These phase converters 33
, Synchronization determination circuit 34, first discriminator 35, and first delay circuit 3
6, a second discriminator 37, a second delay circuit 38, a branch metric generator 39, a Viterbi decoder 41, and an operation decoder 42
Constitute the correction decoding unit 9.

Next, the operation of the transmitting apparatus of the communication system according to the embodiment of the present invention will be described. Referring to FIG.
The bit sequence input from the input terminal 11 is separated by the serial-parallel converter 12 into a (n) and b (n) sequences.
If (a, b) = (In _{, 2} , In _{, 1} ), then (In _{, 2} , In,
I _{n, 1} ) is subjected to an operation represented by the following equation ( 46 ) by the differential encoder 13 and outputs a convolutionally encoded signal. Table 1 below shows what values the convolutional coded signal represented by the following equation 49 takes according to the following equations 47 and 48 .

[0059]

[Equation 46]

[0060]

[Equation 47]

[0061]

[Equation 48]

[0062]

[Equation 49]

[0063]

[Table 1]

The output sequence represented by the following equation ( 50 ) is input to the convolutional encoder 14 and becomes a sequence of encoded convolutional encoded signals ENC1 (n) and ENC0 (n).

[0065]

[Equation 50 ]

As expressed by the following equation ( 51 ), the modulated wave signal phase-modulated by the 8PSK modulator 18 at the transmission point corresponding to the set of (ENC2, ENC1, ENC0) as shown in FIG. 19 is output.

[0067]

(Equation 51)

Next, the operation of the receiving device of the communication system according to the embodiment of the present invention will be described. Referring to FIG.
On the receiving side, the modulated wave signal input from the input terminal 31 is synchronously detected by the 8PSK demodulator 32, and L-bit P and Q data are obtained as a demodulated signal. The phase converter 33 generates ｛(P ₀ , P ₁ ,..., P _L ),
_{(Q 0, Q 1, ...} , Q L) is output as a pair or pairs or phase conversion signal one of which is shown below the number 52 Expressions}. According to the phase conversion signal output of the phase converter 33, the first
The discriminator 35 restores the estimated data expressed by the following Expressions 53 and 54 to generate a first estimated signal.

[0069]

(Equation 52)

[0070]

(Equation 53)

[0071]

(Equation 54)

For example, as shown in FIG.
If it is within sector 0 on the Q plane, it is expressed by the following equation ( 55) .

[0073]

[Equation 55 ]

The output of the first estimated signal of the first discriminator 35 is input to a first delay circuit 36 which adjusts the delay required for Viterbi decoding and the delay required for the convolutional code.
Is output to the synchronization determination circuit 34.
Further, by the transfer conversion signal output of the phase converter 33, (E
The transmission symbol of (NC1, ENC0) is (0, 0) (0, 0,
1) m indicating the degree of certainty that is the case of (1, 1)
The branch metric generator 39 generates four bit branch metrics. Using the obtained four branch metrics, the Viterbi algorithm is executed in the Viterbi decoder 41 to obtain a decoded data sequence J _{n, 1} (n). The decoded data sequence J _{n, 1} (n) is obtained by the convolution encoder 43 to obtain a re-encoded signal of the convolution encoded sequence represented by the following Expressions 56 and 57, and is output to the synchronization determination circuit 34.

[0075]

[Equation 56]

[0076]

[Equation 57]

Here, the synchronization determination circuit 34 matches the two sets of data represented by the following equations ( 58 ) and ( 59 ) whose times coincide with each other for a fixed section, and determines whether the synchronization is smaller or larger than the threshold. Asynchronous is determined, and the result is output as a control signal.

[0078]

[Equation 58]

[0079]

[Equation 59]

When the synchronization is determined by the synchronization determination circuit 34 to be asynchronous, a control signal is output so that the phase converter 33 outputs another phase. Further, based on the output of the phase converter 33, the second discriminator 37 decodes a 4-bit set which is a candidate represented by the following equation 60 and outputs a second estimated signal.

[0081]

[Equation 60]

For example, as shown in FIG.
Suppose that it was in sector 0 on the Q plane. At this time,
{(0,0,0), (1,0,0)}, B = {(0,
0,1), (1,0,1)}, C = {(0,1,1),
(1,1,1)｝, D = ｛(0,1,0), (1,1,1)
0) Considering 4 sets,｝, and for set A, the transmission point (0, 0,
0) and the Euclidean distance between the receiving point r and the transmitting point (1,
(0, 0) and the Euclidean distance between the reception point r and the smaller one is a candidate represented by the following equation (61), which is represented by the following equation (62).

[0083]

[Equation 61]

[0084]

(Equation 62)

[0085] Similarly B, C, performed the same operation with respect to Group D becomes as shown by the number 63 formula below.

[0086]

[Equation 63]

A set of (i, j) in the following equation ( 64 ) represents a 2-bit re-encoded signal output of the convolutional encoder 43.

[0088]

[Equation 64]

Therefore, the following equation ( 66 ) corresponding to the set of (i, j) whose delay has been adjusted by the second delay circuit 38 that matches the 2-bit output of the convolutional encoder 43 shown in the following equation ( 65 ) The second delay signal to be output is
And the estimated bit of the corresponding time represented by the following equation ( 67) .

[0090]

[Equation 65]

[0091]

[Equation 66]

[0092]

[Equation 67]

Viterbi decoded signal output J of Viterbi decoder 41
_{n, 1} and the selection signal output J _{n, 2} of the selector 44 are subjected to an operation represented by the following equation 68 by the differential decoder 42,
These are output as a differential decoded signal and a differential signal, respectively. Table 2 below shows combinations of Viterbi decoded signals and selection signals (J _{n, 2} , J
_{n, 1} ) and the combination of the differential decoded signal and the differential signal (J _n-1,2 , J _n-1,1 ) indicate what value is given by the following equation ( 68 ). ing.

[0094]

[Equation 68]

[0095]

[Table 2]

The differential decoded signal and differential signal output of the differential decoder 42 expressed by the following equation (69) are subjected to parallel / serial conversion by the parallel / serial converter 48 and output from the output terminal 49.

[0097]

[Equation 69]

[0098]

As described above, according to the present invention, in the 8PSK coded modulation communication system proposed by Viterbi,
On the transmitting side, for the purpose of removing the ambiguity of ENC2, for the purpose of removing the ambiguity of ENC2 on the receiving side, a differential code for performing the processing represented by the following equation ( 70) on the serial-to-parallel converted sequence of 2 by performing the differential decoding for performing the processing shown in the two series of output sequence and the output sequence of the Viterbi decoder of the selector by the following expression 71 expression in, for example, the following number of times n 7
Even when either one represented by the two equations is false, the output of the differential transducer time n (n + 1) by an error, without affecting the other time, prevent the deterioration of the bit error rate as compared with the conventional circuit effects There is.

[0099]

[Equation 70]

[0100]

[Equation 71]

[0101]

[Equation 72]

[Brief description of the drawings]

FIG. 1 is a block diagram of an 8PSK coded modulation transmission apparatus including a phase ambiguity remover according to an embodiment of the present invention.

FIG. 2 is a block diagram of an 8PSK coded modulation receiving apparatus including a phase ambiguity remover according to an embodiment of the present invention.

FIG. 3 is a block diagram of an 8PSK coded modulation transmission apparatus according to a conventional example.

FIG. 4 is a block diagram of an 8PSK coded modulation receiving apparatus according to a conventional example.

FIG. 5 is an encoder output mapping diagram for 8PSK modulation.

[Explanation of symbols]

Reference Signs List 10 8PSK coded modulation transmitter 11, 31 Input terminal 12 Serial-to-parallel converter 13, 15, 16 Differential coder 14, 43 Convolutional coder 18 8PSK modulator 19, 49 Output terminal 20 8PSK coded modulation receiver 21, 23, 25, 52, 54, 56 Exclusive OR circuit 22, 24, 26, 51, 53, 55 Register 32 8PSK demodulator 33 Phase converter 34 Synchronization judgment circuit 35 First discriminator 36 First delay circuit 37 2 discriminator 38 second delay circuit 39 branch metric generator 41 Viterbi decoder 42 differential decoder 44 selector 45, 46 differential decoder 48 parallel-serial converter

Claims (7)

(57) [Claims] A transmitting side separates an input first bit sequence into second and third bit sequences, convolutionally encodes the third bit sequence, and converts fourth and fifth bit sequences. A modulated signal generated and modulated to a phase determined according to a set of 3 bits bundled at each time of the second, fourth, and fifth bit sequences is output. The demodulated modulated wave is demodulated by synchronous detection.
One of a signal (P, Q) obtained by phase-converting the two-phase 1-bit demodulated signals P and Q based on the control signal and a signal represented by the following equation (1) is obtained as a phase-converted signal. A first estimation signal that estimates the fourth and fifth bit sequences is generated from the phase conversion signal, a first delay signal is generated by delaying the first estimation signal, and based on the phase conversion signal. Generate a branch metric, execute the Viterbi algorithm to generate a Viterbi decoded signal,
Generating an estimated signal obtained by re-encoding the Viterbi decoded signal;
This estimated signal and the first delay signal are associated with each other for a certain section, and the relationship between the degree of coincidence between the two and a predetermined threshold value is expressed as follows.
The control signal is generated by determining whether the two signals are synchronous or asynchronous, and the four candidate bits of the third bit sequence are estimated based on the control signal to generate a second estimated signal. Delaying the signal to generate a second delayed signal,
Based on the estimated signal, a selection signal is generated by selecting one bit from the second delay signal, and the selected signal and the Viterbi decoded signal are calculated and parallel-serial converted based on a predetermined calculation. In the communication method, on the transmitting side, the value of n time of the second and first bit strings is In _{, 2} , In _{, 1} (where In _{, 2} , In _{, 1} is 0 or 1). When the output after the operation is I'n _{, 2} and I'n _{, 1} , the operation shown in the following equation 2 is performed, and the value of the selection signal at time _{n is Jn, 2} , the Viterbi decoded signal is J _{n, 1,} and the output after the operation is J ′ _{n, 2} , J
_{'N, 1 (where, J n, 2, J n} , 1, J'n, 2, J'n, 1 is 0 or 1) when the, that straining facilities the operation represented by the equation (3) below A method for removing phase ambiguity in a communication system. (Equation 1) (Equation 2) (Equation 3) 2. An input first bit sequence is separated into a second and a third bit sequence, and the third bit sequence is convolutionally encoded to generate fourth and fifth bit sequences. The transmission method of a communication system for outputting a modulated wave signal modulated to a phase determined according to a set of 3 bits bundled at each time of the second, fourth, and fifth bit sequences, The values at time n of the second and first n-bit strings are set to I _{n, 2} , I _{n, 1,} and the outputs after the operation are I ′ _{n, 2} , I ′
A transmitting-side phase ambiguity removing method, wherein an operation represented by the following Expression 4 is performed when _{n, 1} is set. (Equation 4) 3. A demodulated signal transmitted by the transmitting-side phase ambiguity elimination method according to claim 2 is demodulated by synchronous detection, and a 2-phase 1-bit demodulated signal P, Q is converted to a control signal at each time. One of the signal (P, Q) obtained by phase conversion based on the following equation and a signal expressed by the following equation (5) is obtained as a phase conversion signal, and the fourth and fifth bit sequences are estimated by the phase conversion signal. A first estimated signal is generated, a first delayed signal obtained by delaying the first estimated signal is generated, a branch metric is generated based on the phase conversion signal, and a Viterbi decoding signal is generated by executing a Viterbi algorithm. Convoluting the Viterbi decoded signal to generate a re-encoded signal, associates the re-encoded signal with the first delay signal for a certain period, and sets the degree of coincidence between them and a predetermined threshold value. The relationship between the two The control signal is generated by judging whether or not the control signal is out of synchronization, and based on the control signal, four candidate bits of the third bit sequence are estimated to generate a second estimation signal, and the second estimation signal is delayed. Communication for generating a second delayed signal, generating a selection signal by selecting one bit from the second delayed signal based on the re-encoded signal, and performing parallel-to-serial conversion between the selection signal and the Viterbi signal In the receiving method of the system, the value of the selection signal at time _n is J _{n, 2} , the Viterbi decoded signal is J _{n, 1,} and the output after the operation is J ′ _{n, 2} , J
_{'N, 1 (where, J n, 2, J n} , 1, J'n, 2, J'n, 1 is 0 or 1) when the, that straining facilities the operation represented by the equation (6) below Characteristic receiving-side phase ambiguity removal method. (Equation 5) (Equation 6) 4. A communication system comprising a transmitting device and a receiving device, the transmitting device comprising: a serial / parallel converter for separating an input first bit sequence into second and third bit sequences; A differential encoding unit that performs a predetermined operation on the second and third bit sequences, and convolutionally encodes the third bit sequence that has been subjected to the operation to convolve the fourth and fifth bit sequences. A first convolutional encoder that outputs a signal, and a set of three bits that are bundled at each time of the second bit sequence subjected to the operation and the fourth and fifth bit sequences. And a PSK modulator for outputting a modulated wave signal modulated to a predetermined phase, wherein the receiving device is a two-phase modulator that demodulates the input modulated wave signal by synchronous detection.
A PSK demodulator that generates a demodulated signal of bits, a signal (P, Q) obtained by performing phase conversion at each time based on the control signal, where P and Q are the demodulated signals, and A phase converter that obtains one of the signals represented by the following as a phase modulation signal, and the fourth and fifth signals from the phase conversion signal.
A first discriminator for generating a first estimation signal obtained by estimating the bit sequence, a first delay circuit for generating a first delay signal obtained by delaying the first estimation signal, and a A branch metric generator that generates a branch metric; a Viterbi decoder that executes a Viterbi algorithm based on the branch metric to output a Viterbi decoded signal; and generates a re-encoded signal obtained by re-encoding the Viterbi decoded signal. A second convolutional encoder, and the re-encoded signal and the first delay signal are associated with each other for a certain period, and whether synchronous or asynchronous is determined depending on whether the coincidence between the two is smaller or larger than a predetermined threshold. A synchronization determination circuit for generating the control signal, a second discriminator for generating a second estimation signal that estimates four candidate bits of the third bit sequence based on the control signal, A second delay circuit for outputting a second delay signal obtained by delaying the second estimation signal, and selecting one bit from four outputs of the second delay signal based on the re-encoded signal to generate a selection signal A differential decoding unit that performs a predetermined operation on the selection signal and the Viterbi decoded signal to output a differential signal and a differential decoded signal;
In a communication system using PSK modulation, comprising a parallel-serial converter for parallel-to-serial conversion of the differential signal and the differential decoded signal, the differential encoding unit performs the n-th time conversion of the second and first bit strings. The values of In _{, 2} , In _{, 1} (where In _{, 2} , I
_{n, 1} is 0 or 1), and the output after the operation is I'n _{, 2} , I '
_{n, 1} (where I ′ _{n, 2} , I ′ _{n, 1} is 0 or 1), a differential encoder that performs an operation represented by the following equation 8 is provided. The value of the selection signal at time n is represented by J
_{Let n, 2} and the value of the Viterbi signal be J _{n, 1,} and output the computed values as J ′ _{n, 2} , J ′ _{n, 1} (where J _{n, 2} , J _{n, 1} , J ′)
A phase ambiguity remover comprising a differential decoder for performing an operation represented by the following equation (9) when _{n, 2} and J'n _{, 1} are 0 or 1). (Equation 7) (Equation 8) (Equation 9) 5. A serial / parallel converter for separating an input first bit sequence into second and third bit sequences,
And a differential encoding unit that performs a predetermined operation on the third bit sequence, and a first encoding unit that convolutionally encodes the operated third bit sequence and outputs fourth and fifth bit sequences. A convolutional encoder modulates a phase determined according to a set of three bits bundled at each time of the second bit sequence and the fourth and fifth bit sequences subjected to the operation. In a transmitting apparatus of a communication system using PSK coded modulation including a PSK modulator, the differential encoding unit outputs the output of the serial-to-parallel converter at time _{n to In, 2} , In _{, 1.}
(However, I _{n, 2} , I _{n, 1} is 0 or 1), and the output after the operation is I ′ _{n, 2} , I ′ _{n, 1} (where I ′ _{n, 2} , I ′ _{n, 1} is A transmission-side phase ambiguity remover characterized by comprising a differential encoder that performs an operation represented by the following equation (10) when 0 or 1) is set. (Equation 10) 6. A modulated wave transmitted from the transmitting-side phase ambiguity remover according to claim 5 and demodulated by synchronous detection.
8 PSK demodulator, and signals (P, Q) obtained by performing phase conversion of two-phase 1-bit demodulated signals P and Q output from the 8PSK demodulator based on a control signal at each time, and 11 A phase-converted signal obtained by switching one of the signals represented by the equations is obtained, and fourth and fifth signals are obtained based on the phase-converted signal.
A first discriminator for estimating the bit sequence of the first estimated signal to generate a first estimated signal; a first delay circuit for delaying the first estimated signal to generate a first delayed signal; A branch metric generator for generating a branch metric based on the branch metric, a Viterbi decoder for generating a Viterbi decoded signal by executing a Viterbi algorithm based on the branch metric, and generating a re-encoded signal obtained by re-encoding the Viterbi decoded signal A second convolutional encoder that performs synchronization and non-synchronization depending on whether the degree of coincidence is smaller than or larger than a threshold by matching the re-encoded signal with the first delay signal for a certain section to generate a control signal A synchronization determination circuit, a second discriminator for generating a second estimation signal based on the control signal, and estimating four candidate bits of the third bit sequence,
A second delay circuit for generating a second delay signal obtained by delaying the estimated signal, and a selection signal generated by selecting one bit from four outputs of the second delay signal based on the value of the re-encoded signal; A selector, a differential decoding unit that performs a predetermined operation on the selection signal and the Viterbi decoded signal to generate a differential signal and a differential decoded signal, and performs parallel-to-serial conversion on the differential signal and the differential decoded signal In a receiving apparatus of a communication system using PSK coded modulation including a parallel-to-serial converter, the differential decoding unit sets the value of the selection signal at time _n to J _{n, 2} and the value of the Viterbi signal to J _{n, 1} and the output after the operation is J ′ _{n, 2} ,
J ' _{n, 1} (however, J _{n, 2} , J _{n, 1} , J' _{n, 2} , J ' _{n, 1}
Where 0 or 1) is a differential decoder that performs an arithmetic process represented by the following equation (12). [Equation 11] (Equation 12) 7. A differential encoder which is provided between a serial-to-parallel converter and a PSK modulator of a transmitting device and performs a differential on a specific bit sequence of a signal from the serial-to-parallel converter. The convolution-encoded specific bit sequence that has been subjected to the motion, and the P sequence together with a bit sequence signal other than the specific bit sequence.
A Viterbi-decoded signal is provided between a correction code unit to be output to the SK modulator and a parallel-to-serial converter and a PSK demodulator of the receiving device. A Viterbi decoder to generate the signal, a convolutional encoder to generate a re-encoded signal by convolutionally re-encoding the Viterbi decoded signal, and estimating the specific bit string signal based on the re-encoded signal from the convolutional encoder. And a differential decoder for performing a predetermined operation on the estimated signal obtained by estimating a bit sequence other than the specific bit sequence and the Viterbi decoded signal. In the phase ambiguity remover provided with a correction decoding unit, the differential encoder outputs the output of the serial-parallel converter at time _{n to In, 2} , In _{, 1.}
(However, I _{n, 2} , I _{n, 1} is 0 or 1), and the output after the operation is I ′ _{n, 2} , I ′ _{n, 1} (where I ′ _{n, 2} , I ′ _{n, 1} is When 0 or 1) is set, an arithmetic process represented by the following equation 13 is performed, and the differential decoder outputs the output of the selector at time _n to J _{n, 2} and the output of the Viterbi composite to J _{n. , 1} and outputs after the operation are J ′ _{n, 2} , J ′ _{n, 1} (where,
_{J n, 2, J n,} 1, J'n, 2, J'n, 1 is 0 or 1) and the phase ambiguity removing device, characterized in that performing the operation represented by the following Expression 14 formula when the . (Equation 13) [Equation 14]