JP2901475B2 - Field effect transistor and manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having an SOI structure, such as a memory or a logic circuit, which requires a high speed.

[0002]

2. Description of the Related Art Omura has reported that SOIMOSFETs are advantageous in suppressing short channel effects in 1992 IEDM Technical Digest (1992 I.D.
EDMTech. Dig. ), P. 675. However, since the SOIMOSFET has an insulating film below the semiconductor, carriers (holes in the case of an n-channel transistor) generated by impact ionization at the drain end are
It cannot flow into the support substrate, which increases the hole concentration in the SOI substrate and causes an abnormal operation. To solve this problem, it is effective to reduce the electric field strength at the drain end to suppress the generation of holes by using a gate overlap LDD structure. Yamaguchi et al.・ Technical digest (Y
amaguchi 1990 IEDM Tech. D
ig. ) Page 591. The structure is shown in FIG.
Shown in This structure includes the channel region 19 and the source region 46.
Alternatively, an LDD which is an n- region between the drain regions 47
The feature is that there is a region 48. This is because the presence of the LDD 48 region by the n- region on the drain side alleviates the drain electric field, suppresses impact ionization, and suppresses the generation of holes.

[0003]

In the prior art shown in FIG. 9, the structure on the drain side is effective for suppressing the hole concentration, but the structure on the source side does not contribute to the suppression of the hole concentration. The structure on the source side merely serves to function as a drain when the direction of the voltage is reversed, and does not contribute to the suppression of the hole concentration when acting as the source region .

On the other hand, a basic circuit of a logic LSI, a memory LS
In the CMOS configuration used for the peripheral circuit of I, the direction in which the voltage is applied is constant and does not reverse, except for some transmission gates. Therefore, in the transistor used for such an element, the structure of each of the source and the drain can be optimized. Therefore, the source structure can be improved so as to be advantageous in suppressing the hole concentration, and the effect of suppressing the hole concentration can be enhanced.

However, since there is no impact ionization on the source side, the relaxation of the electric field for the purpose of suppressing the impact ionization such as on the drain side is not effective, and a structure based on a different viewpoint is required.

[0006]

According to the present invention, a region adjacent to a source region of an SOI field-effect transistor has a semiconductor or polycrystalline structure containing many defects.

[0007] or SOI field-effect transistor source of
A region adjacent to the source region has a stacked structure of a single crystal and a polycrystalline semiconductor or a single crystal and a semiconductor including many defects.

As a manufacturing method, after forming a source region of an SOI field effect transistor, silicon, oxygen, carbon, and nitrogen atoms are ion-implanted into a region adjacent to the source region to introduce a crystal defect.

[0009]

The operation of the present invention will be described using an n-channel SOI MOSFET as an example. Holes generated at the drain end are lost by diffusing into the source region or recombining with electrons. Recombination rate R is the electron concentration n, hole density p, the carrier concentration n _i intrinsic silicon, are shown as follows using the recombination rate v _r.

R = (np−n _i ² ) / v _r (n + p + 2n _i ) (1) This is maximum when the electron concentration and the hole concentration are equal, as in the chemical reaction formula. In the transistor shown in FIG. 9, in the source region 46, the electron concentration is higher than the hole concentration,
In the channel region 49, the hole concentration is higher than the electron concentration. These concentrations become equal in the vicinity of these boundaries or, if there is an LDD region 48, in the source region 46.
Near the boundary between the side LDD region 48 and the channel region 4, that is, near the source junction. Therefore, when the recombination rate is increased near the source junction, the recombination rate increases remarkably, and holes generated by impact ionization can be lost by recombination with electrons.

FIG. 10 is a band diagram showing such a recombination. When a defect level 53 is formed at the boundary between the source region and the channel region due to a grain boundary, a crystal defect, and an interface defect, the electrons 51 flowing from the source and the holes 52 generated on the drain side become defect levels. Recombines via 53. Therefore, when the density of defect states is increased, recombination can be promoted.

FIG. 11 shows a case where a portion of a channel from a source region and a source region are made of a polycrystalline narrow gap semiconductor 58 typified by polycrystalline germanium. The protrusions in the band diagram indicate local fluctuations in potential formed by the grain boundaries 57. In this structure, holes are lost by recombination via the defect levels 53 present at the grain boundaries, and at the same time, since the source region is a narrow gap semiconductor, a potential barrier when holes are diffused into the source region . Is low and also promotes the diffusion of holes into the source region ,
This is advantageous for removing holes.

In the present invention, the crystal in the vicinity of the source is made of polycrystal, and the density of defect levels serving as recombination centers is increased to increase the recombination rate and promote the disappearance of holes.

In addition, in the vicinity of the drain where a strong electric field is generated, if there is a crystal defect, the leakage current increases due to the effect of the electric field. Therefore, this region has a single crystal structure.

In addition, a monocrystalline and polycrystalline laminated structure near the source is introduced, a polycrystalline region where recombination of holes and electrons occurs is introduced, and a single crystal layer having low resistance is provided. This prevents the increase in resistance caused by the polycrystalline region from affecting the transistor characteristics.

Further, a manufacturing method is provided in which silicon, oxygen, and nitrogen atoms are ion-implanted into a source region of a transistor to break a crystal, thereby polycrystallizing or introducing defects.

The channel region near the source, or both the channel region and the source region , are made of a polycrystalline narrow gap semiconductor such as polycrystalline germanium.

[0018]

1 is a sectional view showing the structure of the first embodiment of the present invention. 3800 angstroms thick on silicon substrate 1
(Hereinafter referred to as A) embedded oxide film 2
An SOI film 3 having a thickness of 500 A is arranged. 0.5 μm length
The p-type gate polysilicon 4 having a high impurity concentration of
It is arranged on the SOI film 3 with the 00A gate oxide film 5 therebetween. A source region 6 and a drain region 7 composed of an n ⁺ region sandwiching a region where the gate polysilicon 4 exists.
Place. The SOI film 3 below the gate electrode is a channel region 9. Further, the channel region 9 and the drain region 7
Has a length of 5 in the SOI film 3 in a region adjacent to the polysilicon 4.
An LDD region 8 consisting of an n ⁻ region of 00A is provided. L
Phosphorus having a concentration of 2 × 10 ¹⁷ cm ⁻³ is introduced into the DD region 8. Boron having a concentration of 1 × 10 ¹⁷ cm ⁻³ is introduced into the channel region 9 located below the gate polysilicon 4. Then, a region having a length of 0.05 μm adjacent to the source region 6 of the channel region 9 is defined as a polycrystalline region 10.

Hereinafter, the manufacturing method will be described.

The surface of an SOI substrate having an SOI film 13 having a thickness of 1000 A is thermally oxidized on a surface of an SOI substrate 13 having a thickness of 1A with a buried oxide film 12 having a thickness of 3800 A on a silicon substrate 11.
A 00A gate oxide film 15 is formed. Followed by boron at ^{30keV 2 × 10 1 2 cm -} 2 ion implantation to 80
A heat treatment at 0 ° C. for 10 minutes is performed in nitrogen. Then, CVD
Is deposited to a thickness of 3000A, and phosphorus is diffused into the polysilicon.
Processing is performed by IE to form a gate polysilicon 14 having a length of 0.5 μm. Gate polysilicon 15 to 3 × 10 ^{1 5} cm arsenic in mask 70 keV ^{- 2} by ion implantation, are activated by a heat treatment of 850 °, the source region 16,
A drain region 17 is formed.

[0021] For this structure, the silicon ions 19 as shown in FIG. 2 5 × 10 ¹³ cm ^- oblique ion implantation at an angle of 45 degrees ² dose, the region 18 containing the defect in the vicinity of the source region formation Then, the shape of FIG. 3 is obtained. For this ion implantation, oxygen, nitrogen, carbon, or the like may be used instead of silicon. The injection amount may be larger or smaller than the above value. Further, the form of the defect may be any of a lattice defect, a defect at an interface, the occurrence of a grain boundary, and the like, depending on the implantation conditions. Further, a heat treatment is performed to the extent that the crystallinity of the crystal damaged by the ion implantation after the ion implantation is not completely recovered (for example, 6
(00 ° C. for 10 minutes).

As a reference example, a polycrystalline semiconductor is a gate electrode.
The structure protruding on the opposite side will be described. A thermal oxide film 22 having a thickness of 2000 A is formed on a silicon substrate 21 and a thickness of 300 A is formed.
After depositing 0A polysilicon and diffusing phosphorus, a gate polysilicon 23 is formed by ordinary photolithography and RIE, and then a 4000 A thick CVD oxide film 24 is deposited and planarized (FIG. 4). ). Next, CVD
A slit 26 having a width of 1 μm is formed in the oxide film 24. Subsequently, 1000 A of amorphous silicon 27 is deposited on the entire surface , and is patterned so that a region having the gate polysilicon 23 and the slit 26 remains continuously (FIG. 5). Subsequently, the whole is covered with a second CVD oxide film 28, and an opening is provided in a region where the amorphous silicon 27 is present, and a second slit 29 is formed (FIG. 6). The amorphous silicon 27 is etched by hydrochloric acid gas through the second slit 29, and the formed cavity is
The single crystal silicon 34 is patterned using a dichlorosilane gas to form an element region. Arsenic 70 is applied so as to sandwich gate polysilicon 23 using photoresist as a mask.
keV at 5 × 10 ^{1 7} cm ^{- 2} implanted, the source region 3
0, a drain region 31 is formed. The photoresist is removed and a heat treatment is performed at 850 ° C. for 15 minutes in nitrogen. Subsequently, 500 A of polycrystalline silicon 33 is deposited on the entire surface, and is removed by RIE leaving a region in contact with the source region 30 and not in contact with the drain region 31. As a result, the shape shown in FIG. 7 is obtained.

Another embodiment according to claim 1 will be described.

In the structure of the first embodiment, the polycrystalline region 10
Is replaced by polycrystalline germanium 70, and the source region 66
Is also made of germanium. Source region 66 may be polycrystalline or single crystal. This is shown in FIG.

The above embodiment is merely an example. For example, the polycrystalline semiconductor is not limited to silicon but may be germanium, gallium arsenide, or the like. In addition, the length of the polycrystalline region or the defect introduction region includes the vicinity of the source and may be longer or shorter than that of the embodiment as long as it does not reach the drain end. Also, SO
The dimensions of the transistor structure such as the I film thickness and the buried oxide film thickness are not limited to the above. In the embodiment, the n-channel F
Although ET has been described, a p-channel FET may be used.

[0026]

The present invention increases the recombination rate by providing a polycrystalline region near the source junction where the recombination of electrons and holes occurs, thereby reducing the minority carriers in the channel region and reducing the minority carriers. Can be reduced more than the operation of the transistor due to the accumulation of the charge.

In addition, silicon atoms, oxygen atoms, and nitrogen atoms are ion-implanted near the source junction to destroy the crystal structure,
It can be polycrystallized.

By implanting these atoms with ions, even if the crystal is not destroyed, defects generated in the crystal or on the crystal surface promote carrier recombination similarly to the grain boundary of the polycrystalline semiconductor. This has the effect of reducing minority carriers.

Further, by making the source region and the vicinity of the source a polycrystalline flow gap semiconductor, diffusion of minority carriers to the source can be promoted and minority carriers can be reduced. In the recombination of electrons and holes, recombination at the interface between a semiconductor and an oxide film, called surface recombination, is known. However, by providing a defect region to reach both interfaces of the SOI layer , Surface recombination can be increased not only at the lower interface but also at the upper interface. Further, in the present invention, since a large number of crystal defects are introduced into a limited region having a width close to the source region in the channel region, there is an advantage that the crystal defects do not lower the channel current in the channel region. is there. In the present invention,
In the case where a polycrystalline semiconductor or a semiconductor containing a large number of defects is configured to protrude into an insulator below a center portion of a channel region on a side opposite to a gate electrode side, the manufacturing thereof is reduced as the SOI becomes thinner. No more difficult things. Further, after the heat treatment following the ion implantation for forming the source region and the drain region, ion implantation for introducing a crystal defect is performed, so that compared with the case where ion implantation for defect introduction is performed before the heat treatment. There is an advantage that the implantation amount can be reduced because it is not necessary to expect a decrease in defects due to crystal recovery by heat treatment. Also, the controllability of the introduction of the defect is increased. Further, there is an effect that abnormalities relating to the distribution and activation of impurities for forming the source and drain regions, which are caused by the introduction of defects before the heat treatment, can be prevented. In a semiconductor having a narrow band gap, the hole electron concentration product increases. Therefore, if a defect is introduced into the semiconductor, a synergistic effect that recombination increases from the above equation (1) is brought about. In addition, a heterojunction (heterojunction) is formed by a semiconductor having a narrow band gap. In two semiconductors forming the heterojunction, crystal defects are likely to occur because the crystal lattice spacing is different. In the process of forming a semiconductor having a narrow band gap , crystal defects are naturally induced at the junction or inside the semiconductor, and have the effect of generating crystal defects in a necessary region without ion implantation. Will be. Further, by introducing nitrogen or carbon, an element different from oxygen and silicon constituting the upper and lower interfaces of the SOI layer is introduced, and an electronic state which does not originally exist, that is, a recombination level is formed in a region in contact with the interface. And the surface recombination is increased, and holes can be effectively removed. Regarding these elements, nitrogen forms a stable bond with silicon or an oxide film, and carbon, which is the same group IV element as silicon, can form a stable bond with silicon. This has the effect of making it easier to fix in position.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing method of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing method of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing method of a reference example .

FIG. 5 is a cross-sectional view illustrating a manufacturing method of a reference example .

FIG. 6 is a cross-sectional view illustrating a manufacturing method of a reference example .

FIG. 7 is a cross-sectional view illustrating the manufacturing method of the reference example .

FIG. 8 is a sectional view showing another embodiment of the present invention.

FIG. 9 is a sectional view showing a conventional example.

FIG. 10 is a band diagram illustrating the principle of the present invention.

FIG. 11 is a band diagram illustrating the principle of the present invention.

[Explanation of symbols]

 1, 11, 21, 41, 61 silicon substrate 2, 12, 42, 62 buried oxide film 3, 13, 43, 63 SOI film 4, 14, 23, 44, 64 gate polysilicon 5, 15, 25, 45, 65 Gate oxide film 6, 16, 30, 46, 54 Source region 7, 17, 31, 47, 56, 67 Drain region 8, 48, 68 LDD region 9, 32, 49, 55, 69 Channel region 10 Polycrystalline region Reference Signs List 18 Defect-containing region 22 Thermal oxide film 24 CVD oxide film 26 Slit 27 Amorphous silicon 28 Second CVD oxide film 29 Second slit 33 Polycrystalline silicon 51 Electron 52 Hole 53 Defect level 57 Grain boundary 58 Polycrystalline narrow Gap semiconductor 66 Germanium source region 70 Polycrystalline germanium

Claims (8)

(57) [Claims] An SO is used to form an element in a semiconductor layer on an insulator.
A channel region having a width of 1 in contact with the source region in the channel region is formed of a polycrystalline semiconductor or a semiconductor containing a large number of defects caused by the destruction of the crystal lattice so as to reach both upper and lower surfaces of the silicon layer. A field effect transistor comprising: a channel region other than the region; and a single crystal semiconductor having a lower defect density than the region having a certain width . 2. A method for manufacturing a field-effect transistor having an SOI structure in which an element is formed in a single crystal semiconductor on an insulator, wherein a source region and a drain region are formed by ion implantation and heat treatment, and then are adjacent to the source region. Ion implantation of silicon, oxygen, carbon, or nitrogen into the channel region, and then do not perform heat treatment for crystal recovery , or perform crystal implantation recovery after the silicon, oxygen, carbon, or nitrogen ion implantation. Forming a region including a large number of defects caused by the destruction of a crystal lattice in the channel region by performing a heat treatment at a temperature lower than the temperature of the heat treatment. 3. An SO for forming an element in a semiconductor layer on an insulator.
A region having an I structure, which is in contact with the source region in the channel region and has a certain width within a range in which the potential decreases or increases in the direction from the source to the drain of the n- or p-channel transistor, is a destruction of the polycrystalline semiconductor or the crystal lattice. And a channel region excluding that region is formed of a single crystal semiconductor having a lower defect density than the region having a certain width. 4. The method according to claim 1, wherein the polycrystalline semiconductor or the semiconductor containing a large number of defects caused by the destruction of the crystal lattice is a silicon layer.
4. The field effect transistor according to claim 3 , wherein the field effect transistor is formed so as to reach both upper and lower surfaces . 5. An SO for forming an element in a semiconductor layer on an insulator.
A semiconductor which has an I structure and has a region in contact with a source region in a channel region or both of the region and the source region, the band gap of which is smaller than a region other than the region in contact with the source region in the channel region. A field-effect transistor, comprising: 6. A part or all of the semiconductor rich the crystal defects, the claim bandgap than the area excluding the area in contact <br/> to the source region of the channel region is narrow polycrystalline semiconductor 5 The field-effect transistor according to any one of the preceding claims. 7. An SO for forming an element in a semiconductor layer on an insulator.
A semiconductor region having an I structure, in which a region in contact with a source region in a channel region has crystal defects caused by introduction of nitrogen or carbon, and the crystal defects are higher in density than crystal defects in a channel region excluding the region; A field-effect transistor, comprising: 8. An SO which forms an element in a semiconductor layer on an insulator.
In a method of manufacturing a field effect transistor having an I structure, a channel is formed after forming a source region and a drain region.
A method for manufacturing a field-effect transistor, comprising: ion-implanting carbon or nitrogen into a region of a flannel region that is in contact with a source region to form a large number of defects caused by destruction of a crystal lattice.