JP2901541B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus connected to a network (LAN, VAN, WAN) and capable of exchanging data and programs with other terminals.

[0002]

2. Description of the Related Art Conventional information processing apparatuses which can be connected to a network are compatible with network environments such as LAN, VAN, WAN, etc., and share information such as hardware and software, e-mail and electronic conference systems. , And data transfer or processing at another terminal using network application software (FTP, TELNET, etc.).

A conventional information processing apparatus will be described with reference to the drawings. Referring to FIG. 5, a conventional information processing apparatus includes:
CPU for managing and controlling the entire operation of the information processing device
(Central processing unit) 1, a network interface unit 18 for network connection, a main memory 2 for temporarily storing data and programs required for processing, and a main memory control unit for controlling data input / output to / from the main memory 2. 3, a hard disk unit 5 for storing data and programs as magnetic media, and a disk control unit 19 for controlling data input / output to / from the hard disk unit 5.
A DMAC (Direct Memory Access Controller) 7 for processing data transfer between the main memory 2 and the disk control unit 19 without passing through the CPU 1;
And a decoding circuit 4 for generating a select signal for the network interface unit 18 and the disk control unit 19.

A signal line connecting these blocks includes a command bus 8 for transmitting a command from the CPU 1 to the network interface unit 18, the DMAC 7, the disk control unit 19 and the main memory control unit 3, and an address information output from the CPU 1. To the network interface unit 18, the DMAC 7, the main memory control unit 3, and the decoding circuit 4, and the data between each block of the CPU 1, the network interface unit 18, the DMAC 7, the disk control unit 19, and the main memory 2. The data bus 10 and the DMAC
DMA request signal 11 which is a data transfer request to
A hold request 12 which is a bus use permission request from the DMAC 7 to the CPU 1;
Acknowledgment signal 13 which is a bus use permission signal to DMA controller 7, DMA acknowledge signal 14 which is a data transfer permission signal from DMAC 7 to disk control unit 19, and network control unit select signal 20 which is a select signal to network interface unit 18. And a disk control unit select signal 21 which is a select signal of the disk control unit 19 and a DMAC which is a select signal of the DMAC 7.
There are a select signal 22 and a memory access signal 23 which is a memory control signal from the main memory control unit 3 to the main memory 2.

Next, the operation of the above-mentioned prior art will be described with reference to FIGS. 6, 7 and 8. FIG. FIG. 6 is a flowchart showing the operation of the information processing apparatus of FIG. this is,
The outline until data that has entered the information processing apparatus from the external network to the hard disk unit 5 is shown. FIG. 7 is a timing chart showing an operation (data transfer from a memory to an I / O) according to the related art. FIG.
5 is a timing chart showing an operation (data transfer from an I / O to a memory) according to the related art.

In step 601, data from the external network is taken into the network interface unit, and temporarily stored in the main memory 2 via the data bus 10 in accordance with a data transfer instruction from the CPU 1. In step 602, the CPU 1 transfers the address and data length of the data stored in the main memory 2 to the DMAC 7. In step 603, the CPU 1 instructs the disk control unit 19 to write to the disk (DMA transfer). In step 604, the disk controller 19 issues a DMA request signal 11 to the DMAC 7, and the DMAC 7 issues a hold request signal 12 to the CPU 1. The CPU 1 sets the data bus 10 to DMA.
When it is ready to surrender to C7, the DMAC 7 returns a hold acknowledge signal 13 to the DMAC 7, and the DMAC 7 returns a DMA acknowledge signal 14 to the disk controller 19. As a result, data transfer becomes possible, and the DMAC 7 sends the address of the transfer source main memory 2 to the address bus 9, and also outputs a memory read signal as a read request to the main memory 2 and a write request to the disk control unit 19. /
An O-write signal is sent to the command bus 8. This DM
The operation of the AC 7 causes the main memory control unit 3 to instruct the main memory 2 to send data to the main memory 2.
Is transmitted to the data bus 10 and the disk control unit 19 receives the data. The disk control unit 19 transfers the received data to the hard disk unit 5 and instructs the writing, and the data writing to the hard disk unit 5 is completed. This operation is repeated until all data indicated by the data length is transferred.

In this embodiment, the data transfer by the DMAC 7 has been described. However, other devices replacing the DMAC 7, for example, when a logic circuit is dedicated to the device,
The same operation can be performed when data is transferred using G / A or the like newly developed for data transfer. Further, the unit used as the storage medium is not limited to the hard disk unit, and the same operation can be performed using an optical disk, tape, floppy disk, or the like.

In this conventional information processing apparatus, when a virus enters from the network, the virus itself directly operates the disk control unit 19 and the DMAC 7 to destroy data stored in the hard disk unit 5 and to execute the program. The problem of easy infection is addressed by checking and removing the virus using software called a vaccine program. However, this method cannot cope with a new kind of virus, and there is no way to cope with it until a new vaccine program is created.

[0009] Japanese Patent Application Laid-Open No. 5-143611 discloses
There is also an information processing apparatus that employs a method of detecting a virus contaminated via a network by using cryptographic decryption, as in the technique described in the above.

[0010]

According to the above-mentioned prior art, this is dealt with by setting access rights to vaccine programs and files. However, some viruses are not effective. Is in a difficult situation. Further, when writing is prohibited by setting the access right, overwriting or erasing cannot be performed in a normal program, so that there is a problem that the access right must be set each time.

Also, the technique disclosed in Japanese Patent Application Laid-Open No. 05-143611 has a problem that it cannot cope with a new kind of virus.

An object of the present invention is to solve the above problems,
An object of the present invention is to provide an information processing apparatus capable of preventing a virus from being mixed by enabling file management and write protection setting in hardware (including firmware).

[0013]

A first information processing apparatus according to the present invention comprises a CP for managing and controlling the entire information processing apparatus.
U, a main memory for storing various data, a main memory control unit for controlling access to the main memory,
A decoding circuit for decoding addresses to generate select signals for various I / O devices; a storage unit for storing and storing programs and data; a disk control unit for controlling read / write of the storage unit; A command bus for transmitting instructions from the CPU, and the CPU
An address bus for transmitting address information of the I / O device, the storage unit, and the main memory from the CPU, and exchange of data between the CPU and the I / O device, the storage unit, and the main memory in the information processing apparatus and a data bus for
There, etc. should be allowed to write to the storage unit
A hardware switch that Specifies if a nonvolatile memory for storing a file name registered in the storage unit, a nonvolatile memory controller for controlling access of the non-volatile memory, file in the storage unit
When writing a file, the file is
If registered in volatile memory, the hardware
Check the contents of the switch.
Write to the storage unit,
If present, write the file to the storage unit
The file is registered in the nonvolatile memory.
If not, check the contents of the hardware switch and write
If writing is permitted, the file is stored in the nonvolatile memory.
Register the file name and enter the file
Write to the storage unit, if writing is not allowed,
Writing to the storage unit according to the judgment of the CPU
Control to implement only

According to a second information processing apparatus of the present invention,
And a hard disk unit is provided as the storage unit.

[0015] The third information processing apparatus of the present invention comprises the first information processing apparatus.
The information processing apparatus according to the above, further comprising a magneto-optical disk unit as the storage unit.

[0016]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. Referring to FIG. 1, an information processing apparatus according to the present invention includes a CPU 1 for managing and controlling the entire information processing apparatus, a main memory 2 for storing various data, and a main memory control unit 3 for controlling data read / write. A decoder circuit 4 for generating a select signal for each I / O, a hard disk unit 5 for storing and storing programs and data, a disk control unit 6 with a write restriction function for controlling the operation of the hard disk unit 5, A DMAC 7 for transferring data between the O and the memory;
Command bus 8 for transmitting an access control signal from C7
An address bus 9 for transmitting address information from the CPU 1 and the DMAC 7, a data bus 10 used for data exchange between the CPU 1 and each I / O or memory, and a DMA transfer request from the disk control unit 6 to the DMAC 7. A certain DMA request signal 11, a hold request signal 12 which is a use permission request signal for the data bus 10,
A hold acknowledge signal 13 indicating that the data bus 10 has become usable, and a DMA indicating DMA transfer permission.
The acknowledgment signal 14, the non-volatile memory 16 for registering the file name of the file for which writing to the hard disk unit 5 is not specified, the non-volatile memory control unit 17 for controlling access to the non-volatile memory 16, and the non-volatile memory 16 A switch 15 that is turned on when registering a file name in the non-volatile memory 16 and turned off when prohibiting writing of the file registered in the nonvolatile memory 16 to the hard disk unit 5, and a network interface unit 18 for connecting to an external network A network control unit select signal 20 as a select signal to the network interface unit 18; a disk control unit select signal 21 as a select signal of the disk control unit 6 with write restriction function; and a DMAC cell as a select signal of the DMAC 7. A control signal bus 23 for controlling read / write to / from the main memory 2; a nonvolatile memory / control signal bus 24 for controlling read / write to / from the nonvolatile memory 16; A non-volatile memory address bus 25 for supplying an address to the memory, a non-volatile memory data bus 26 for flowing read / write data of the non-volatile memory 16,
A disk write enable signal 27 is output from the non-volatile memory controller 17 and indicates whether writing to the disk is possible.

Referring to FIG. 4, the disk control unit 6 with a write restriction function includes a disk control unit 19, a disk write enable signal 27 indicating whether or not writing to the hard disk unit 5 is possible, and a control from the disk control unit 19. The nonvolatile memory control unit 17 controls the writing to the hard disk unit 5 by the signal of the switch 15 and the data of the nonvolatile memory 16 based on an AND logic having a signal and a disk write enable signal 27 as inputs. A write determination unit 28 and a disk write enable signal 27 that is turned off when the switch 15 is turned off
An address decoder 33 for controlling access to the nonvolatile memory 16; a nonvolatile memory address bus 25 for supplying an address to the nonvolatile memory 16; and a data nonvolatile memory for passing read / write data of the nonvolatile memory 16. A data bus 26, a nonvolatile memory select signal 32 which is a select signal of the nonvolatile memory 16,
A non-volatile memory read signal 31 which is a control signal for reading data from the non-volatile memory 16; a non-volatile memory write determining unit 29 for determining whether data can be written to the non-volatile memory 16; Non-volatile memory write signal 30 which is a control signal for writing
It is composed of

Next, the operation of the present invention will be described with reference to FIG. FIG. 2 is a flowchart showing the operation of the information processing apparatus of FIG.

File data to be written to the hard disk unit 5 is temporarily taken into the network interface unit 18 from an external network. This data is C
The network controller select signal 20 is output from the decode circuit 4 that controls access to various I / Os under the control of the PU 1 to the network interface 18 and transmitted to the main memory 2 via the data bus 10. At this time, since the main memory control signal bus 23 is output to the main memory 2 by the main memory control unit 3, data is recorded in the main memory 2. When data transfer to the hard disk unit 5 is to be started in this state, first, the CPU 1 outputs address information indicating the position of the nonvolatile memory 16 to be confirmed to the address bus 9 and simultaneously issues a read instruction to the command bus 8. Output to The address information is transmitted to an address decoder 33 in the nonvolatile memory control unit 17, and the nonvolatile memory select signal 32 and the nonvolatile memory
The command information is transmitted to the nonvolatile memory 16 via the address bus 25, and the command information is stored in the nonvolatile memory / control signal bus 1.
It is transmitted to the nonvolatile memory 16 via the nonvolatile memory read signal 31 which is a book. As a result, the nonvolatile memory 16 returns data to the CPU 1 via the nonvolatile memory / data bus 26, the write determination unit 28, and the data bus 10. By repeating this operation, the nonvolatile memory 16
Is confirmed (step 201).

If the same file name is registered, the write judging unit checks the setting of the switch 15 (step 202). If the write is not permitted, the CPU 1 informs the CPU 1 via the data bus 10 that the write is not possible. The notification is made and the process ends (step 203).

If the writing is permitted, the write judging section 28
Turns on the disk write enable signal 27 (step 204) to transfer data. The CPU 1 controls the decoding circuit 4 to output a DMAC select signal 22 to the DMAC 7, and sets the address and data length of data stored in the main memory 2 for the DMAC 7.
Next, under the control of the CPU 1, a disk control unit select signal 21 is output from the decoding circuit 4 to the disk control unit 6 with the write restriction function, and the disk control unit 6 with the write restriction function is written to the hard disk unit 5 (DMA transfer). To instruct.

Disk control unit 6 with write restriction function
Issues a DMA request signal 11 to the DMAC 7,
The DMAC 7 issues a hold request signal 12 to the CPU 1. When the CPU 1 is ready to hand over the data bus 10 to the DMAC 7, the CPU 1 returns a hold acknowledge signal 13 to the DMAC 7, and the DMAC 7 returns a DMA acknowledge signal 14 to the disk control unit 6 with a write restriction function. As a result, the data transfer becomes possible, and the DMAC 7 sends the address of the transfer source main memory 2 to the address bus 9 and also writes the memory read signal, which is a read request to the main memory 2, and the write to the disk control unit 6 with write restriction function. The request I / O write signal is sent to the command bus 8. By the operation of the DMAC 7, the main memory control unit 3 instructs to send data to the main memory 2, the transfer data is sent from the main memory 2 to the data bus 10, and the disk control unit 6 with write restriction function receives the data. . The disk control unit 6 with the write restriction function transfers the received data to the hard disk unit 5 and instructs the writing, and the data writing to the hard disk unit 5 is completed. This operation is repeated until all data indicated by the data length has been transferred (step 205).

When the transfer is completed, the disk write enable signal 27 is turned off by the write judging section 28, and the process is terminated (step 206).

If the same file name is not registered in the contents of the non-volatile memory 16, the write decision unit 28 turns on the disk write enable signal 27 (step 2).
07), the writing judgment unit checks the setting of the switch 15 (step 208).

If the setting of the switch 15 is write permission, the CPU 1 executes the non-volatile memory 1
At the same time as outputting address information indicating the position of No. 6 to the address bus 9, a write instruction is output to the command bus 8.
The address information is transmitted to the address decoder 33 in the non-volatile memory control unit 17, is transmitted to the non-volatile memory 16 by the non-volatile memory select signal 32 and the non-volatile memory address bus 25, and the command information is transmitted to the non-volatile memory write determination unit. 29 and a non-volatile memory write signal 30 which is one of the non-volatile memory / control signal buses. By repeating this operation, the file name is registered in the non-volatile memory 16 (step 209), the data is transferred (step 205), and when the transfer is completed, the write determination unit 28 turns off the disk write enable signal 27 and terminates. (Step 206).

If writing is not permitted, the CPU 1 is notified of confirmation of writing to the hard disk unit 5 (step 210). If writing is permitted, data is transferred (step 205). Turn off 27 and finish (step 20)
6).

Next, a method of registering a file name will be described with reference to FIG.
This will be described with reference to FIG. FIG. 3 is an explanatory diagram showing a file name registration method.

As an example of a method of registering a file name in the nonvolatile memory 16, as shown in FIG. 3, file information is recorded in units of 16 bytes from the head address of the nonvolatile memory 16 as shown in the memory map. The contents can be easily managed by using information such as a file name and a registered date.

The setting of the memory map is not specified in this method. For example, if one file information is set as a larger area, more detailed information, a registrant name, a file size, a version number, etc. are also managed. It becomes possible.

As described above, the management based on the presence or absence of the file name is determined to be written in the hard disk unit. However, the unit is not limited to the hard disk, and the same processing is performed on a recording medium such as an optical disk or a floppy disk. It is possible.

Also, if the nonvolatile memory is a device which does not disappear when the power is turned off, the EEPROM, SRAM, RA
Other than the M file is also possible. In this case, access from outside and access by a program loaded from outside must be disabled.

When a plurality of units are connected, the information can be individually controlled by writing the write enable / disable information for each unit in the information in the nonvolatile memory.

[0034]

As described above, according to the present invention, the hardware switch for selecting whether or not to add a new file to a data storage unit such as a hard disk unit is turned off, and the same file is registered in the nonvolatile memory. If the hardware switch is on, write data to both the nonvolatile memory and the data storage unit.If the hardware switch is on, write the data to both the nonvolatile memory and the data storage unit. If the file name is not registered in the non-volatile memory when it is turned off, it is checked whether or not to write to the CPU, and if permission is given, it is possible to write, so that it is stored in the hard disk unit by a virus entered from a network etc. Data corruption or program damage There is an effect that it is possible to prevent the pulse infection. Also, since the registered file cannot be overwritten or deleted, there is also an effect that the contents of important files are not destroyed or deleted due to erroneous operation.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing apparatus according to the present invention.

FIG. 2 is a flowchart illustrating an operation of the information processing apparatus of FIG. 1;

FIG. 3 is a memory map of the nonvolatile memory of FIG. 1;

FIG. 4 is a detailed block diagram illustrating disk write control according to the present invention.

FIG. 5 is a block diagram of the prior art.

FIG. 6 is a flowchart showing the operation of the conventional technique of FIG. 5;

FIG. 7 is a timing chart illustrating the operation of the conventional technique.

FIG. 8 is a timing chart for explaining the operation of the related art.

[Explanation of symbols]

Reference Signs List 1 CPU (central processing unit) 2 main memory 3 main memory control unit 4 decoding circuit 5 hard disk unit 6 disk control unit with write restriction function 7 DMAC (direct memory access controller) 8 command bus 9 address bus 10 data bus 11 DMA request signal 12 Hold request signal 13 Hold acknowledge signal 14 DMA acknowledge signal 15 Switch 16 Nonvolatile memory 17 Nonvolatile memory control unit 18 Network interface unit 19 Disk control unit 20 Network control unit select signal 21 Disk control unit select signal 22 DMAC select Signal 23 Main memory control signal bus 24 Non-volatile memory / control signal bus 25 Non-volatile memory / address bus 26 Non-volatile memo Data bus 27 disk write permission signal 28 write detector 29 nonvolatile memory write detector 30 nonvolatile memory write signal 31 nonvolatile memory read signal 32 nonvolatile memory select signal 33 address decoder

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 12/00 G06F 9/06 G06F 3/06 G06F 12/14

Claims (3)

(57) [Claims] 1. A CPU for managing and controlling the entire information processing apparatus, a main memory for storing various data, a main memory control unit for controlling access to the main memory, and various I / O by decoding addresses. A decoding circuit for generating a select signal of the device; a storage unit for storing and storing programs and data; a disk control unit for controlling read / write of the storage unit;
A command bus for transmitting an instruction from a PU, an address bus for transmitting address information of the I / O device and the storage unit and the main memory from the CPU, the CPU and the I / O device And an information processing device having a data bus for exchanging data with the storage unit and the main memory, wherein writing to the storage unit is permitted.
A hardware switch that specifies whether the non-volatile memory for storing a file name registered in the storage unit, a nonvolatile memory controller for controlling access of the non-volatile memory, said storage unit To
When writing a file, the file
If registered in the nonvolatile memory, the hardware
Check the contents of the hardware switch.
Write to the storage unit and write
If permitted, write the file to the storage unit.
The file is registered in the nonvolatile memory.
If not, adjust the contents of the hardware switch.
In addition, if writing is permitted, the nonvolatile memory
Register the file name and copy the file to the file
Write to the storage unit, if writing is not allowed
If the CPU determines, the storage unit
An information processing apparatus, comprising: performing control to execute writing of data. 2. The information processing apparatus according to claim 1, wherein a hard disk unit is applied as said storage unit. 3. The information processing apparatus according to claim 1, wherein a magneto-optical disk unit is applied as said storage unit.