JP2901713B2 - Input circuit of programmable controller - Google Patents

Description

The present invention relates to an input circuit of a programmable controller (hereinafter, referred to as a PCS), and more particularly to an input of a PCS suitable for reducing a load on an arithmetic processing unit of the PCS. Circuit.

[Prior Art] When a PCS takes in a signal from, for example, a large relay or a limit switch, the input signal has a long chattering when the signal is turned on or off as shown in FIG. Often occurs. When a signal having such chattering is input to the PCS, the control content becomes unstable. Therefore, the input signal is delayed. In the prior art described in Japanese Patent Application Laid-Open No. 61-86807, a resistor and a capacitor provided on the secondary side of an element that electrically insulates an input signal delay a time determined by the time constant. Is a fixed value determined by the time constant (for example, the half-wave and full-wave time of the commercial AC power supply, 10 milliseconds and 20 milliseconds in 50 cycles), and is not so effective. Therefore, usually, as shown in FIG. 6, an on-delay timer is incorporated in a program executed by the PCS to prevent adverse effects due to chattering.

[Problem to be Solved by the Invention] Eliminate the adverse effects of chattering described above,
PCS for the purpose of adjusting the operation timing of the controlled object
Defines how many timer control instructions can be programmed according to the control scale (the number of input / output points to be controlled). If the number of timer control instructions is large, the load on the central processing unit of the PCS that executes the timer control instructions increases. For this reason, usually, a timer control instruction of about 1/10 of the number of input / output points to be controlled can be used. However, the number of input / output points to be controlled by the recent PCS is increasing, and the number of relays and the like that generate chatter is also increasing. There is a problem that a heavy burden is imposed.

An object of the present invention is to provide an input circuit of a PCS that reduces the number of timer control instructions executed by a central processing unit and reduces the load.

[Means for Solving the Problems] The object of the present invention is to provide a programmable controller that converts the level of an output signal to be controlled, converts the signal into an electrically insulated signal, passes through a filter, and inputs the signal to the programmable controller via a bus interface. In the input circuit, an input signal delay circuit having a signal delay unit and a delay amount setting unit is provided between the filter and the bus interface, and the delay amount setting unit divides the original clock signal to generate a clock signal. And a switching means for switching the frequency division number. The signal delay unit includes a flip-flop cascade-connected in four stages and a NA of the Q output of each of the four stages of flip-flops.
An NAND gate that takes ND, an OR gate that takes the OR of the Q outputs of each of the four-stage flip-flops, and outputs a high-level signal at the output of the NAND gate and outputs a low-level signal at the output of the OR gate An output flip-flop is provided, the signal delay unit is provided to be interposed between the filter and the bus interface, and the output of the frequency divider circuit is connected to each of the cascade-connected flip-flops so as to supply the flip-flop as a clock signal. This is achieved by controlling the time until the Q output of the last flip-flop of the cascade-connected flip-flop changes to a high level in accordance with the output clock of the frequency dividing circuit.

[Operation] Before the input signal enters the PCS from the input circuit, the input signal is delayed by the input circuit, and the amount of delay can be controlled to an optimal value for the chattering time by the switching means for switching the frequency division number of the frequency divider circuit. Even if a chattering signal passes through this input circuit, no erroneous input is made to the PCS. In other words, in the present invention, the delay is dealt with by hardware, so that the load on the central processing unit of the PCS is reduced accordingly.

Embodiment A preferred embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 is a configuration diagram of an input circuit according to a first embodiment of the present invention. The input circuit 12 includes an input terminal 21 for receiving an output signal from a control target as an external signal, a level conversion circuit 16, a photocoupler 17 as an electrically insulating element, a filter 18 including a resistor and a capacitor, Delay circuit
13 is provided. After the signal input from the input terminal 21 to the input circuit 12 is level-converted by the level conversion circuit 16, then once converted into an optical signal by the photocoupler 17, converted again into an electric signal, and filtered by the filter 18, After being input to the input signal delay circuit 13 and delayed by a set delay amount, the signal is sent out to the bus 20 via the bus interface circuit 19 and is taken into the PCS (not shown).

The input signal delay circuit 13 according to the present embodiment includes a signal delay unit 14
And a delay amount setting unit 15. The detailed circuit is shown in FIG. The delay amount setting unit 15 includes a frequency dividing circuit 5 for dividing the frequency of the original clock signal, and a switch 6 for switching the frequency dividing number. The signal delay unit 14 includes a four-stage cascade-connected signal delay flip-flop 1 (Q output is connected to the data input), a NAND gate 2 that takes a NAND of the Q output of each flip-flop 1, and an OR of each Q output. , And an output flip-flop 4 operated by the output signals of the gates 2 and 3. Then, the clock signal 11 output from the frequency dividing circuit 5 becomes a clock signal for each flip-flop 1.

Now, it is assumed that the input data (signal) is at a low level. It is also assumed that each flip-flop 1 has been reset in advance by a reset signal. Then, since the Q output of each flip-flop 1 is at a low level, the output of the OR gate 3 causes the output flip-flop 4 to output a low-level signal.

Next, it is assumed that the input data becomes high level. The change to the high level sequentially appears as the Q output of each flip-flop 1. When the Q outputs of all the flip-flops 1 become the high level, the output flip-flop 4 becomes the high level by the output signal of the NAND gate 2. Become. That is, the time is controlled until the Q output of the last-stage flip-flop 1 changes to a high level in accordance with the output clock of the frequency dividing circuit 5.

It is assumed that chattering shown in FIG. 5 has occurred in the input data. That is, it is assumed that the input data is at a high level, at a low level, or in an unstable state. In the present embodiment, the delay time is set by the delay amount setting unit 15 (that is, the last flip-flop 1
Is set to be longer than the chattering period, so that the influence of chattering does not appear on the output of the output flip-flop 4. That is, in the chattering state, the Q output of one of the flip-flops 1 has turned to low level, and the output of the NAND gate 2 is kept at high level.

FIG. 3 is a configuration diagram of the input circuit according to the second embodiment of the present invention, and FIG. 4 is a detailed configuration diagram of the input signal delay circuit 13. In the first embodiment described above, the delay amount of the input signal is controlled by controlling the switch 6, but in the present embodiment,
A register 22 is provided instead of this switch.
The frequency division number is controlled by the set value of 22, and the input signal delay amount is made variable. The set value of the register 22 is set by a command from a central processing unit (not shown) of the PCS through a data setting bus 23. In the first embodiment, the delay amount is controlled by the user operating the switch 6, whereas in the present embodiment, the central processing unit automatically sets the delay amount according to the control content.

[Effects of the Invention] According to the present invention, an input signal delay amount can be set so as not to be adversely affected by chattering in accordance with an input device in which chattering occurs, and the input signal is delayed in a hardware manner. In addition, the central processing unit of the PCS does not need to manage the delay amount of each input signal by software, so that overhead can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an input circuit according to a first embodiment of the present invention,
FIG. 2 is a detailed configuration diagram of the input signal delay circuit shown in FIG. 1,
3 is a detailed configuration diagram of an input signal delay circuit according to a second embodiment of the present invention, FIG. 4 is a detailed configuration diagram of the input signal delay circuit shown in FIG. 3, FIG. 5 is a signal waveform diagram of chattering, Sixth
The figure is a ladder circuit diagram for realizing a delay of an input signal by a program. 12 ... input circuit, 13 ... input signal delay circuit, 14 ... input signal delay unit, 15 ... delay amount setting unit, 16 ... level conversion circuit, 17 ... photocoupler, 18 ... filter, 19 ... ... Bus interface.

────────────────────────────────────────────────── (7) Continuation of the front page (72) Inventor Shingo Furusawa 7-1-1, Higashi Narashino, Narashino City, Chiba Prefecture Inside the Narashino Plant of Hitachi, Ltd. JP-A-60-168211 (JP, A) JP-A-59-68007 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G05B 19/05

Claims (1)

(57) [Claims] An input circuit of a programmable controller for converting the level of an output signal of a control target, converting the output signal into an electrically insulated signal, passing through a filter, and inputting the signal to the programmable controller via a bus interface.
An input signal delay circuit having a signal delay unit and a delay amount setting unit is provided between the filter and the bus interface, and the delay amount setting unit divides an original clock signal to generate a clock signal. Switching means for switching the number of divisions, wherein the signal delay unit includes a cascade-connected four-stage flip-flop, a NAND gate for taking a NAND of a Q output of each of the four-stage flip-flops, An OR gate for ORing the Q outputs of the four flip-flops; and an output flip-flop for outputting a high-level signal at the output of the NAND gate and outputting a low-level signal at the output of the OR gate. Wherein the signal delay section is provided so as to be interposed between the filter and the bus interface, and an output of the frequency dividing circuit is provided for each of the cascade-connected flip-flops. Is connected so as to be supplied as a clock signal, and is configured to control the time until the Q output of the last flip-flop of the cascade-connected flip-flop changes to a high level in accordance with the output clock of the frequency dividing circuit. An input circuit of a programmable controller.