JP2902945B2 - Spread spectrum code synchronization acquisition and holding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a spread spectrum code synchronization acquisition and holding device used for, for example, power line communication.

[0002]

2. Description of the Related Art In a spread spectrum communication system, an information signal to be transmitted is multiplied by a pseudo-noise code (hereinafter referred to as a PN code) used as a spreading code to spread the information signal in a band wider than the bandwidth of the information signal. This is a communication method for transmitting data by being transmitted, and has excellent confidentiality and noise resistance, and thus is often used for communication on a poor transmission path.

In order to receive a signal transmitted by the spread spectrum communication, a PN included in the received signal is required.
It is necessary to generate the same PN code as the code on the receiving device side so that the phases match, and multiply them. As a matter of course, the receiving apparatus cannot know in advance the phase of the PN code included in the received signal, and therefore, as shown in FIG.
The phase of the PN code is detected by utilizing the characteristic that almost no correlation is obtained if there is a phase difference of one chip (the minimum unit of the PN code) or more in the autocorrelation function of the N code. In order to establish the phase synchronization of the PN code on the receiving device side, a function of capturing the phase error of the PN code within one chip and a function of holding the phase error of the PN code at 0 are required.

FIG. 7 shows an example of a conventional spread spectrum code synchronization acquisition and holding device. 7, reference numeral 21 denotes an input terminal; 22, 23, and 24 multipliers; 25, 26, and 27 band-pass filters; 28, 29, and 30 envelope detectors;
Is a comparator, 32 is a differential amplifier, 33 is a loop filter,
34 is a voltage controlled oscillator, 35 is an AND gate, 36 is P
An N code generator, 37 is a sweep controller, and 38 is a delay lock loop.

[0005] The spread spectrum signal input to the input terminal 21 is divided into three, and the PN codes (0, + Δ,-) of which the phases are shifted by one chip from the PN code generator 36 respectively.
Is multiplied by the multipliers 22 to 24 and, after being despread, passes through band-pass filters 25 to 27, which pass only the band of information modulation, and envelope detectors 28 to 3
Detected by 0. Each output is shown in FIG.
As shown in FIG.

[0006] The synchronization acquisition here is performed in a sliding correlation loop. The output of the envelope detector 28, which has been envelope-detected over one cycle of the PN code, is compared with a preset threshold level 39 by the comparator 31, and no correlation exceeding the threshold level 39 is obtained. At the time, the sweep controller 37 is activated and the PN code generator 36
One pulse of the input clock to the PN code is extracted, and the phase of the PN code is shifted by one chip. Since a PN code can normally obtain a correlation only within the range of a phase difference of ± 1 chip, if a correlation exceeding the threshold level 39 is obtained at the output of the envelope detector 28, synchronization can be acquired. And the sweep is stopped. Thereafter, when the output of the envelope detector 28 falls below the threshold level, it is considered that synchronization has been lost, and the sweeping is started again.

Maintaining synchronization while the sweep is stopped is performed by the delay lock loop 38. Lag phase and lead phase 2
Despread with two PN codes, detected, and the differential amplifier 32
The control voltage of the voltage controlled oscillator 34 obtained by differential amplification by
As shown in (d), the delay lock loop 38 operates so as to be stable at the synchronization point 40 where the phase difference is zero.

[0008]

In FIG. 7, a correlator constituted by band-pass filters 25 to 27 and envelope detectors 28 to 30 is used for synchronization acquisition and loss of synchronization detection and synchronization holding PN. There are three types, one for the code delay phase and the other for the synchronization holding PN code advance phase, and if the delay phase correlator and the advance phase correlator are not balanced, the difference is given by the output difference between the two correlators. There has been a problem that the control voltage waveform of the voltage controlled oscillator 34 is distorted and an offset is generated in the delay lock loop 38, thereby deteriorating performance.

The voltage controlled oscillator 34 is set so as to output a rated frequency clock to the PN code generator 36 with the voltage at the control point synchronization point 40. If the rated frequency clock is not output at the voltage, there is a problem that the loop is stabilized at the shifted point.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a spread spectrum code synchronization acquisition and holding apparatus which can reduce the number of adjusting elements and is less affected by temperature.

[0011]

Means for Solving the Problems To achieve the above object,
For this purpose, the present invention provides a first spreading code generator for demodulation, a second spreading code generator for acquisition and holding of synchronization, and a spreading code from the first spreading code generator multiplied by a received signal. And a second multiplier for despreading the received signal by multiplying the received signal by a spreading code from the second spreading code generator.
A single correlator for obtaining the correlation value of the output of the second multiplier, and for synchronization acquisition, the phase of the spreading code of the second spreading code generator is shifted over one cycle, and When the maximum value of the correlation value by the correlator exceeds a predetermined value, the first and second phases are added to the phase giving the maximum value.
In order to make the phases of the spread codes of the spread code generators coincide with each other and to maintain synchronization, the spread codes of the first spread code generator
The phase of the spreading code of the second spreading code generator is shifted by a small predetermined width without shifting the phase, and the phase giving the maximum value of the correlation value by the correlator at that time is
Control means for matching the phases of the spread codes of the first and second spread code generators.

[0012]

[0013]

FIG. 1 is a block diagram showing an embodiment of the present invention.

1 is an input terminal of a spread spectrum signal which is a received signal, 2 and 3 are multipliers, 4 is a band-pass filter, 5
Is an envelope detector, which includes a band-pass filter 4 and an envelope detector 5
Constitutes the correlator 6. 7 is a PN code generator for demodulation,
Reference numeral 8 denotes a PN code generator for synchronizing and holding, and multipliers 2 and 3
Output the PN codes 9 and 10 for. 11 and 12 are P
A programmable counter 13 for supplying a clock CK to the N code generators 7 and 8;
A CPU which controls the PN code generator 12 and outputs a clear signal 14 for setting the phase of the PN code of the PN code generators 7 and 8 to 0;
15 is an A / D converter for converting a correlation value into a digital value;
16 is a memory.

FIG. 2 shows the synchronization acquisition operation, that is, the operation of the CPU 13 for setting the phase difference between the PN code included in the received signal and the PN codes 9 and 10 generated by the PN code generators 7 and 8 within one chip. It is a flowchart shown. [Step 1] The CPU 13 sends a clear signal 14 to the PN code generators 7 and 8 at the same time, and the two PN codes 9 and
The phase of 10 is set to 0. Then, initialization is performed so that the programmable counters 11 and 12 output the rated frequency clock of the PN code. [Step 2] Address P, MP, MA of the memory 16
Address X is set to 0 each. PN code 9 and P at address P
A value indicating the phase difference of the N code 10 in units of one chip is stored. If one cycle of the PN code is M chips, 0 ≦ P ≦ M
It is. However, P = 0 and P = M are the same. At the MP address, a value indicating the phase of the PN code 10 giving the maximum correlation value is stored. 0 ≦ MP ≦ M. The maximum correlation value is stored in the address MAX. 0 ≦ MAX. [Step 3] The CPU 13 controls the programmable counter 12 to change the pulse width of the clock CK to the PN code generator 8 to delay the phase of the PN code 10 by one chip. At this time, the phase of the PN code 9 is not shifted. How to shift the phase will be described later. [Step 4] The value of the address P in the memory 16 is incremented by one. [Step 5] The CPU 13 waits for one cycle of the PN code 10. During this time, the received signal is split into two,
Are multiplied by the PN codes 9 and 10, respectively, and despread. The signal despread by the multiplier 3 passes through a band-pass filter 4, is detected by an envelope detector 5, and is subjected to A / D conversion.
The digital signal is converted by the converter 15
13 is input. [Step 6] The CPU 13 samples the envelope detected correlation value over one cycle of the PN code 10. [Step 7] The sampled correlation value is compared with the value of the MAX address. Now, since MAX = 0 at the beginning, the correlation value is naturally large, so that the process proceeds to step 8.
If the correlation value of the current sampling is equal to or smaller than the value of the MAX address, the process jumps to step 9 . [Step 8] The value of address P is stored in address MP, and the correlation value of the current sampling is stored in address MAX. [Step 9] It is determined whether or not P = M, and Steps 3 to 8 are repeated while P <M. That is, the correlation value sampling is repeated until the phase difference between the PN code 9 and the PN code 10 becomes M chips, and the maximum correlation value and the phase thereof are stored at addresses MP and MAX. When P = M, step 1
Move to 0. [Step 10] It is determined whether or not the maximum correlation value stored at the MAX address is greater than the threshold level sh. If it is larger, the process proceeds to step 11, and if it is smaller, the process proceeds to step 12. [Step 11] The phases of the PN code 9 and the PN code 10 are delayed by the MP chip. As a result, the phase difference between the PN codes 9 and 10 included in the received signal is within one chip.

In the above operation, since the correlation value is sampled while being delayed one chip at a time, sampling is performed at the timing shown in FIG. 3 and a correlation value exceeding the threshold level sh cannot be obtained. It is possible. This is the case in step 10 where the maximum correlation value is equal to or lower than the threshold level sh.
[Step 12] The phases of the PN code 9 and the PN code 10 are delayed by 1/2 chip, and the synchronization acquisition operation from Step 2 is performed again.

Here, how the phases of the PN codes 9 and 10 are shifted by changing the pulse width of the clock CK of the programmable counters 11 and 12 will be described with reference to FIG.

The programmable counters 11 and 12 are CP
At the moment when the comparison value set by U13 matches the count value, the count value is cleared and toggle output is performed. For example, the programmable counter 1
The frequency of the clock input to 1, 1 and 12 is changed to PN code 9,
Assuming that the frequency is 40 times the rated frequency of 10, if the comparison value is set to 20 by the CPU 13, 20 clocks are input to the programmable counters 11 and 12 so that the output of the programmable counters 11 and 12 is P.
A half cycle of the clock CK of the N code generators 7 and 8 is formed, and the next half cycle is formed by inputting the next 20 clocks, and the PN code generators 7 and 8 are input by a total of 40 clock inputs. Since one cycle of the clock CK is formed, the output frequencies of the programmable counters 11 and 12 become the rated frequencies of the PN codes 9 and 10.

[0019] Taking as an example the case of delaying 1/2 chip phase in step 12, CPU 13 is not monitoring the output of the programmable counter 12, the count value at time t ₁ in FIG. 4 (a) (= 20) is As soon as it is cleared, the comparison value is rewritten to 40. Then, when the count value (= 40) is cleared at time t ₂ , the comparison value is rewritten to 20 again. This operation, the clock CK during the high level at time t ₁ ~t ₂ continues, phase 1
/ 2 chips later. When the phase is advanced by １ ／, the comparison value may be rewritten to 10 at time t ₃ and returned to 20 at time t ₄ , as shown in FIG. 4B. Similarly, by rewriting the comparison value to a value in the range of 1 to 40, the phase can be arbitrarily delayed or advanced by a shift width having 1/40 chip as a minimum unit. Also, when the phase is shifted by such a width that the speed of the CPU 13 cannot keep up with the above operation, the shift may be performed a plurality of times.

Next, the synchronization maintaining operation will be described. FIG. 5 is a flowchart showing the synchronization maintaining operation, that is, the operation of the CPU 13 which keeps the phase difference between the PN code and the PN codes 9 and 10 in the received signal within one chip close to 0 and keeps the phase difference at 0. It is.

At the time of capturing, the correlation was obtained while delaying one chip, so that the phase of the PN code 10 should have a maximum correlation value within ± 1/2 chip. [Step 21] The CPU 13 changes the pulse width of the clock CK to the PN code generator 8 by controlling the programmable counter 12, and advances only the phase of the PN code 10 by 1/2 chip. Here, it is assumed that the minimum shift width defined by the clock speed input to the programmable counters 11 and 12 is 1/40. From this step, the operation of bringing the phase difference closer to 0 is started.
The phase will be shifted between 1/2 chips. [Step 22] The CPU 13 sets the comparison value X of the programmable counter 12 to 20. [Step 23] -X is stored at the address P 'of the memory 16. The address P 'is a value indicating the phase difference between the PN code 9 and the PN code 10 in units of 1/40 chip (−20 ≦ P ′ ≦ 20, −
The code is assumed to be a phase advance). -X
Means that the advance of -20/40, that is, -1/2 chip, is stored in the memory 16. [Step 24] The CPU 13 waits for one cycle of the PN code 10. During this time, the received signal is split into two,
The PN codes 9 and 10 are respectively multiplied by 3 and despread. The signal despread by the multiplier 3 passes through the band-pass filter 4, is detected by the envelope detector 5, and
The signal is converted into a digital signal by the D
It is input to U13. [Step 25] The CPU 13 samples the correlation value detected by the envelope detection over one period of the PN code 10. [Step 26] -X is stored in the address MP ', and the correlation value of the current sampling is stored in the address MAX'. MP '
At the address, a value indicating the phase of the PN code 10 giving the maximum correlation value is stored. −20 ≦ MP ′ ≦ 20. MA
The maximum correlation value is stored at the address X '. 0 ≦ MAX ′. [Step 27] The CPU 13 delays only the phase of the PN code 10 by 1/40 chip. [Step 28] The value of the address P 'is incremented by one. [Step 29] The CPU 13 waits for one cycle of the PN code 10. During this time, the received signal is subjected to envelope detection, and the CPU 1
3 is input. [Step 30] The CPU 13 samples the envelope detected correlation value over one period of the PN code 10. [Step 31] The sampled correlation value is MAX ′
Compare with the address value. If the correlation value is larger, the process proceeds to step 32, where the correlation value of the current sampling is set to MA.
If the value is equal to or less than the value of the address X ', the process jumps to step 33. [Step 32] The value of the address P 'is stored in the address MP', and the correlation value of the current sampling is stored in the address MAX '. [Step 33] It is determined whether or not P '= X, and -20 <
Steps 27 to 32 are repeated while P <20. That is,
Correlation value sampling is repeated until the phase difference between the PN code 9 and the PN code 10 becomes + ／ chip, and the maximum correlation value and the phase thereof are stored at addresses MP ′ and MAX ′. When P ' = 20, the process proceeds to step 34. [Step 34] The phase of the PN code 10 is shifted to the phase indicated by (value stored at address MP '/ 40). [Step 35] The phase of the PN code 9 is adjusted to the phase of the PN code 10. As a result, the P included in the received signal is
This means that the phase difference between the N code and the PN codes 9 and 10 is within 1/2 of the minimum shift width (within ± 1/80 chip). [Step 36] It is determined whether or not the maximum correlation value stored at the address MAX 'is larger than the threshold level sh. If it is less than this, it is considered that synchronization has been lost, and the process returns to step 2 of the synchronization acquisition operation in FIG. [Step 37] The CPU 13 changes the pulse width of the clock CK to the PN code generator 8 by controlling the programmable counter 12, and advances only the phase of the PN code 10 by 3/40 chips. From this step, the operation of keeping the phase difference at 0 starts, and in this operation, ± 3 /
The phase will be shifted between 40 chips. [Step 38] The CPU 13 sets the comparison value X of the programmable counter 12 to 3. After this, step 2
3 and the steps 23 to 38 are repeated.

Although the above-described synchronization maintaining operation has two stages of an operation of approaching 0 and an operation of maintaining the same at 0, it may be performed in one stage of only the operation of approaching 0, or may be performed in two or more stages of the operation of approaching 0. A total of three or more stages may be used.

In the illustrated embodiment, the PN code generator 8
Since the phase of the code 10 is shifted independently of the PN code generator 7 so that the single correlator 6 performs synchronization acquisition and hold, there is no need to consider the balance of the correlator. , Fewer adjustment elements,
It can be less affected by temperature.

When synchronization is maintained by a single correlator, it is not possible to determine whether the phase shift is advanced or delayed just by changing the correlation value. Therefore, useless phase shift is performed to deteriorate the performance of information demodulation. Although it is conceivable that two PN code generators 7 and 8 are used, the phase of one PN code generator 7 is fixed and the phase of the other PN code generator 8 is shifted during sampling of the correlation value. Thus, it is possible to determine whether the phase difference is advanced or delayed.

Conventionally, if the correlation value exceeds the threshold level, it is determined that synchronization has been acquired, and the process is shifted to holding. Therefore, there may have been another peak value and it may have been overlooked. Since the synchronization acquisition operation obtains the correlation while shifting the phase for one cycle and finds the maximum value, erroneous detection and oversight of the synchronization can be reliably prevented.

Although it is conceivable that the spread spectrum signal is momentarily interrupted in a poor transmission path, the conventional out-of-synchronization detection results in a loss of information for a long time until the synchronization is acquired again. On the other hand, in the illustrated embodiment, the received signal is despread by the demodulating PN code generator 7 and the multiplier 2 even during correlation value sampling and sent to the information demodulator, thereby minimizing information loss. be able to.

[0027]

As described above, according to the present invention, a first spread code generator for demodulation, a second spread code generator for synchronization acquisition and holding, and a first spread code generator are provided. A first multiplier for despreading the received signal by multiplying the received signal by a spread code from the transmitter, and demultiplexing the received signal by multiplying the received signal by a spread code from the second spread code generator. A second multiplier for spreading, a single correlator for obtaining a correlation value of an output of the second multiplier, and a phase code of a spreading code of the second spreading code generator for synchronization acquisition. When the maximum value of the correlation value by the correlator at that time exceeds a predetermined value, the phase of the spread code of the first and second spreading code generators is shifted to the phase giving the maximum value. In order to match phases and maintain synchronization,
The phase of the spreading code of the first spreading code generator is shifted.
Is shifted in without the second spread code generator of the diffusion phase small predetermined width code causing, the phase which gives the maximum value of the correlation value by the correlator at that time, the first and second spreading code Since there is provided control means for making the phases of the spread codes of the generator coincide with each other , the number of adjustment elements can be reduced, and the influence of temperature can be reduced.
Further, erroneous detection and oversight of synchronization can be reliably prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a flowchart showing a synchronization acquisition operation of a CPU in FIG. 1;

FIG. 3 is a diagram illustrating a relationship between a sampling point and a correlation value in a synchronization acquisition operation.

FIG. 4 is a diagram showing an operation of the programmable counter in FIG. 1;

FIG. 5 is a flowchart illustrating a synchronization holding operation of the CPU in FIG. 1;

FIG. 6 is a diagram showing an autocorrelation function of a PN code of M chips for one cycle.

FIG. 7 is a block diagram showing an example of a conventional spread spectrum code synchronization acquisition holding device.

FIG. 8 is a diagram showing output waveforms of an envelope detector and a differential amplifier in FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2, 3 Multiplier 4 Band pass filter 5 Envelope detector 6 Correlator 7, 8 PN code generator 9, 10 PN code 11, 12 Programmable counter 13 CPU 14 Clear signal 15 A / D converter 16 memory CK clock sh threshold level

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04J 13/00 H04L 7/00

Claims (1)

(57) [Claims] 1. A first spreading code generator for demodulation, a second spreading code generator for synchronizing acquisition and holding, and multiplying a received signal by a spreading code from the first spreading code generator. A first multiplier for despreading a received signal by
A second multiplier for despreading the received signal by multiplying the received signal by a spreading code from the spreading code generator of the above, a single correlator for obtaining a correlation value of an output of the second multiplier,
For synchronization acquisition, the phase of the spreading code of the second spreading code generator is shifted over one cycle, and when the maximum value of the correlation value by the correlator at that time exceeds a predetermined value, the maximum The phase of the spreading code of the first and second spreading code generators is matched with the phase giving the value, and the phase of the spreading code of the first spreading code generator is maintained for synchronization.
Is shifted at a small predetermined width said second spreading code generator of spread code phase without shifting the, the phase which gives the maximum value of the correlation value by the correlator at that time, the first and second Control means for matching the phases of the spread codes of the spread code generator.