JP2903526B2 - Pulse generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator, and more particularly, to a pulse generator for generating a fuel injection pulse in an engine control of an automobile.

[Conventional technology]

Recently, many microcomputers are used for controlling the engine of a vehicle. Among the engine controls, the most central control is fuel injection control, and the microcomputer calculates a reference injection amount based on the intake air amount and the engine speed. Multiplying by the correction coefficient obtained from the measured value such as the amount of oxygen contained in the exhaust gas, the optimal fuel injection amount is converted into the injection time,
By activating the output port for a desired injection time, fuel injection is performed for each cylinder.

Normally, a specific position of a rotation cycle for each cylinder, for example, a signal indicating a top dead center or a suction start timing is used as a reference signal, which is accepted by the microcomputer as an interrupt signal, and the fuel injection from the reference point is performed by an interrupt processing program. The start time is set using hardware such as a timer. Then, the output port is set to the active level by the interrupt processing program started by the interrupt signal from the timer, and the fuel injection end time is set again using the timer. Next, in the interrupt processing program started by the interrupt signal from the timer, the output port is made inactive and the fuel injection ends.

FIGS. 7A and 7B show a fuel injection pulse generation pattern (the horizontal axis is time) in the case of a four-cylinder engine. From four output ports P ₀ to P ₃ in FIG., The fuel injection pulse is output in the time period corresponding to each cylinder. The rising of the pulse indicates the timing of starting the fuel injection, and the falling of the pulse indicates the timing of ending the fuel injection. There is a reference signal timing before the fuel injection start timing, which is shown in FIGS. 7 (a) and 7 (b).
Not shown. The high level period of the pulse indicates the fuel injection time, that is, the fuel injection amount. The longer the high level period, the larger the fuel injection amount. The pattern of the pulse generation in the fuel injection control takes various forms depending on the control method, but in the case of this example, the finest control is possible by a method of controlling each cylinder independently. .

FIG. 7A shows a fuel injection pulse pattern when the vehicle is traveling at a low speed and a constant speed, and shows a state in which pulses do not overlap with each other. FIG. 7B shows a fuel injection pulse pattern during rapid acceleration. In this pattern, pulses are overlapped for each cylinder. The actual pulse pattern will be a random combination of these two examples, depending on the current state, and the control of pulse generation from the output port will be more complex.

Hereinafter, a conventional example of the pulse generator will be described with reference to FIG. 8 and FIG.

FIG. 8 is a system block diagram of the conventional example. In this conventional example, a data bus 400 and an address bus 401 are shown.
In response to the above, an arithmetic and logic unit (hereinafter, referred to as ALU) 201, a temporary register 202, a general-purpose register 203 acting as high-speed storage means, an address buffer 204 (represented as AB in the figure), a micro address A generation unit (hereinafter, referred to as μ address generation unit) 205, a program counter (hereinafter, referred to as PC) 206, means for holding a program execution state (hereinafter, referred to as PSW) 207, a microprogram ROM (hereinafter, referred to as μROM) 208, Central processing unit (hereinafter referred to as CPU) 200 including timing control unit 209
, An interrupt request generation circuit (hereinafter referred to as INTC) 210 including an interrupt request flag 211, a program memory 212, a data memory 213, and peripheral hardware 214. In FIG. 8, a display abbreviated in parentheses is shown.

The INTC 210 receives several interrupt signals from external hardware, selects one interrupt source with the priority assigned to each interrupt source, and sets the interrupt request flag 211 corresponding to that interrupt source. I do. When there are n interrupt requests, n interrupt request flags 211 are set. However, in FIG. 8, only one interrupt request flag 211 is described as an example. In addition,
An interrupt signal from external hardware, a priority determination unit, and the like are not shown.

Conventional interrupt processing is usually called vector interrupt, and a vector table space is preset in a memory space, and an entry address of an interrupt processing program corresponding to each interrupt source is stored in this space. ing. When a vector interrupt occurs, a branch is made to an entry address corresponding to the interrupt source.

FIG. 9 is a block diagram of the peripheral hardware 214 in the conventional example. The peripheral hardware 214 is connected to the data bus 4
00 corresponding to the clock-based free-running timer 215, compare registers 216, 218, 219, 220, and 2
21, is constituted by port output circuit 222, and an output port P ₀ to P ₃ comprises a capture register 217, the port register 223 and a buffer 224.

In this example, in the interrupt processing program based on the reference signal, a value specifying the fuel injection start timing is set in the compare register 216, and the match signal in the compare register 216 gives the fuel injection start timing for all four cylinders, coincidence signal from the register 218 to 221 is configured to provide a fuel injection termination timing corresponding to the output ports P ₀ to P _3, respectively.

Note that the match signals from the respective compare registers are output to the INTC 210 as interrupt request source signals, respectively.
Expressed as INT. Hereinafter, all signals represented by INT have the same meaning.

In the following, the compare register 216, the interrupt processing program by the reference signal, as the value that specifies the fuel injection timing corresponding to the output ports P ₀ in advance is set, the coincidence signal from the compare register 216 is generated The operation will be described from the point at which the operation is performed.

In FIG. 8, in the normal instruction processing, the program address stored in the PC 206 is transferred to the address buffer 204, the address bus 401 is driven, and the next instruction to be executed is fetched from the program memory 212. . The fetched instruction is transferred to the μ address generation unit 205 via the data bus 400. μ address generation section 205,
The address of the μROM 208 is generated from the transferred instruction code. Thereafter, according to the instruction of the μ program corresponding to the instruction stored in the μ ROM 208, the general-purpose register 20
3. Instruction processing is performed by operating the ALU 201, the temporary register 202, and the like.

The INTC 210 continually samples whether or not an interrupt request has been issued from the peripheral hardware 214 independently of the processing in the CPU 200, and if a request has been issued, selects one request and sends a request to the request source. Interrupt request flag corresponding to
Set 211.

When a match signal from compare register 216 is generated,
The capture register 217 captures the value of the free running timer 215 at that time. Then, the compare register 216
Generates an interrupt request to the INTC 210. When the INTC 210 receives the interrupt request and sets the interrupt request flag 211, the interrupt request signal 4
03 is output to the timing control unit 209.

The last command of the μ program is a command for normally detecting whether or not an interrupt has occurred. When this command is issued, the timing controller 209 samples the presence or absence of the interrupt request signal 403. If the interrupt request signal 403 is active, an interrupt request clear signal 402 is output to the INTC 210, and the interrupt request flag 211 is cleared.

Next, the PC 206 and the PSW 207 are connected to the stack pointer (CPU 200
(The register is set inside but not shown)
Is saved in the stack space pointed to by the data memory 213.
The entry address of the interrupt processing program corresponding to the interrupt source stored in the vector table set at the specific address is read out, and set to the PC 206 via the data bus 400. The interrupt processing program starts executing from the program address newly set in the PC 206.

In the interrupt processing program, first, the port register 22
By setting bit 0 of 3 to “1”, the output pulse from the output port P ₀ is set to the high level, and data corresponding to the fuel injection pulse width in the cylinder corresponding to the output port P ₀ is added. The result is transferred to compare register 218.

In the processing of the instruction that terminates the interrupt processing program, the PC value and PSW value saved in the stack space are returned to the PC 206 and PSW 207, respectively, so that processing from the next instruction at the time when the interrupt occurs is restarted. I do.

Next, when a coincidence signal from the compare register 218 indicating the fuel injection end timing is generated during the normal instruction execution, the INTC 210 accepts the interrupt request and the interrupt request signal 403 outputs the interrupt request signal 403 as described above. Output to 209.

When a command is issued from the μ program to detect whether or not an interrupt has occurred, the timing controller
209 samples the presence or absence of the interrupt request signal 403. If the interrupt request signal 403 is active, an interrupt request clear signal 402 is output to the INTC 210, and the interrupt request flag 211 is cleared.

Next, the PC 206 and the PSW 207 are evacuated to the stack space, and branch to an entry address of an interrupt processing program corresponding to an interrupt source stored in a vector table set at a specific address in the data memory 213, The interrupt processing program starts executing.

The interrupt processing program are the fuel injection termination processing for output ports P _0, by setting bit 0 of the port register 233 to "0", the output pulse from the output port P ₀ to a low level, the corresponding cylinder Is terminated.

In the processing of the instruction that terminates the interrupt processing program, the PC value and the PSW value saved in the stack space are returned to the PC 206 and the PSW 207, so that the processing from the next instruction when the interrupt occurs can be performed. Resume. Similar processing is performed similarly for P ₃ from the output port P _1. As described above, one conventional example of the pulse generator for controlling the automobile engine has been described, but the basic processing functions of the conventional general pulse generator are almost as described above.

[Problems to be solved by the invention]

In the above-described conventional pulse generator, the microcomputer receives a reference signal for outputting a fuel injection pulse as an interrupt signal, and performs control such as setting of a fuel injection time by an interrupt processing program. For this reason, when the engine speed increases and the number of times the reference signal is generated increases, many interrupt requests such as a reference signal interrupt, a fuel injection start interrupt, and a fuel injection end interrupt occur, and the PC value and the PSW value at that time are also generated. When returning to the main process from an interrupt processing program or when saving to the stack, processing to restore the contents of the stack to the PC 206 and PSW 207 occurs frequently, resulting in a huge amount of CPU time dedicated to saving and restoring. .

On the other hand, the CPU also performs various other tasks such as ignition timing control and idle rotation control in addition to fuel injection control, and when the engine speed increases, the CPU time allocated to these main processes is reduced. Less, and in some cases,
It is possible that processing that cannot be handled at all may occur. Accordingly, it has become very difficult to control the engine by a microcomputer in a vehicle model equipped with a high-speed rotation and a multi-cylinder engine these days.

In recent engine control, high-precision fuel injection control is required due to requirements such as exhaust gas regulations and fuel cost reduction, and the fuel injection start timing and fuel injection end timing can be controlled with a minimum error. In addition, it is becoming necessary to control each cylinder independently. In the conventional method of controlling these requests only by software processing, there is a delay in the time between the occurrence of an interrupt factor and the start of the interrupt processing program, and a delay due to the time required to write data to the output port. Occurs and high-precision control cannot be expected. In order to perform high-precision control, dedicated hardware based on signals within several tolerances and higher resolution than a series of processing cycles and with direct control by hardware is provided. There must be. Specifically, a dedicated hardware such as a timer for counting up the number of clocks, a capture register for storing the value of the timer when an event occurs, and a compare register for indicating that a predetermined value of the timer has been matched is obtained. Requires hardware. Here, the capture register is used to store fuel injection start timing, and the compare register is used to generate fuel injection start timing and end timing. As described above, since the output pulses from the output port take various patterns, overlapping and losing, there is no software intervention and only two compare registers for the fuel injection start timing and the end timing are used. Control corresponding to four cylinders cannot be performed. Therefore,
In order to control only by hardware, four sets of compare registers are required, and the amount of hardware is increased, resulting in an economic burden. Naturally, if the number of cylinders increases to six or eight, the number of compare registers also increases to six or eight. Especially when applied to a configuration in which a CPU and peripheral circuits are integrated on a single board, such as a single chip. Increase.

In relation to the reference signal fuel injection start timing,
If the reference signal is selected such that the reference signal for the cylinder (n + 1) always comes later than the fuel injection start timing for the cylinder (n), as shown in FIG. 9, the capture register and the fuel injection start are started. Although only one compare register for generating the timing may be used, the cylinder (n +) may be arranged at a timing shorter than the fuel injection end timing of the cylinder (n).
In consideration of the fact that the fuel injection start timing of 1) may come earlier in time, the compare registers that provide the fuel injection end timing must be provided for the number of cylinders, which also increases the amount of hardware. Results.

That is, in order to respond to the recent increase in the accuracy of automobile engine control, the conventional pulse generation circuit generates a signal having a higher resolution than a series of control processing cycles and within an allowable error range in control accuracy. It is necessary to add dedicated hardware as a base and directly control the hardware. Therefore, there is a disadvantage that the amount of hardware including the dedicated hardware is significantly increased.

[Means for solving the problem]

A pulse generation circuit according to the present invention, in a pulse generation device for controlling an automobile engine using a CPU, means for generating a request for asynchronous interrupt processing to the CPU and also generating a request for predetermined data processing. An INTC including a request for interrupt processing and a request for the predetermined data processing, and a processing mode information for specifying a processing mode of the predetermined data processing together with required data. A data register that also stores the data, a free-running timer, a capture register that captures the value of the free-running timer at a predetermined timing to determine the fuel injection end timing, and that the value of the free-running timer is a predetermined value. A pair of compare registers for generating fuel injection start timing and end timing when they match, and engine control Output ports for outputting fuel injection pulses, a first bit selection register for selecting a port for generating fuel injection pulses, and a first bit selection register.
A peripheral circuit including a control circuit, a second bit selection register for selecting a port to stop generating fuel injection pulses, and a second control circuit;
Includes a PC for holding an execution address of an instruction, a stage for holding an execution state of a program, a high-speed storage unit, and a μROM, wherein a request for the predetermined data processing is generated from the INTC, When it is detected that the instruction of the predetermined data processing is given, the instruction execution processing is interrupted while retaining the contents of the PC and the contents of the means for retaining the execution state of the program. A vehicle output from the plurality of output ports by executing a microprogram command stored at a predetermined address of the μROM according to information and operating the pair of compare registers, the capture registers, and the data memory. The fuel injection pulse for engine control is controlled.

〔Example〕

Next, the present invention will be described with reference to the drawings. First
FIG. 1 is a system block diagram of a first embodiment of the present invention;
FIG. 2 is a block diagram of peripheral hardware in the first embodiment.

As shown in FIG. 1, the first embodiment has an ALU 10 corresponding to the data bus 300 and the address bus 301.
1, temporary register 102, general-purpose register 103, address buffer 104, μ address generator 105, PC 106, PSW 10
7, CPU 100 including μROM 108 and timing control unit 109
, An INTC 110 including an interrupt request flag 111 and a form designation flag 112, a program memory 113, and a data memory 1
14 and peripheral hardware 115.

In addition, as shown in FIG.
5 is a free-running timer 116, a compare register (described as COMP 1 in the figure) 117 and a compare register (described as COMP 2 in the figure) 119, a capture register (described as CAP in the figure) 118, a bit Select register (SR)
120, a bit selection register (RR) 121, a control circuit 122 and 123 respectively including four AND gates 124, four RS flip-flop 126 and buffers respectively corresponding to the four output ports P ₀ to P ₃ Port output circuit including 127
125 and.

The INTC 110 receives several interrupt signals from external hardware, determines the priority assigned to each interrupt request source, selects one interrupt source having the highest priority, and selects the interrupt source. Is set to the interrupt request flag 111 corresponding to. When there are n interrupt requests, n interrupt request flags 111 and mode designation flags 112 are set respectively. However, in order to simplify the description,
Only one set is shown in the figure. In addition, an interrupt signal from external hardware, a priority determination unit, etc.
It is not particularly shown because it has no direct bearing on the gist of the present invention.

The CPU 100 can process an interrupt request from the INTC 110 in two forms. One is a conventional vector interrupt processing, and the other is a processing mode which is a feature of the present invention. When an interrupt request is generated, the data memory 114 is stored in the data memory 114 without referring to the vector table. Based on the processing mode information set in advance for the specific address of
This is a processing mode for executing predetermined data processing. Hereinafter, this predetermined data processing is referred to as a macro service. For the above two processing modes, whether the vector interrupt or the macro service is specified is specified by the mode specifying flag 112. When the CPU 100 specifies “0” in the mode specifying flag 112, the vector interrupt or the macro service is specified. When "1" is specified, it is specified as a macro service.

Next, processing mode information for specifying the processing mode of the macro service of the present invention will be described. FIG. 3 is a diagram showing an example of a processing configuration information configuration of a macro service, and FIG. 4 is a diagram showing a macro service processing flowchart in the first embodiment.

The processing mode information is arranged at a specific address in the data memory 114. The processing mode information of this embodiment includes a macro service mode and a 2-byte header section having a channel pointer (denoted as PTR in FIG. 3). , A 13-byte macro service channel pointed to by the channel pointer. The macro service channel of the present embodiment has a configuration assuming fuel injection control of four cylinders, and includes an initial counter (described as INIT in FIG. 3), reset data for specifying the fuel injection pulse width, and temporary Word buffer (P _{0 to} P
₃ ), a write counter indicating the write position to the word buffer (described as WR CNT. In FIG. 3), and a read counter indicating the read position from the word buffer (described as RD CNT. In FIG. 3). ).

In the compare register 117, data indicating a displacement from a reference signal in fuel injection control to a fuel injection start timing is stored by the CPU 100. The data setting timing is set by an interrupt processing program when the reference signal generates an interrupt.
As described in the conventional example, in the present embodiment, a reference signal for giving a fuel injection start timing to a plurality of cylinders is selected by only one compare register 117.

The macro service according to the present embodiment includes a compare register 117.
And a match signal 308 from the compare register 119. Before the macro service is activated, the CPU 100 initializes a macro service channel and hardware. The macro service channel INIT, WR CNT., And RD CNT. Are set to 4 in the case of four cylinders. The bit selection register (S
To R) 120 and bit selection register (RR) 121, first to the output port should output a fuel injection pulse to specify that the P _0, bit only corresponding to the output ports P ₀ "1" Otherwise, it is set to “0”.

The macro service will be described below in accordance with the fuel injection pulse patterns shown in FIGS. 7 (a) and 7 (b).

In the case of the fuel injection pulse pattern shown in FIG. 7A, first, the match signal 3 from the compare register 117 is output.
When 07 occurs, only the RS flip-flop 126 corresponding to the output port P ₀ is set from the initial value of the bit selection register SR 120, the output level from the output port P ₀ becomes high, and the fuel injection to the cylinder 0 is performed. Is started.
At the same time, the value of the free running timer 116 is stored in the capture register 118 by the coincidence signal 307. The match signal 307 generates an interrupt request to the INTC 110. INTC 110 provides match signal 3 via data bus 300
When 07 is accepted, the interrupt request flag 111 corresponding to this source is set, and the interrupt request signal 303 is activated. The timing control unit 109 samples the interrupt request signal 303 at the end of the instruction processing.
Since 03 is active, the configuration specifying signal 305 is sampled. “1” indicating that the form designation signal 305 indicates a macro service
Is detected, the macro service processing entry address of the μROM 108 is generated while holding the PC 106 and the PSW 107, and the macro service is started. Thereafter, the macro service processing is executed according to the specification of the μ program of the micro service.

Hereinafter, regarding the processing flow by the μ program command,
This will be described with reference to the flowchart of FIG.

First, a macro service header using the coincidence signal 307 as an interrupt source is read from a specific address in the data memory 114. In this case, the macro service mode is set to M1 (mode name) in advance. When the macro service mode is M1, the WR CNT. And RD CNT. Are compared.

Since both WR CNT. And RD CNT. Have an initial value of 4, the contents of the capture register 118 and the reset data in the macro service channel are added using the ALU 101, and the result is compared. It is stored in the register 119.
The reset data is constantly updated by the CPU 100, and the macro service will use the reset data which is the latest fuel injection time.

Next, WR CNT. Is decremented by 1 to 3. WR CN
T. performs left shift processing because non-zero bit selection register (SR) 120, and sets only one bit corresponding to the output port P _1. In this case, since no shift-out occurs, the timing control unit 109 outputs the interrupt request clear signal 302 to the INTC 110, and outputs the interrupt request flag 111
Is reset, and the macro service process ends. When the macro service processing ends, the timing control unit 109
Resumes normal instruction processing from the values of PC 106 and PSW 107 held.

In the case of the pulse pattern shown in FIG. 7A, since there is no overlap of the pulses, a coincidence signal 308 from the compare register 119 is generated next. Bit select register (RR) 1
In 21, only the bit corresponding to the output port P ₀ is 1 and the bits corresponding to the other output ports are 0, so only the RS flip-flop 126 of the output port P ₀ is reset, and the fuel injection to the cylinder 0 is not performed. finish. The match signal 308 generates an interrupt request to the INTC 110.

When receiving the interrupt request of the coincidence signal 308, the INTC 110 sets the interrupt request flag 111 corresponding to the source and activates the interrupt request signal 303. The timing control unit 109 samples the interrupt request signal 303 at the end of the instruction processing, but samples the configuration designation signal 305 because the interrupt request signal 303 is active.
As a result, when detecting that the form designation signal 305 is “1” indicating the macro service, the macro service processing entry address of the μROM 108 is generated while holding the PC 106 and the PSW 107, and the macro service processing is started.

In the macro service processing, first, the match signal 30
The header of the macro service using 8 as an interrupt source is read from a specific address in the data memory 114. As the specific address, an address different from the address corresponding to the above-described match signal 307 is assigned. The macro service mode is set to M2 (name of mode) in advance, and the channel pointer points to the macro service channel corresponding to the coincidence signal 307.

When the macro service mode is M2, RD CNT. Is decremented by 1 and set to 3. Since RD CNT. Is not 0, proceed to the next processing, and RD CNT. Is 3 as described above, and WD CNT.
Also, since the macro service processing on the fuel injection start timing side has reached 3, RD CNT. = WR CNT., And the process proceeds to the next processing.

In the left-shift processing of the bit selection register (RR) 121, output port P ₁ only bit for the 1, and the other bits zero. Accordingly, since no shift-out occurs, the timing control unit 109 outputs the interrupt request clear signal 302
Is output to the INTC 110, the interrupt request flag 111 is reset, and the macro service processing ends. When the macro service processing is completed, the timing control unit 109 restarts the normal instruction processing from the values of the PC 106 and the PSW 107 held. The above processing is repeated exactly as from the output port P ₀ to P _3.

In the macro service is by connexion start the fuel injection start timing for the output port P _3, similarly for the macro service mode is M1, is compared with WR CNT. And RD CNT.. In this case, since both WR CNT. And RD CNT. Are 1, the contents of the capture register 118 and the reset data in the macro service channel are added using the ALU 101, and the result is stored in the compare register 119. I do.

Next, WR CNT. Is decremented by 1 to 0. WR CN
Since T. becomes 0, the value 4 of INIT is reset to WR CNT. Next, when the left shift process of the bit selection register SR 120 is performed, a shift-out from the bit selection register (SR) 120 occurs. Therefore, the timing control unit 109 outputs the configuration change signal 304 to the INTC 110, The designated flag 112 is reset.

Since the interrupt request flag 111 is in the set state and the mode designation flag 112 is in the reset state, the INTC 110 issues a normal vector interrupt request to the CPU 100 in this case. Execute
The interrupt processing program is activated at the 4-cylinder is round, reconfigure the bit selection register (SR) 120 to the initial state comprises a fuel injection pulse output from the output port P _0.

Next, the macro service is by connexion start the fuel injection end timing with respect to the output port P _3, since the macro service mode is M2, to 0 performs 1 decremented RD CNT.. Since RD CNT. Becomes 0, RD CN
Set INIT value 4 to T. Since RD CNT. Is 4, and WR CNT. Is also 4 in the macro service processing on the fuel injection start timing side, WR CNT. = RD CNT., And the process proceeds to the next processing.

Since shift-out occurs due to the left shift processing of the bit selection register (RR) 121, the timing control unit 109
Outputs the form change signal 304 to the INTC 110 and resets the form designation flag 112.

Since the interrupt request flag 111 is in the set state and the mode designation flag 112 is in the reset state, the INTC 110 issues a normal vector interrupt processing request to the CPU 100 in this case. Execute the process. The interrupt processing program is started in the fuel injection end timing is also would be activated at the 4-cylinder is round, reconfigure the bit selection register (RR) 121 to the initial state, the fuel injection pulse from the output port P ₀ Prepare for output.

Then, when the fuel injection pulse pattern shown in FIG. 7 (b), the first coincidence signal 307 from the compare register 117 is generated, only the RS flip-flop 126 corresponding to the output ports P ₀ is set , such an output pulse is high level from the output port P ₀ connexion, fuel injection for the cylinder 0 is started. Also, the match signal 307 sets the interrupt request to INTC
Occurs for 110 and starts the macro service. The processing procedure up to this point is exactly the same as in the case of FIG. 7A described above.

Also in this case, since the macro service mode is M1, the WR CNT. Is compared with the RD CNT. WR CNT. And R
Since both D CNT. Have an initial value of 4, the contents of the capture register 118 and the reset data in the macro service channel are added using the ALU 101, and the result is stored in the compare register 119.

Next, WR CNT. Is decremented by 1 to 3. WR CNT.
Performs a left shift processing because non-zero bit selection register (SR) 120, and sets only one bit corresponding to the output port P _1. In this case, since no shift-out occurs, the timing control unit 109 outputs the interrupt request clear signal 302 to the INTC 110, and outputs the interrupt request flag 111
Reset to end macro service. When the macro service ends, the timing control unit 109 restarts and executes normal instruction processing from the values of the PC 106 and the PSW 107 held.

In the case of the pulse pattern shown in FIG. 7B, there is a pulse overlap, and the match signal 308 from the compare register 119 is output.
Occurs, the match signal 307 from the compare register 117 is generated again. At this time, only the RS flip-flop 126 corresponding to the output port P ₁ is set, the output pulse from the output port P ₁ becomes high level, the fuel injection is started with respect to the cylinder 1, both both cylinder 0 and cylinders 1 Fuel injection will be performed.

The match signal 307 generates an interrupt request to the INTC 110 and starts macro service. Even in this case,
Since the macro service mode is M1, WR CNT. And RD CN
Perform T. comparison. Unlike the previous case, WR CNT. Is 3, R
Since D CNT. Is 4, the contents of the capture register 118 and the reset data in the macro service channel are
Addition using ALU 101, the result is [PTR-WR CN
T.X2-4] That [PTR-10] wherein addresses represented by the, in this case is stored in the word buffer (for P _1).

Next, WR CNT. Is decremented by 1 to 2. WR CNT.
Since is not 0, it performs a left shift operation of the bit selection register (SR) 120, and sets only one bit corresponding to the output port P _2. In this case, since no shift-out occurs, the timing control unit 109 outputs the interrupt request clear signal 302 to the INTC 110, and outputs the interrupt request flag.
Reset 111 to end macro service.

When a match signal 307 from the compare register 117 occurs again, at this time, only the RS flip-flop 126 corresponding to the output port P ₂ is set, connexion such output pulse is high level from the output port P _2, for cylinder 2 Fuel injection is started.

The match signal 307 generates an interrupt request to the INTC 110 and starts macro service. Also in this case, since the macro service mode is M1, the WR CNT. And the RD CNT. Are compared. Since WR CNT. Is 2 and RD CNT. Is 4, the contents of the capture register 118 and the reset data in the macro service channel are added using the ALU 101,
The result is [PTR-WR CNT.x2-4],
Wherein the address represented by the 8], this case is stored in the word buffer (for P _2).

Next, WR CNT. Is decremented by 1 to 1. WR CNT.
Since is not 0, it performs a left shift operation of the bit selection register (SR) 120, and sets only one bit corresponding to the output port P _3. Also in this case, since no shift-out occurs, the timing control unit 109 outputs the interrupt request clear signal 302 to the INTC 110, resets the interrupt request flag 111, and ends the macro service processing.

When a match signal 307 from the compare register 117 occurs again, at this time, RS flip-flop of the output port P ₃
Only 126 is set, the output pulse from the output port P ₃ becomes high level, the fuel injection for the cylinder 3 is started.

The match signal 307 generates an interrupt request to the INTC 110 and starts macro service. Also in this case, since the macro service mode is M1, the WR CNT. And the RD CNT. Are compared. Since WR CNT. Is 1 and RD CNT. Is 4, the contents of the capture register 118 and the reset data in the macro service channel are added using the ALU 101,
The result is [PTR-WR CNT.x2-4],
Wherein the address represented by the 6], in this case is stored in the word buffer (for P _3).

Next, WR CNT. Is decremented by 1 to 0. WR CNT.
Becomes 0, reset the value 4 of INIT to WR CNT. Then, a left shift process of the bit selection register (SR) 120 is performed. At this time, since a shift-out occurs, the timing control unit 109 outputs the form change signal 304 to the INTC 110 and resets the form designation flag 112.

Since the interrupt request flag 111 is in the set state and the mode designation flag 112 is in the reset state, the INTC 110 issues a normal vector interrupt request to the CPU 100 in this case. Execute the process. The interrupt processing program, resetting the bit selection register (SR) 120 to the initial state comprises a fuel injection pulse output from the output port P _0.

Next, when a match signal 308 is generated from the compare register 119 that gives the fuel injection end timing to the output port P ₀ , the bit selection register (RR) 121
_Since only the bit corresponding to ₀ is 1 and the other bits are 0, only the RS flip-flop 126 corresponding to the output port P ₀ is reset, and the fuel injection to the cylinder 0 ends. The coincidence signal 308 generates an interrupt request to the INTC 110 and starts macro service. Since the macro service mode in this case is M2, the RD CNT. RD CN
Since T. is not 0, proceed to the next process, RD CNT. Is 3 and W
Since R CNT. Is initially set to 4 in the macro service processing on the fuel injection start timing side, WR CNT. And RD CNT.
[PTR-RD CNT.x2-4], that is, [PT
R-10], the address and word buffer (P
_The data indicating the fuel injection pulse width stored in ( ₁ ) is transferred to the compare register 119.

The left shift process in the bit selection register (RR) 121, only the bit for the output port P ₁ becomes 1,
Other bits are 0. In this case, since no shift-out occurs, the timing control unit 109 outputs the interrupt request clear signal 302 to the INTC 110, resets the interrupt request flag 111, and ends the macro service.

Next, when the coincidence signal 308 from the compare register 119 is generated to provide a fuel injection end timing with respect to the output port P _1, the bit selection register (RR) 121, the output port P
_Since only the bit corresponding to ₁ is 1 and the other bits are 0, only the RS flip-flop 126 corresponding to the output port P ₁ is reset, and the fuel injection to the cylinder 1 ends. The coincidence signal 308 generates an interrupt request to the INTC 110, and the macro service processing is started.

Since the macro service mode in this case is also M2, RD
Decrement 1 of CNT. To 2 RD CNT. Is 0
Therefore, the process proceeds to the next process, and the RD CNT. Is set to 2 in the macro service process at the fuel injection start timing side, and the WR CNT. Not [PTR-RD CNT.x2-4]
−8], the address and word buffer (P ₂
) Is transferred to the compare register 119.

The left shift process in the bit selection register (RR) 121, only the bit for the output port P ₂ becomes 1,
Other bits are 0. In this case, since no shift-out occurs, the timing control unit 109 outputs the interrupt request clear signal 302 to the INTC 110, resets the interrupt request flag 111, and ends the macro service processing.

Next, when the coincidence signal 308 from the compare register 119 is generated to provide a fuel injection end timing with respect to the output port P _2, bit selection register (RR) 121, the output port P
Only bits corresponding to the ₂ in 1, since the others are 0, only the RS flip-flop 126 of the output port P ₂ is reset, the fuel injection for the cylinder 2 is completed. This match signal 308 generates an interrupt request to the INTC 110,
Macro service processing is started.

Since the macro service mode in this case is also M2, RD
Decrement 1 of CNT. To 1 RD CNT. Is 0
RD CNT. Is 1 and WR CNT. Is 4 in macro service processing on the fuel injection start timing side.
WR CNT. And RD CNT. Cannot be matched because [PTR-RD CNT.x2-4], ie [PTR-6]
And the data indicating the fuel injection pulse width stored in the word buffer (for P3) are transferred to the compare register 119.

The left shift process in the bit selection register (RR) 121, only the bit for the output port P ₃ becomes 1,
Other bits are 0. In this case, since no shift-out occurs, the timing control unit 109 outputs the interrupt request clear signal 302 to the INTC 110, resets the interrupt request flag 111, and ends the macro service processing.

Next, when the coincidence signal 308 from the compare register 119 is generated to provide a fuel injection end timing with respect to the output port P _3, the bit selection register (RR) 121, the output port P
Only bits corresponding to ₃ is 1, because the other is 0, only the RS flip-flop 126 of the output port P ₃ is reset, the fuel injection for the cylinder 3 terminates. This match signal 308 generates an interrupt request to the INTC 110,
Macro service processing is started.

Since the macro service mode in this case is also M2, RD
Decrement 1 of CNT. To 0. RD CNT. Is 0
Therefore, the value of INIT is reset to 4. As a result, RD
CNT. = WR CNT.4, and no data transmission to the compare register 119 is performed, and the processing shifts to the left shift processing of the bit selection register (RR) 121. In this case, since a shift-out from the bit selection register (RR) 121 occurs,
The timing control unit 109 outputs the form change signal 304 to the INTC 110, and resets the form designation flag 112. INT
Since the interrupt request flag 111 is in the set state and the mode designation flag 112 is in the reset state, the C 110 issues a normal vector interrupt request to the CPU 100 in this case. Execute the process.

In the interrupt processing program is started in the fuel injection end timing, and resets the bit selection register (RR) 121 to the initial state comprises a fuel injection pulse output from the output port P _0.

In this embodiment, before the fuel injection end timing of the output port P _3, although the case where the fuel injection start timing for the other cylinders is not occurring, for example, before the fuel injection end timing of the output port P ₃ , when the fuel injection start timing of the output ports P ₀ has occurred, the processing of the macro service fuel injection start timing side, the capture register 118 and the reset data of the addition result, [PTR
-WR CNT.X2-4] That [PTR-12 expression address represented by the, stored in a word buffer (for P _0), then, WR CNT. = 3, and therefore, the fuel output port P ₃ In the macro service processing started at the injection end timing, the WR CNT. = 3 and the RD CNT. = 4, which are not coincident. In this case, [PTR-12] wherein the address represented by the, ie for the data stored in the word buffer (for P _0), the processing to be transferred to the compare register 119 is executed, like this in case, it is possible to obtain a fuel injection termination timing for logically without contradiction output port P _3.

Although the case of the pulse patterns shown in FIGS. 7A and 7B has been described above, the macro service processing can be applied to any combination of these two patterns.

In this embodiment, the bit selection register (S
R) 120 and the bit selection register (RR) 121 show a method in which when a shift-out occurs as a result of shift processing, a vector interrupt is generated and initialization is performed by an interrupt processing program. If some kind of correction processing is required according to the state of the above, it is set for the purpose of giving the correction timing. In a system that does not require such correction processing, the bit selection register (SW) 120 or If the rotation processing is performed on the bit selection register (RR) 121 and the macro service processing is changed so that the shift-out from bit 3 is transferred to bit 0, the macro service processing can be performed without occurrence of vector interrupt processing. Alone, complete fuel injection control is possible.

Next, a second embodiment of the present invention will be described. The configuration of the system block diagram and the processing form information of the macro service in the present embodiment are the same as those in the first embodiment, and thus the description thereof is omitted. FIG. 5 is a block diagram of peripheral hardware in the second embodiment.

As shown in FIG. 5, the peripheral hardware of this embodiment includes a free-running timer 128, a compare register (described as COMP 1 in the figure) 129 and a compare register (FIG. 13 and the capture register (CAP in the figure) 13
0, delay circuits 132 and 133, and a bit selection register (S
And R) 134, a bit selection register (RR) 135, a control circuit 136, 137 each include four AND gates 138, four RS flip-flop that corresponds to the four output ports P ₀ to P ₃
140 and a port output circuit 139 including four buffers 141
And

In FIG. 5, match signals 310 and 311 are output from compare registers 129 and 131, respectively. Bit select register (SR) 134 and bit select register (RR) 135
Has a shift register configuration, and the delay circuit 13
The signal is left-shifted by 1 bit in accordance with the signal from 2,133. In the first embodiment, the shift processing of the bit selection register (SR) 120 or the bit selection register (RR) 121 is executed according to the instruction of the macro service, but in the present embodiment, the coincidence signal 310 or 311 described above is executed. The delay circuit 132
Or by a signal delayed several clocks by 133,
The shift processing of the bit selection register (SR) 134 or the bit selection register (RR) 135 is executed.

Next, a macro service processing flow in the present embodiment is shown in FIG. Since the shift processing in the bit selection register (SR) 134 or the bit selection register (RR) 135 can be executed by hardware through the delay action of the delay circuit 132 or the delay circuit 133, the first embodiment is different from the first embodiment. In addition, the shift processing part executed by the μ service command of the macro service is deleted, and the processing speed of the macro service is improved. The other operations are exactly the same as those in the first embodiment, and thus detailed description is omitted.

〔The invention's effect〕

As described above in detail, according to the present invention, the interruption of the fuel injection start timing, the interruption of the fuel injection end timing, and the like are processed by the macro service and the vector interruption request is not generated. Even if the number increases, the CPU time is occupied in the process of saving the PC and PSW to the stack when shifting to the interrupt processing program, and the process of returning the contents of the stack to the PC and PSW when returning to the main processing from the interrupt processing program There is no.

Therefore, it becomes possible to dedicate sufficient CPU time to various tasks such as fuel injection control, ignition timing control and idle rotation control in engine control, and the microcomputer has sufficient margin even at high speed rotation with a multi-cylinder engine. Thus, there is an effect that engine control can be performed.

In addition, due to recent demands for exhaust gas regulations and reduction of fuel cost, high-precision fuel injection control is required. Signals directly control the output port to generate a fuel injection pulse, so there is no delay from the occurrence of an interrupt factor to the start of the interrupt processing program, and no delay due to the time required to write data to the output port. In addition, since engine control can be performed with a minimum error and control can be performed independently for each cylinder, there is an effect that the fuel injection amount can be adjusted with high accuracy. .

In addition, as shown in the conventional example, in order to control a plurality of cylinders corresponding to various fuel injection patterns, a plurality of sets of compare registers are required, and the amount of hardware increases. Regarding the economic burden, the macro service processing corresponding to the same macro service channel according to the present invention is applied to the fuel injection start timing and the fuel injection end timing, so that one set of compare register and Fuel injection control for a plurality of cylinders can be performed using only the capture register, and the amount of hardware can be reduced. This means that even if the number of cylinders increases to six or eight, exactly the same measures can be taken simply by increasing the number of word buffers in the macro service channel, so that an economically superior engine control system is constituted. This makes it possible to sufficiently apply the present invention to a single chip in which a CPU and peripheral circuits are integrated on a single substrate.

[Brief description of the drawings]

FIG. 1 is a system block diagram of the first and second embodiments of the present invention, FIG. 2 is a block diagram of peripheral hardware in the first embodiment, and FIG. 3 is a macro service processing. FIG. 4 shows a macro service processing flowchart in the first embodiment, FIG. 5 is a block diagram of peripheral hardware in the second embodiment, and FIG. FIG. 7 is a flowchart showing a macro service processing in the second embodiment. FIGS. 7A and 7B are diagrams showing an output pattern of a fuel injection pulse from an output port. FIG. FIG. 9 is a system block diagram of a generating circuit, and FIG. 9 is a block diagram of peripheral hardware in a conventional example. In the figure, 100, 200 ... CPU, 101, 201 ... ALU, 102, 20
2… Temporary register, 103,203 …… General-purpose register,
104, 204 ... address buffer, 105, 205 ... μ address generation unit, 106, 206 ... PC, 107, 207 ... PSW, 108, 208 ...
μROM, 109,209 …… Timing control unit, 110,210 …… INT
C, 111, 211 ... interrupt request flag, 112 ... form designation flag, 113, 212 ... program memory, 114,213 ... data memory, 115, 214 ... peripheral hardware, 116, 128, 215
…… Free running timer, 117,119,129,131,216,21
8,219,220,221 …… Compare register, 118,130,217 ……
Capture register, 120, 134 ... bit selection register (SR), 121, 135 ... bit selection register (RR), 122, 1
23,136,137 …… Control circuit, 124,138 …… AND gate, 125,
139,222 ... port output circuit, 126,140 ... RS flip-flop, 127,141,224 ... buffer, 132,133 ... delay circuit, 223 ... port register.

Claims (1)

(57) [Claims] 1. A pulse generator for controlling an automobile engine using a central processing unit, wherein a request for asynchronous interrupt processing to the central processing unit and a request for predetermined data processing are also generated. An interrupt request generating circuit including: an interrupt request requesting means for identifying the interrupt processing request and the predetermined data processing request; and specifying a processing mode of the predetermined data processing together with required data. A data memory that also stores processing mode information, a free-running timer, a capture register that captures the value of the free-running timer at a predetermined timing to determine a fuel injection end timing, and a value of the free-running timer. A pair of compare units that generate a fuel injection start timing and an end timing when they match a predetermined value Register, a plurality of output ports for outputting a fuel injection pulse for engine control, a first bit selection register and a first control circuit for selecting a port for generating the fuel injection pulse, and generation of the fuel injection pulse Peripheral hardware including a second bit selection register and a second control circuit for selecting a port to stop the operation, the central processing unit includes: a program counter that holds an execution address of an instruction; Means for holding an execution state, high-speed storage means, and a microprogram ROM, wherein the request for the predetermined data processing is generated from the interrupt request generation circuit, and the form instruction means instructs the predetermined data processing. Is detected, the contents of the program counter and the execution state of the program are stored in the program counter. The instruction execution process is interrupted while holding, and according to the processing mode information, a microprogram command stored at a predetermined address of the microprogram ROM is executed, and the pair of compare registers, the capture registers, and the data memory are executed. Controlling a fuel injection pulse output from the plurality of output ports for controlling an automobile engine.