JP2903540B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device provided with a means for relieving a defective memory cell by a redundant circuit.

[Prior Art] Conventionally, this type of semiconductor memory device has a configuration shown in FIG. FIG. 4 shows an n-bit static RAM having n I / O terminals (input / output terminals). The memory cell array unit MC is divided into n array units CA1 to CAn corresponding to the respective input / output terminals I / O1 to I / On, and the n array units have redundant memory cell columns and There are redundant memory cell rows RC1 to RCn.

A remedy method when a defective memory cell exists in the normal memory cell array will be described below.

Usually, when a defective memory cell is present, a row or column address having the defective memory cell is programmed in advance in the address program circuit AP, and when an external address input signal matches the program address, a redundant memory cell column activation signal RX And the redundant memory cell row activation signal RY is activated.

The column activation signal RX is connected to the column selection circuit X, and the row activation signal RY is connected to the row selection circuit Y. When these signals RX and RY are activated, all the normal word lines are reset, and The word line goes up. That is, all the normal row selection transistors are turned off, the selection transistors in the redundant memory cell row are turned on, and the output data of the redundant memory cell row is transmitted to the sense amplifiers SA1 to SAn. As described above, defective memory cells are electrically replaced with redundant memory cells.

[Problem to be Solved by the Invention] In the above-mentioned conventional semiconductor memory device, a redundant memory cell column and a redundant memory cell row are provided in all n memory cell array portions corresponding to I / O terminals. When repairing a defective memory cell in the memory cell array corresponding to the I / O terminal of the normal memory cell even if there is no need for the memory cell array corresponding to the other I / O terminal And the electrical replacement of the redundant memory cell is performed. For this reason, the conventional semiconductor memory device requires n redundant memory cell columns (rows) in order to relieve one defective address, and has a disadvantage that the rescue efficiency is extremely poor.

The present invention has been made in view of the above-mentioned conventional circumstances, and has as its object to provide a semiconductor memory device that rationally solves the above-mentioned disadvantages.

[Differences from the Prior Art] In contrast to the conventional semiconductor memory device described above, the present invention
Any one of the memory cell array sections corresponding to the O terminal can be set as a redundant memory cell array, so that even when defective cells are concentrated in one memory cell array section, this memory cell array section can be set. Is set to the redundant memory cell array,
Relief is possible. In addition, the remedy of a defective memory cell in the normal memory cell array unit can be replaced by specifying a defective address in I / O terminal units, so that the remedy efficiency is extremely high.

[Means and Actions for Solving the Problems] A semiconductor memory device according to the present invention has a plurality of memory cell arrays divided corresponding to a plurality of input / output terminals, and a sense amplifier of each memory cell array and each input / output terminal. In a semiconductor memory device having a plurality of input / output bus lines that can be connected to an input / output control circuit of a terminal, the semiconductor memory device can be connected to all sense amplifiers respectively associated with the plurality of memory cells in the plurality of memory cell arrays. A redundant bus line, input / output bus selecting means for selectively connecting a sense amplifier of a first memory cell array arbitrarily selected from the plurality of memory cell arrays to the redundant bus line, and the plurality of memory cell arrays The redundant bus line is connected to the second memory cell array according to a program address for accessing the second memory cell array. An address program circuit connected to an input / output control circuit of an input / output terminal corresponding to the memory cell array, and accessing the first memory cell array in place of the second memory cell array to be accessed by the program address It is characterized by doing so.

As a more specific embodiment of the present invention, n + 1 I / Os
It has memory cell arrays corresponding to terminals, and has (n + 1) sense amplifiers and (n + 1) input / output control circuits corresponding to each memory cell array unit. Further, there are (n + 1) I / O bus lines for connecting the sense amplifier output and the input / output control circuit, and each of the sense amplifier units has the sense amplifier output of any of the (n + 1) I / O bus lines. It has an I / O bus selection circuit for connecting to one of them. Further, among the n + 1 input / output control circuits, n
An address program circuit is added to each of the input / output control circuits, and an I / O bus line connected to the input / output control circuit is switched according to a program address.

Therefore, according to the present invention, in a semiconductor memory device having n + 1 I / O terminals, if there is no defective memory cell in all the memory cell array portions, the semiconductor memory device can be used as an n + 1 bit semiconductor memory device. If it exists, any one of the memory cell array units is set as a redundant memory cell array unit corresponding to the (n + 1) I / O terminals, and a defective memory cell is present in another normal memory cell array unit. In this case, n I / O terminals are electrically replaced with redundant memory cells to provide n I / O terminals.
It can be relieved as a semiconductor memory device having an O terminal.

Example Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment when the present invention is applied to a static RAM. Memory cell array section MC
Is n + 1 corresponding to n + 1 I / O terminals I / O1 to I / On + 1
The bit lines in each cell array are connected to sense amplifiers SA1 to SAn + 1 via a row selection circuit. The sense amplifier output is supplied to I / O buses B1 to Bn via I / O bus selection circuits IB1 to IBn + 1.
Connected to +1. Each I / O bus selection circuit IB1-IBn + 1
First, in the initial state, it is set so that the sense amplifier output is connected to the I / O buses B1 to Bn + 1 corresponding to the respective I / O terminals I / O1 to I / On + 1, that is, the sense amplifier SA1
Is connected to the I / O bus B1, and the output of the sense amplifier SAi is connected to the I / O bus Bi. The I / O bus Bn + 1 is used as a redundant I / O bus when the semiconductor memory device of the present embodiment is used as an n-bit static RAM. Also I
/ O buses B1 to Bn are connected to the address program circuit AP1 respectively.
Are connected to the input / output control circuits C1 to Cn via .about.APn, and the I / O bus Bn + 1 is directly connected to the input / output control circuit Cn + 1. The address program circuits AP1 to APn program defective I / O addresses only when used as an n-bit static RAM. The redundant I / O bus B is used only when an external input address matches a program address.
n + 1 is connected to the input / output control circuits C1 to Cn. Therefore, in the initial state, the input / output control circuits C1 to Cn + 1 and the corresponding normal I / O buses B1 to Bn + 1 are always connected. As described above, the semiconductor memory device of the present embodiment operates as an (n + 1) -bit static RAM in the initial state where no specific operation is applied to the I / O bus selection circuits IB1 to IBn + 1 and the address program circuits AP1 to APn.

Next, a remedy method for using the device as an n-bit static RAM when a defective memory cell exists in the entire memory cell array of the semiconductor memory device of the present embodiment will be described.

In this case, first, n + 1 cell array units CA1 to CAn + 1
Of these, any one cell array section is designated as a redundant memory cell array. Note that a defective memory cell may exist inside the redundant memory cell array.
When a memory cell having the same address as the address of the defective memory cell in the normal memory cell array section is defective, it cannot be repaired.

The redundant memory cell array is specified by operating the I / O bus selection circuits IB1 to IBn + 1. For example, when the cell array CA3 is designated as a redundant memory cell array, by programming the I / O bus selection circuit IB3,
The output of the sense amplifier SA3 is connected to the redundant I / O bus Bn + 1. At this time, the output of the sense amplifier SA4 is connected to the I / O bus B3 by programming the I / O bus selection circuit IB4. Hereinafter, similarly, the output of the sense amplifier SAi is connected to the I / O bus Bi-1. Next, a remedy method when a defective memory cell exists in the n normal memory cell arrays will be described. As described above, replacement of a defective memory cell is performed for each I / O terminal by operating the address program circuits AP1 to APn provided in each input / output circuit. Normally, each of the input / output control circuits C1 to Cn + 1 has a corresponding normal I / O bus B1 to Bn +
1 for writing or reading information to or from a memory cell in the normal memory cell array, but only when the external address input matches the program address, the redundant I / O bus Bn + 1 and the input / output control circuit C1. To Cn are connected to write or read information to or from a memory cell in the redundant memory cell array. Note that it is impossible to remedy a defective memory cell when the memory cell at the same address in the redundant memory cell array is also defective and the memory cell at the same address in the normal memory cell array of another I / O is defective. Only when there is.

FIG. 2 shows one row of the I / O bus selection circuit IBi. This circuit connects the output of the sense amplifier SAi to the I / O bus Bi-1 when the fuse F1 is cut, and the sense amplifier when the fuse F2 is cut.
The output of the SAi is connected to the redundant I / O bus Bn + 1, and is connected to the I / O bus Bi when these fuses F1 and F2 are not cut.

FIG. 3 shows an example of the address program circuit. Fe in the figure is an activation fuse of the circuit, and the input / output control circuit is always connected to the normal I / O bus when the fuse Fe is not cut. A0, ▲ ▼, Am, ▲ ▼ Am are internal address signals.When the fuse Fe is cut, the programmed address matches the external address input depending on whether the fuse of the program circuit from A0 to Am is cut or not. Only the redundant I / O bus is connected to the input / output control circuit. Depending on the method of selecting an address to be programmed in this circuit, replacement of a defective memory cell can be freely performed for each column or each row.

[Effects of the Invention] As described above, the semiconductor memory device of the present invention has n +
It has a memory cell array part corresponding to one I / O terminal,
When a defective memory cell exists in the memory cell array, any one of the n + 1 memory cell array units is used as a redundant memory cell array unit, and the defective memory cells of the other n normal memory cell arrays are used in the redundant memory cell array. It can be replaced as a semiconductor memory device having n I / O terminals by being electrically replaced with a memory cell.

Therefore, even when a large number of defective memory cells exist in a certain memory cell array section, it can be remedied by designating the memory cell array section as a redundant memory cell array section. Further, even when defective memory cells are scattered at different addresses in the memory cell array section corresponding to a plurality of I / Os, replacement is performed for each I / O, so that there is an effect that the relief efficiency is high.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of an I / O selection circuit, FIG. 3 is a circuit diagram showing an example of an address program circuit, FIG. 4 is a block diagram showing an example of a conventional semiconductor memory device. CA1 to CAn + 1 ... memory cell array, SA1 to SAn + 1 ...
Sense amplifier, IB1 to IBn + 1 ... I / O bus selection circuit,
B1 to Bn + 1 ... I / O bus lines, AP1 to APn ... Address program circuit, C1 to Cn + 1 ... I / O control circuit I / O1
~ I / On + 1 ... I / O terminal.

Claims (1)

(57) [Claims] A plurality of input / output terminals each having a plurality of memory cell arrays divided corresponding to a plurality of input / output terminals and connecting a sense amplifier of each memory cell array to an input / output control circuit of each input / output terminal; In a semiconductor memory device having a bus line, a redundant bus line connectable to all sense amplifiers respectively associated with the plurality of memory cells in the plurality of memory cell arrays; An input / output bus selecting means for selectively connecting the sense amplifier of the first memory cell array selected to the redundant bus line; and a program address for accessing a second memory cell array of the plurality of memory cell arrays. Connecting the redundant bus line to an input / output control circuit of an input / output terminal corresponding to the second memory cell array. To and an address program circuit, the second to be accessed by the program address
A semiconductor memory device wherein the first memory cell array is accessed in place of the memory cell array.