JP2905883B2 - ATM-STM converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for a communication device accommodated in an ATM (Asynchronous Transmit Mode) network that performs data transmission using asynchronous fixed-length packets.

In particular, the present invention relates to multiplexed asynchronous fixed-length packet data and synchronous continuous bit stream STM (Synchronous-ous T
(ransmit Mode) Used for an ATM-STM conversion device that converts data into and out.

[Conventional technology]

Currently, the CCITT (International Telegraph and Telephone Consultative Committee) is working on the standardization of a broadband service integrated digital communication network (B-ISDN). In B-ISDN, information is converted into cells consisting of short packets of a fixed length and the AT
M transmitted. Even in the communication using the ATM network, the conventional circuit-switched (STM) type communication is important in terms of using existing facilities and components. For example, when connecting an existing narrowband ISDN (hereinafter referred to as N-ISDN) (for example, NTT (Nippon Telegraph and Telephone Corporation) ISN net 64 and 1500 services) terminals to an ATM network, or using an existing voice codec In the case of using, for example, it is necessary to convert a cell into STM data.

In ATM, the arrival intervals of cells are not constant, and fluctuations occur. Therefore, when converting to STM, it is necessary to absorb and reproduce this fluctuation.

On the other hand, in N-ISDN, the basic interface (2B + D; B = 6
4Kbps, D = 16Kbps, Primary group interface (23B + D;
Channels are multiplexed on one interface line as in B and D = 64 Kps. Further, in the primary group interface, 2B (128 Kbps), 6B (384 Kbps) and 23B (1.544
Mbps).

Therefore, in a terminal device or a gateway device for converting an ATM network interface to an N-ISDN interface, it is necessary to perform both fluctuation absorption and multiplexing.

As for fluctuation absorption, a method of reproducing data with a fluctuation fluctuation buffer according to the communication speed of STM is general.

FIG. 12 is a block diagram showing the outline of such an ATM-STM converter, in which the STM side is an N-ISDN circuit.

The ATM data or cells from the ATM network 28 are temporarily stored in the fluctuation absorbing circuit 21 for each channel in accordance with the STM data handled by the N-ISDN circuit 29,
The data is multiplexed at 22 and the parallel data is converted to series data at the PS conversion circuit 23 and sent to the N-ISDN circuit 29 as predetermined STM data.

On the other hand, the STM data from the N-ISDN circuit 29 converts the series data into parallel data by the SP conversion circuit 23, is separated into cells by the separation circuit 25, and
, A predetermined cell is generated and transmitted to the ATM network 28. The control circuit 27 performs the above control.

[Problems to be solved by the invention]

As described above, ATM-ST for converting ATM to N-ISDN
Considering that the M conversion device uses a different band for each communication like the primary interface of the N-ISDN and performs simultaneous communication of a plurality of channels, for example, in the case of the primary interface of 23B + D, as shown in FIG. And a fluctuation absorbing circuit 21 for each of 23 channels (B) to B23.
Is required, and each fluctuation absorbing circuit 21 has a fluctuation absorbing buffer of the maximum band (23B), which requires a large amount of memory.

For example, in the case of FIG. 12, the memory capacity of each fluctuation absorbing circuit 21 is 47 bytes × 23 channels × 2 (for fluctuation absorption) = 2162 bytes, and the entire apparatus has a huge amount of 2162 × 23 = 49726 bytes. Capacity is required.

For this reason, there is a problem that it is difficult to realize an ATM-STM conversion device at low cost.

An object of the present invention is to solve the above problems,
ATM with low buffer requirements and low price
-To provide an STM converter.

[Means for solving the problem]

The present invention provides a means for interconnecting an ATM transmission line for performing information transfer using cells in an asynchronous fixed short packet format and an STM transmission line for performing information transfer by multiplexing a plurality of channels at periodic time positions. In the provided ATM-STM conversion device, a physical interface circuit for performing synchronization control of the ATM transmission line and transmitting and receiving signals, a cell transmission and reception circuit for transmitting and receiving cells of the ATM transmission line, and a cell received from the ATM transmission line. A reception buffer memory for temporarily storing data in a reception area divided into cell data units, and a synchronous bit string in which a plurality of channels are multiplexed at periodic time positions.
An STM data generation circuit for generating STM data, an STM interface circuit for transmitting and receiving STM data of the STM transmission line and generating a basic clock synchronized with a synchronization signal of the STM transmission line, and a cell received by the cell transmission / reception circuit. And a continuous bit stream regeneration circuit for periodically reading data from the reception buffer memory by the basic clock and transferring the data to the STM data generation circuit, wherein the continuous bit stream regeneration circuit comprises:
The reception area is allocated to a plurality of reception areas satisfying a cell length twice as long as the maximum cell delay time of the ATM transmission line for each channel in accordance with the speed used for each channel of the STM data generated by the STM data generation circuit. And means for starting reading of data from the reception buffer memory after receiving the next cell of half of the allocated reception area and performing alternate writing and reading.

[Action]

The continuous bit stream reproduction circuit determines the usage amount and area of the reception buffer memory corresponding to the channel in accordance with the speed used in each channel of each STM data generated by the STM data generation circuit. For example, if the STM data is 23B,
47 bytes x 23 channels x reception buffer memory
2. One conventional fluctuation absorbing circuit shown in FIG.
The first cell of the input ATM data is written first, then the second cell is written to the remaining area, and at the same time, the first cell is sequentially read from the first bit and sent to the STM data generation circuit. Output. Then, the third cell is written after the first cell is read. By repeating this operation sequentially, the ATM data
Can be converted to TM data.

Therefore, in this case, the capacity of the receiving buffer memory is 1/23 that of the conventional example, and the memory capacity as a fluctuation absorbing circuit can be greatly reduced, realizing an ATM-STM conversion device at low cost. It is possible to do.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
The case where conversion between an ATM network and an N-ISDN primary rate interface is performed will be described.

In this embodiment, a physical interface circuit 1 for performing synchronization control and signal transmission / reception with the ATM network 12 and a header addition confirmation circuit 2 as a cell transmission / reception circuit for providing a header of a transmission cell and confirming a header of a reception cell The N-ISDN interface circuit 9 writes the received cells into a reception buffer memory 3 for temporarily storing received cells and a reception buffer memory adapted to the channel speed on the N-ISDN side.
A cell assembling / regenerating circuit 4 as a continuous bit stream reproducing circuit for reading out the contents of the receiving buffer memory 3 in accordance with the synchronous clock from
A cell conversion circuit 5 for reading the information signal from the P conversion circuit 8 for each channel, writing the information signal to the transmission buffer memory 6 and sending the information to the header addition confirmation circuit 2 when the information has accumulated for the length of the cell; A transmission buffer memory 6 for temporarily storing the data and a byte data parallel data from the cell assembling / reproducing circuit 4 are multiplexed, converted into bit-serial data, and sent to the N-ISDN interface circuit 9 as an STM data generation circuit. A multiplexing PS conversion circuit 7; an SP conversion circuit 8 which converts bit-wise serial data from the N-ISDN interface circuit 9 into parallel data in byte units and sends it to the cell-forming circuit 5;
N-ISDN with layer 1 function of primary interface
An N-ISDN interface circuit 9 as an STM interface circuit connected to the terminal 13 for multiplexing or demultiplexing the information signal and the call control signal, and for generating a basic clock synchronized with the synchronization signal of the STM transmission line; From the N-ISDN terminal 13 through the ISDN interface circuit 9 or from the N-
Analysis and assembly of the call control signal to the ISDN terminal 13, and from the ATM network 12 or the AT
Analyzes and assembles the call control signal to the network 12, and performs N-ISDN
A channel used by the N-ISDN terminal 13 is determined by a call control signal received from the terminal 13, and a cell header number for distinguishing a communication path is set in the header assignment confirmation circuit 2 by a call control signal received from the ATM network 12, A control circuit 10 for setting the division of the reception buffer memory 3 used for each channel to the cell assembly and reproduction circuit in accordance with the communication speed of the channel required by the N-ISDN terminal 13, and a necessary power supply for each circuit of the present apparatus. And a power supply circuit 11.

The feature of the present invention is that, in FIG. 1, a physical interface circuit 1, a header assignment confirmation circuit 2 as a cell transmission / reception circuit, a reception buffer memory 3, a cell assembling / reproduction circuit 4 as a continuous bit stream reproduction circuit, and STM data A multiplexed PS conversion circuit 7 as a generation circuit and an N-ISDN interface circuit 9 as an STM interface circuit are provided.
The cell assembling / reproducing circuit 4 includes means for determining the usage amount and area of the reception buffer memory 3 corresponding to the channel in accordance with the speed used for each channel of the STM data generated by the multiplexing PS conversion circuit 7. is there.

Next, the operation of the present embodiment will be described including the configurations of the reception buffer memory 3 and the transmission buffer memory 6.

 First, signal formats between main circuits will be described.

First, the N-ISDN interface circuit 9-multiplexed PS
As shown in FIG. 2, the signal a between the conversion circuits 7 and the signal b between the N-ISDN interface circuit 9 and the SP conversion circuit 8 exclude the D-channel signal from the N-ISDN primary group (23B + D). This is a signal of a bit string, and has a configuration of 23 channels of 64 Kbps. This bit string is synchronized with the synchronization clock from the N-ISDN interface circuit 9 and corresponds to N-ISDN channels B1 to B23 every eight bits. Each of the B1-B23 channels is not only an information signal of 64 Kbps alone, but also 128 Kbps or 6
It is possible to obtain a speed of 384 Kbps by combining them. The method of using the B channel is determined by a call control signal transmitted through the D channel.

Next, the multiplexed PS conversion circuit 7 and the cell assembly and reproduction circuit 4
The signal c between them and the signal d between the SP conversion circuit 8 and the celling circuit 5 have a byte-by-byte structure obtained by serial-parallel conversion of the bit string signal shown in FIG. 2 as shown in FIG. .

Next, a signal e between the cell assembling / reproducing circuit 4 and the header addition confirmation circuit 2 and the celling circuit 5 and the header addition confirmation circuit 2
As shown in FIG. 4, the signal f between the channels is a channel indicating which communication channel of the N-ISDN corresponds to the communication channel of N-ISDN (for communication using a plurality of channels, for example, the first B channel number). It is composed of a number, a sequence number indicating the order of cells, and 47 bytes of information. The channel number is used by the header assignment confirmation circuit 2 to assign a VPI and VCI number for distinguishing the communication path in the ATM network 12, and the N-IS
Used to identify the channel on the DN side. The sequence number is used to check if the cells were delivered in order. Information is cellized every 47 bytes according to CCITT recommendations. The correspondence between the channel number and the VPI and VCI numbers is notified to the header assignment confirmation circuit 2 by an instruction from the control circuit 10 at the time of call setting.

Next, as shown in FIG. 5, the signal g between the header assignment confirmation circuit 2 and the physical interface circuit 1 is obtained by converting the channel number of FIG.
The configuration is changed to an M cell header. This structure is described in the CCITT recommendation.

 Next, the configuration of the transmission buffer memory 6 will be described.

As shown in FIG. 6 (a), the transmission buffer memory 6 is divided into 47 bytes (hereinafter referred to as a transmission area), which is a cell unit of the information part, for each channel of the N-ISDN primary rate interface. (The value of 47 bytes is standardized by CCITT). This is NI
This is for application when the SDN terminal 13 performs simultaneous communication using 23 channels.

The transmission information is, for example, in the case of performing 64 Kbps communication using one B1 channel with respect to the transmission area, FIG.
Is written by the celling circuit 5 and sent to the header addition confirming circuit 2 when 47 bytes are completed. Also B2
FIG. 6 (c) shows a case where 128 Kbps communication is performed using two B3 channels.

 Next, the configuration of the reception buffer memory 3 will be described.

As shown in FIG. 7 (a), the reception buffer memory 3 is divided into an area for a plurality of cells (47 bytes) (hereinafter referred to as a reception area) for each channel of the N-ISDN primary rate interface. . The number of reception areas is ATM
It is determined by the maximum value of the fluctuation range of the net 12. Here, assuming that the maximum fluctuation value in the ATM network 12 is 5 mS, 64 Kb
Since it is equivalent to 40 bytes in ps conversion, it is sufficient to have two reception areas.

For example, when 64 Kbps communication is performed with respect to the reception area using one B1 channel, the cell is assembled into two reception areas B1 corresponding to the B1 channel as shown in FIG. 7 (b). The data is written by the reproducing circuit 4 and sequentially sent to the multiplexed PS converter 7 in accordance with the channel synchronization. In the case of performing 128 Kbps communication using two B2 and B3 channels, the data is written to the reception areas B2 and B3 as shown in FIG. 7 (c).

In the first reproduction of the cell, reproduction is started after receiving a half + 1st cell of the allocated reception area in consideration of fluctuation (delay) of the arrival time of the cell. This means that if playback is started immediately after receiving the first cell, playback for one cell will be completed before the next cell arrives, causing a loss of information to be sent to the N-ISDN side. This is to prevent it.

 Next, the overall operation will be described.

(1) First, one B1 channel was used from the N-ISDN side.
The case where 64 Kbps communication is required will be described.

FIG. 8 is a sequence example of a call control signal from the idle state to the communication state.

When the call setup request signal (N) is transmitted from the N-ISDN terminal 13 from the idle state, the call setup request signal (N) becomes N-IS
It is received by the control circuit 10 via the DN interface circuit 9. The call setting request signal (N) includes communication speed information (here, 64 Kbps) together with address information of the connection destination. Since the B1 channel on the N-ISDN side is vacant, the control circuit 10 sends a call setting acceptance signal (N) including the "B1 channel" as a channel to be used to the N-ISDN terminal 13 via the N-ISDN interface circuit 9. . In addition, the control circuit 10
A call setting request signal (A) is sent to the network 12 via the header assignment confirmation circuit 2 and the physical interface circuit 1.
The call setting request signal (A) includes information of 64 Kbps as the communication speed and circuit switching information and address information as the quality. Upon receiving the call setup request signal (A), the ATM network 12 performs connection processing to the other party and also sets the VPI and VCI values (normally assigned individually for uplink and downlink) used to distinguish the information path to the partner. The call setting acceptance signal (A) including the call is sent to the ATM-N-ISDN converter of this embodiment. The call setting acceptance signal (A) is received by the control circuit 10 via the physical interface circuit 1 and the header assignment confirmation circuit 2.

The control circuit 10 analyzes the call setting acceptance signal (A) and notifies the header assignment confirmation circuit 2 of the VPI and VCI (up and down) values to be used and the channel number of the N-ISDN terminal 13. Thereby, when receiving the transmission information from the celling circuit 5, the header assignment confirmation circuit 2 sets the VPI and VCI (upper) corresponding to the channel number to AT.
If the ATM header of the received cell matches the notified VPI and VCI (lower), a channel number is assigned to the received cell and the cell is sent to the cell assembling / reproducing circuit 4.

Further, the control circuit 10 notifies the channel and the speed (here, 64 Kbps in the B1 channel) used for the cell assembling / reproducing circuit 4 and the cellizing circuit 5. Thereby, the cell assembling / reproducing circuit 4 secures two areas for B1 as reception areas of the reception buffer memory 3. The celling circuit 5 secures one area for B1 as a transmission area of the transmission buffer memory 6.

Thereafter, when the other party responds, the response signal (A) is transmitted from the ATM network 12 and received by the control circuit 10. Control circuit 10
Transmits a response signal (N) to the N-ISDN terminal 13 and instructs the cell assembling / reproducing circuit 4 and the cellizing circuit 5 to start operation. In this state, the N-ISDN terminal 13 enters a communication state.

(2) Next, a method of transmitting and receiving information in a communication state will be described.

The transmission information (B1 channel) from the N-ISDN terminal 13 is received by the celling circuit 5 via the N-ISDN interface circuit 9 and the SP conversion circuit 8 one byte per frame. The celling circuit 5 writes the received information one by one into the transmission area B1 of the transmission buffer memory 6 from the beginning. The celling circuit 5 repeats this operation and repeats the transmission area B1.
When the 47th byte is written, a channel number and a sequence number are added and sent to the header assignment confirmation circuit 2 as a transmission cell. The header assignment confirmation circuit 2 receives this transmission cell, attaches the VPI and VCI values (upper) assigned from the channel number, and sends the same to the physical interface circuit 1. Furthermore, the transmission cell is
It is delivered to the other party via the ATM network 12.

Information received from the ATM network 12 is received by the header assignment confirmation circuit 2 via the physical interface circuit 1 for each cell, and the header assignment confirmation circuit 2 determines the VPI and VCI of the ATM header.
A channel number is assigned from (below) and sent to the cell assembly / reproduction circuit 4. The cell assembling / reproducing circuit 4 writes the received cell into the receiving area B1-1 of the receiving buffer memory 3. Upon receiving the next cell, the cell assembling / reproducing circuit 4 receives the next cell.
At the same time as writing to B1-2, one byte is read from the head of the reception area B1-1 and sent to the B1 channel of the multiplexing PS converter 7 in synchronization with the channel synchronization signal. The transmitted one byte is converted into a serial bit string by the multiplexing PS conversion circuit 7 and sent to the N-ISDN terminal 13 through the N-ISDN interface circuit 9. Since the third cell arrives after at least the entire contents of the reception area B1-1 have been reproduced, it is written into the reception area B1-1.

By repeating the above operation, the information signal of the asynchronous ATM can be converted into the synchronous signal of the STM, or vice versa.

(3) Next, an operation when a communication request of 128 Kbps using two channels simultaneously from the N-ISDN terminal is performed will be described.

The procedure from the call setting request from the N-ISDN terminal 13 to the reception of the call setting of the ATM network 12 is the same as that described in the above (1). Here, since the communication is performed at 128 Kbps, the control circuit 10 controls the N-ISD
It is assumed that the N terminal 13 is instructed to use the B2 and B3 channels simultaneously.

After receiving the call setting acceptance signal (A), the control circuit 10 sends the VPI and VCI (up / down) values to be used and the channel numbers (here, B2 and B3) of the N-ISDN terminal 13 to the header addition confirmation circuit 2. Notify. Thus, when receiving the transmission information from the celling circuit 5, the header assignment confirmation circuit 2 sets the VPI and VCI (upper) corresponding to the channel number in the ATM header, and conversely, the ATM header of the received cell is Notified VPI, VCI (lower)
If they match, a channel number is assigned and sent to the cell assembly and reproduction circuit 4.

Further, the control circuit 10 controls channels and speeds (here, B2, B3
128Kbps on the channel. Thereby, the cell assembling / reproducing circuit 4 serves as a receiving area of the receiving buffer memory 3.
Secure four areas for B2 and B3. In addition, cell conversion circuit 5
Secures one area for B2 as a transmission area of the transmission buffer memory 6. Here, the transmission area may be one area because the transmission side only needs to transmit to the ATM network when 47 bytes are completed.

Thereafter, when the other party responds, the response signal (A) is transmitted from the ATM network 12 and received by the control circuit 10. Control circuit 10
Transmits a response signal (N) to the N-ISDN terminal 13 and instructs the cell assembling / reproducing circuit 4 and the cellizing circuit 5 to start operation. In this state, the N-ISDN terminal 13 enters a communication state.

(4) Next, a method of transmitting and receiving information in a communication state will be described.

Transmission information (B2, B3 channels) from the N-ISDN terminal 13 is received by the celling circuit 5 via the N-ISDN interface circuit 9 and the SP conversion circuit 8 two bytes per frame. The celling circuit 5 writes the received information into the transmission area B2 of the transmission buffer memory 6 one by one in the order of B2 and B3, respectively. When the celling circuit 5 repeats this operation and writes the 47th byte of the transmission area B2, it assigns a channel number and a sequence number and sends it to the header assignment confirmation circuit 2 as a transmission cell. The header assignment confirmation circuit 2 receives the transmission cell, and assigns VPI and VCI to be assigned based on the channel number.
The value is sent to the physical interface circuit 1 with a value (upper ').
Further, the transmission cell is delivered to the other party via the ATM network 12.

Information received from the ATM network 12 is received by the header assignment confirmation circuit 2 via the physical interface circuit 1 for each cell, and the header assignment confirmation circuit 2 determines the VPI and VCI of the ATM header.
The channel number is assigned from (lower) and sent to the cell assembling / reproducing circuit 4. The cell assembling / reproducing circuit 4 writes the received cell into the receiving area B2-1 of the receiving buffer memory 3.
Upon receiving the second cell, the cell assembling / reproducing circuit 4 writes the cell into the receiving area B2-2. The cell assembling / reproducing circuit 4 receives the third cell, writes it in the receiving area B3-1, and simultaneously reads out two bytes from the head of the receiving area B2-1, and synchronizes with the channel synchronization signal to multiplex the PS conversion circuit. 7 of
Send to B2 and B3 channels. The transmitted 2 bytes are converted into a serial bit string by the multiplexing PS conversion circuit 7,
-Sent to the N-ISDN terminal 13 through the ISDN interface circuit 9; Since the fourth cell is written in the receiving area B3-2 and arrives from the fifth cell after at least the entire contents of the receiving area B2-1 are reproduced,
It is written to the receiving area B2-1. This reception area and N
FIG. 9 shows the correspondence relationship between the ISDN channels.

By repeating the above operation, an asynchronous ATM information signal can be converted into an STM synchronous signal, or vice versa.

384Kbps using 6 channels in addition to the above description
Communication can be realized by securing the reception buffer memory 3 as shown in FIG. 10, and an arbitrary speed (a speed of 64 Kbps) is also possible.

As described above, according to the present embodiment, the fluctuation absorbing circuit 21 (the receiving buffer memory 3 in the present embodiment) shown in the configuration of the conventional example shown in FIG. In this case, as shown in FIG. 11, only one is required, and the required memory capacity is 47 bytes × 23 channels × 2 = 2162 bytes, which is 1/23 of the conventional example.

In the present embodiment, the unit of cellization has been described as 47 bytes. However, other cellization units can be applied by changing the buffer configuration. In addition, although the N-ISDN primary group interface has been described as an example of the interface on the terminal side, it is easy to analogize that even if there is a digital leased line for performing similar multiplexing, provision of a multiplexing circuit corresponding to the terminal will make it easier to analogize. it can. Furthermore, although a continuous channel has been described as an example at a speed other than 64 Kbps, the present invention can be easily realized even in a discontinuous case by continuously using the corresponding channel number in the reception area.

Although the present embodiment has been described with reference to a conversion device between ATM and N-ISDN, the present invention is similarly applied to a gateway device that performs ATM and STM conversion, and a relay device that performs STM multiplexing transmission in a network. Can be.

〔The invention's effect〕

As described above, according to the present invention, the use amount and area of the reception buffer memory corresponding to the channel are determined in accordance with the speed used in each of the plurality of channels or each channel of the channel multiplexed STM data. This can be realized as long as the STM has the amount corresponding to the maximum speed, the buffer can be configured with a minimum necessary amount, and there is an effect that the price of the apparatus can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an ATM-N-ISDN converter according to one embodiment of the present invention. FIG. 2 shows the N-ISDN interface circuit 9-multiplexed P
Between the -S conversion circuit 7 and the N-ISDN interface circuit 9
FIG. 4 is an explanatory diagram showing a signal format between -SP conversion circuits 8; FIG. 3 is an explanatory diagram showing signal formats between the multiplexed PS conversion circuit 7 and the cell assembling / reproduction circuit 4 and between the SP conversion circuit 8 and the cell conversion circuit 5. FIG. 4 is an explanatory diagram showing signal formats between the cell assembly / reproduction circuit 4 and the header addition confirmation circuit 2 and between the cell circuit 5 and the header addition confirmation circuit 2. FIG. 5 is an explanatory diagram showing a signal format between the header addition confirmation circuit 2 and the physical interface circuit 1. 6 (a) to 6 (c) are explanatory diagrams showing the configuration of the transmission buffer memory 6. FIG. 7 (a) to 7 (c) are explanatory diagrams showing a configuration example (1) of the reception buffer memory 3. FIG. FIG. 8 is an explanatory diagram showing an example of the call setting sequence. FIG. 9 is an explanatory diagram showing the correspondence between the reception area information and the information on the N-ISDN interface. FIG. 10 is an explanatory diagram showing a configuration example (2) of the reception buffer memory 3. FIG. 11 is an explanatory diagram of a fluctuation absorbing circuit in the present embodiment. FIG. 12 is a block diagram showing an outline of a conventional example. FIG. 13 is an explanatory diagram of a fluctuation absorbing circuit in a conventional example. 1 ... Physical interface circuit, 2 ... Header assignment confirmation circuit, 3 ... Reception buffer memory, 4 ... Cell assembly / reproduction circuit, 5 ... Cellularization circuit, 6 ... Transmission buffer memory,
7: multiplexed PS conversion circuit, 8, 24 ... SP conversion circuit, 9: N-ISDN interface circuit, 10, 27 ... control circuit, 11 ... power supply circuit, 12, 28 ... ATM network, 13 ... N
-ISDN terminal, 21 ... fluctuation fluctuation circuit, 22 ... multiplexing circuit, 23 ... PS conversion circuit, 25 ... separation circuit, 26 ... segment circuit, 29 ... N-ISDN circuit, a to g ……signal.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-266946 (JP, A) JP-A-63-108832 (JP, A) JP-A-63-232544 (JP, A) JP-A-1- 198143 (JP, A) JP-A-2-234544 (JP, A) JP-A-3-106149 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 12/28

Claims (1)

(57) [Claims] A means for mutually connecting an ATM transmission line for transferring information using cells in an asynchronous fixed short packet format and an STM transmission line for multiplexing a plurality of channels at periodic time positions and transferring information. An ATM-STM converter comprising: a physical interface circuit (1) for controlling synchronization of the ATM transmission line and transmitting / receiving signals; a cell transmission / reception circuit (2) for transmitting / receiving cells on the ATM transmission line; A reception buffer memory (3) for temporarily storing cells received from the transmission line in a reception area divided into cell data units, and STM data of a synchronous bit string obtained by multiplexing a plurality of channels at periodic time positions. An STM data generation circuit (7) for generating, transmitting and receiving STM data of the STM transmission line, and
S that generates a basic clock synchronized with the synchronization signal of the M transmission line
A TM interface circuit (9), and writes cells received by the cell transmission / reception circuit to the reception buffer memory, and periodically reads data from the reception buffer memory according to the basic clock, the ST
A continuous bit stream regeneration circuit (4) for transferring to the M data generation circuit, wherein the continuous bit stream regeneration circuit is provided for each channel in accordance with the speed used in each channel of the STM data generated by the STM data generation circuit. The reception area is allocated with a plurality of reception areas satisfying a cell length twice as long as the maximum cell delay time of the ATM transmission line, and after receiving the next cell that is half of the allocated reception area, data from the reception buffer memory is received. An ATM-STM conversion device comprising means for starting reading of data and performing alternate writing and reading.