JP2905949B2 - Image display circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display circuit in, for example, a television.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional image display circuit, and FIG. 4 is a timing chart of signals of respective parts. This image display circuit is configured to display three rows of images on one screen. Position registers 1a, 1b,
In 1c, data indicating the vertical display start position of each row for displaying an image is written from the CPU 3 via the data bus 2.

The display position control circuit 4 uses the vertical synchronization signal V
_SYC is reset each time is input, thereby counting the horizontal synchronizing signal H _SYC shown in FIG. 4 (a) that is input to the counter. When the count value matches the data stored in the position register 1a, the display position control circuit 4
Supplies a signal for activating the character generator 5 to the character generator 5 and simultaneously supplies a display start signal S _S to the horizontal synchronization signal counter 6.

Then, the horizontal synchronizing signal counter 6 starts counting the horizontal synchronizing signal H _SYC . On the other hand, the activated character generator 5 synchronizes with the clock supplied from the oscillation circuit 7 to display the first line of the first line image stored in the image display memory (not shown). The character font data of the horizontal scanning line is serially output to color signal terminals 8, 8, 8 provided for each color.

When the next horizontal synchronizing signal H _SYC is input to the display position control circuit 4, the character generator 5 colorizes the character font data of the second horizontal scanning line for displaying the image on the first line. The signals are serially output to the signal terminals 8, 8, 8. And during the period until the count value of the horizontal synchronizing signal counter 6 overflows, for example until the character font data in the fourth horizontal scanning lines for displaying an image of one line is output, shown in FIG. 4 (c) As described above, the character font data of each horizontal scanning line is sequentially output.

The horizontal synchronizing signal counter 6 overflows when it counts the number of horizontal scanning lines for displaying one row of images, that is, the number of horizontal synchronizing signals H _{SYC allocated} for displaying one row of images. I have. Therefore, Fig. 4 (b)
As shown in FIG. 7, when seven pulses of the horizontal synchronizing signal _HSYC are counted, image display of one line is completed. If overflow interrupt signal S _A is generated as shown in FIG. 4 (d), it gives it to the CPU 3.

Then, the display position control circuit 4 again operates
When the count value obtained by counting the horizontal synchronization signal matches the data in the position register 1b, the character generator 5 is activated again, and the same operation as that for displaying the image on the first line is performed. Is displayed, and an interrupt signal S _A is given to the CPU 3 when the image display is completed.

Thereafter, when the count value obtained by counting the horizontal synchronizing signal by the display position control circuit 4 matches the data of the position register 1c, the character generator 5 is activated, and the third line is operated by the same operation as described above. Is completed, and an interrupt signal S _A is given to the CPU 3. Thus, each time the interrupt signal S _A is given to the CPU 3, the operation for displaying the image of the next row or another image processing is started.

[0009]

As described above, in the conventional image display circuit, no interrupt signal is given to the CPU until the count value of the horizontal synchronizing signal counter overflows. In other words, the next image processing cannot be started until the number of horizontal synchronizing signals allocated for displaying the image of one line has been counted.

[0010] Thus, as shown in FIG. 4 (b), until you count the number of horizontal synchronizing signals allocated for the image display of one line, character font data as shown in FIG. 4 (c) When the output of the character font data is completed, from the time when the output of the character font data is completed to the time when the image display of one line is completed, the waiting time T during which the next image processing cannot be started.
And the efficiency of image processing is low.

In view of such a problem, the present invention provides an interrupt signal when the output of character font data is completed,
It is an object of the present invention to provide an image display circuit capable of executing the following image processing.

[0012]

In the image display circuit according to the present invention, the type and display position of the character font are controlled by the CPU.
Characters on the horizontal scanning lines according to the horizontal synchronization signal.
Output the data and count the horizontal sync signal.
When the count value of the flat sync signal counter reaches a predetermined value,
Image where one line of image display by character font data is completed
In the image display circuit, the output of the character font data is terminated.
Register for storing data indicating the end position, and the register
Stored data and count of the horizontal synchronization signal counter
And a comparison circuit for comparing data.
The counter value matches the data stored in the register.
Should start the next processing for displaying images.
While the image of the one line is being displayed, an interrupt signal is sent to the CPU.
It is configured to output.

[0013]

In the register, data of the output end position of the character font data is stored. The horizontal synchronization signal is counted by the horizontal synchronization signal counter, and when the data stored in the register matches the count value of the horizontal synchronization signal counter, an interrupt signal is output from the comparison circuit to the CPU . This allows horizontal
Output of character font data is not performed even during scanning of scanning lines.
At the time of completion, an interrupt signal is input to the CPU ,
It is possible to start the next image processing.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments. FIG. 1 is a block diagram showing a configuration of an image display circuit according to the present invention, and FIG. 2 is a timing chart of signals of respective parts. This image display circuit is configured to display three rows of images on one screen.

In the position registers 1a, 1b, and 1c, data indicating the vertical start position of each row for displaying an image is written from the CPU 3 via the data bar 2. Interrupt position control register 10
Data indicating the output end position of the character font data according to the horizontal synchronizing signal H _SYC is stored in the data bus 2 on a, 10b, and 10c.
Is written from the CPU 3 via the.

The display position control circuit 4 uses the vertical synchronization signal V
Reset every time _SYC is input and input Figure 2
The horizontal synchronization signal _HSYC shown in FIG. When the count value matches the data stored in the position register 1a, the display position control circuit 4 displays the character
A signal for activating the generator 5 is supplied to the character generator 5, and at the same time, a display start signal SS is _supplied to the horizontal synchronizing signal counter 6.

Then, the horizontal synchronizing signal counter 6 starts counting the horizontal synchronizing signal _HSYC . On the other hand, the activated character generator 5 synchronizes with the clock supplied from the oscillation circuit 7 to display the first horizontal image stored in the image display memory (not shown). The character font data of the scanning line is serially output to color signal terminals 8, 8, 8 provided for each color.

When the next horizontal synchronizing signal H _SYC is input to the display position control circuit 4, the character generator 5 converts the character font data of the second horizontal scanning line for displaying the image on the first line. It is serially output to the color signal terminals 8, 8, 8. In this manner, the next horizontal synchronizing signal, that is, the character font data of the horizontal scanning line is sequentially output.

On the other hand, the horizontal synchronizing signal counter 6 counts the horizontal synchronizing signal H _SYC and updates the count value.
Here, the interrupt position control register 10a, for example, FIG. 2 (c)
If the data of four pulses of the horizontal synchronizing signal H _SYC indicating the output end position of the character font data is stored as shown in (4), the count value of the horizontal synchronizing signal counter 6 becomes "4".
2 , when the data matches the data stored in the interrupt position control register 10 a, the comparator 11 outputs an interrupt signal S _A as shown in FIG.

Therefore, as shown in FIG. 2 (b), an interrupt signal S _A is obtained within a period until the counting of the number of horizontal synchronizing signals H _{SYC allocated} for displaying one row of images is completed. Image processing can be started. Therefore, until the counting of the number of horizontal synchronizing signals allocated for displaying the image of one line is completed, there is no waiting time that the interrupt signal S _A cannot be obtained even if the output of the character font data is completed.

Then, as described above, the interruption signal S _A
3, the display position control circuit 4 again counts the horizontal synchronizing signal, and the position register 1b
When the data matches, the character generator 5
Are activated again to display the second row image by the same operation as that for displaying the first row image. If the data indicating the output end position of the character font data for displaying the image of the second line is stored in the interrupt position control register 10b, the count value of the horizontal synchronization signal counter 6 matches the data of the interrupt position control register 10b. When the comparison circuit
From 11, an interrupt signal S _A is given to the CPU 3.

Then, the next image processing can be started without waiting until the counting of the number of horizontal synchronization signals allocated for displaying the image on the second line is completed. In this manner, when the image on the third line is displayed, the data stored in the interrupt position control register 10c and the horizontal synchronization signal counter are displayed in the same manner as when the images on the first and second lines are displayed. When the count value matches 6, the interrupt signal S _A is obtained, and the next image processing can be started as described above.

In this embodiment, the case where three lines of images are displayed on one screen has been described, but this is merely an example.
The present invention is not limited to displaying three lines of images.
Also, the period during which the character font data is output is set to the period of four pulses of the horizontal synchronization signal, but this is merely an example.
There is no limitation to this.

[0024]

As described above in detail, according to the present invention, an interrupt signal can be generated when the output of the character font data of the horizontal scanning line is completed. for that reason,
Without wait until counting all horizontal synchronizing signal number of allocated to display an image of one line, any horizontal scanning
During scanning line, an excellent effect that to the CPU can Rukoto to start subsequent image processing can increase the efficiency of image processing.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image display circuit according to the present invention .

FIG. 2 is a timing chart of signals of respective parts in FIG.

FIG. 3 is a block diagram illustrating a configuration of a conventional image display circuit.

FIG. 4 is a timing chart of signals of respective parts in FIG.

[Explanation of symbols]

1a, 1b, 1c position register 3 CPU 4 display position control circuit 5 character generator 6 horizontal synchronizing signal counter 8-color signal terminals 10a, 10b, 10c interrupt position control register 11 comparator circuit S _A interrupt signal

Claims (1)

(57) [Claims] 1. The type and display position of a character font are CP
U controlled by a horizontal scanning line according to a horizontal synchronizing signal.
The horizontal sync signal counter that outputs character font data and counts the horizontal sync signal reaches a predetermined value.
To the, in the image display complete <br/> Ryosuru image display circuit for one row by the character font data, a register for storing data indicating the output end of the character font data, storage data and the horizontal of the register A comparison circuit for comparing the count data of the synchronization signal counter is provided, and when the count value of the horizontal synchronization signal counter matches the data stored in the register, the next processing for image display is started.
Image display circuit, characterized in that the image displayed in the first line in order to, interrupts <br/> are constituted to so that to output signals only to the CPU.