JP2906148B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit such as a dynamic RAM, a static RAM, a microprocessor, or the like, which is configured by an NMOS, a PMOS, or a CMOS circuit.

(Prior Art) A conventional semiconductor integrated circuit of this type will be described with reference to a main part circuit diagram of FIG.

In FIG. 4A, the semiconductor integrated circuit includes a plurality of N-channel MOS transistors (hereinafter, referred to as NMOS) or a plurality of P-channel transistors (hereinafter, referred to as PMOS), each of which is surrounded by a dashed line. an NMOS circuit 1 and the PMOS circuit 2, an external power supply voltage V _CC to supply several V lower operating voltage than, the step-down circuit 4 connected to the power supply terminal 3, CMOS circuit formed by the NMOS and PMOS Ground terminal 6 connected to the low level side of
And a substrate bias generating circuit 7 for supplying a negative voltage to the semiconductor substrate. The output side of the negative voltage circuit 4 is connected to the high level side of the CMOS circuit via a PMOS 8.

FIG. 4 (b) is a circuit diagram showing the internal configuration of the above-mentioned substrate bias generation circuit 7. The substrate bias generation circuit has a ring oscillator 9 connected to the power supply terminal 3 and two serially connected ring oscillators 9. The intermediate between NMOSs 10 and 11 and the above link oscillator 9 are connected via an amplifier 12 and a capacitor 13, and
A smoothing capacitor with one end grounded to the source of NMOS11
And a charge pumping circuit connected to the p-type semiconductor substrate.

(Problems to be Solved by the Invention) However, the step-down circuit 4 and the substrate bias generating circuit 7 reduce the junction capacitance with the semiconductor substrate acting as a load of the NMOS circuit 1 and the PMOS circuit 2 and reduce the substrate bias effect coefficient. It is provided to reduce and prevent malfunction due to injection of electrons into the semiconductor substrate due to signal undershoot which is a particular problem in dynamic RAM and static RAM. The output resistance of the bias generation circuit 7 is extremely high from the time when the power supply voltage is applied until the operation is stabilized, and the reverse bias is not sufficiently applied to the semiconductor substrate. Therefore, the semiconductor substrate or the well is almost floating. There is a problem that latch-up is likely to occur in the state. There is also a problem that minority carriers generated in the smoothing circuit section in the circuit can also trigger latch-up.

Further, there is a problem that the current consumption of the ring oscillator 9 or the like for operating the substrate bias generation circuit 7 is too large in the dynamic RAM circuit which requires low power consumption.

Further, there is a problem that the dynamic RAM circuit in which the smoothing capacitor 14 required for the substrate bias generation circuit 7 requires a large area and the semiconductor chip area is limited is an obstacle to miniaturization.

The present invention solves the above-mentioned problem, and provides a semiconductor integrated circuit which does not require the use of a substrate bias generation circuit 7 including a charge pumping circuit.

(Means for Solving the Problems) In order to solve the above problems, the present invention relates to a first circuit formed on a semiconductor substrate for supplying a high-level voltage of logic of a CMOS circuit integrated on the semiconductor substrate. A step-down circuit, means for supplying a voltage of an n-type semiconductor substrate or an N-well from a power supply terminal, and a second step-down circuit formed on the semiconductor substrate for supplying a low-level voltage of the logic of the CMOS circuit. ,
There is provided a means for supplying a voltage of a p-type semiconductor substrate or a P-well from a ground terminal. It is preferable that the first step-down circuit and the second step-down circuit use a common power supply terminal and a common ground terminal as reference potentials.

(Operation) With the above configuration, the high-level voltage of the logic of the CMOS circuit integrated on the semiconductor substrate is supplied from the first step-down circuit formed on the semiconductor substrate, and The voltage is supplied from the second step-down circuit. Furthermore, CM
A voltage of an n-type semiconductor substrate on which a PMOS for an OS circuit is formed or an N-well is supplied from a power supply terminal, and a voltage of a p-type on which an NMOS is formed
By supplying the voltage of the semiconductor substrate or the P-well from the ground terminal, a potential difference occurs between the substrate and the source of the NMOS and the PMOS, which is equivalent to the application of the substrate bias, and the substrate bias generation circuit This means that the substrate bias is applied without using the above.

Also, the internal power supply line and the internal ground line to which the outputs of the first step-down circuit and the second step-down circuit are connected have received power fluctuation noise from one or both of the external power line and the external ground line. Sometimes, the fluctuations of the internal power supply line and the internal ground line are in phase, and even if the absolute value of each potential fluctuates, by suppressing the fluctuation of the relative potential difference between the two, the logic level of the high side and the low level of the logic level are reduced. , A logical margin can be secured.

(Embodiment) An embodiment according to the present invention will be described with reference to FIGS.

FIG. 1 is a circuit diagram showing a circuit configuration example for explaining a semiconductor integrated circuit according to the present invention. The difference from the conventional example shown in FIG. 4 is that a power supply terminal 3, an NMOS circuit 1 and a PMOS circuit 2 are provided. The point that the high-level side of the configured CMOS, that is, the source of the PMOS, is connected via the PMOS8 and the above-mentioned CMO
Three points: the low level side of S, that is, the drain of the NMOS is connected to the output side of the step-down circuit 4, and the point that the p-type semiconductor substrate or P-well of the NMOS is directly connected to the connection terminal 6. It is. The other components are the same as those of the conventional example, and the same components are denoted by the same reference numerals and description thereof will be omitted.

With the above configuration, the voltage amplitude of the MOS circuit is expressed by the following equation (1).

Amplitude voltage = power supply voltage V _CC −generated voltage V _{L of the} step-down circuit (1) On the other hand, the potential difference between the p-type substrate or P-well and the source side of the NMOS is applied to the NMOS as a substrate bias. The voltage is expressed by the following equation (2).

Substrate bias = ground voltage V _SS - voltage value of the generated voltage V _L of the step-down circuit (2) above (1) and (2), specifically, the power supply voltage V _CC is 5V, the step-down circuit 4 of the generated voltage V _L is 2V,
The applied voltage of the substrate bias is set to a value of -2V.

As described above, according to the circuit configuration example shown in FIG.
Even without using the substrate bias generation circuit, the problems of the latch-up, the power consumption, and the required area of the smoothing capacitor, which are the conventional problems, are solved.

FIG. 2 is a circuit diagram showing another example of a circuit configuration for explaining a semiconductor integrated circuit according to the present invention. The difference between the circuit configuration example of FIG. 2 and the circuit configuration example shown in FIG. generated voltage V _H of the step-down circuit 4, the high level side of the logic of the CMOS circuits, namely that it is connected to the source of the PMOS circuit 2, a low-level side, i.e., the NMOS circuit 1 source, the ground terminal 6 Is connected via NMOS5.

The other components are the same, and the same components are denoted by the same reference numerals and description thereof will be omitted.

With such a configuration, the p-type semiconductor substrate of NMOS or P
The well voltage is equal to the voltage V _SS of the ground terminal 6 and the PMOS
The voltage of the n-type semiconductor substrate or the N-well has the same potential as the voltage V _CC of the power supply terminal 3. That is, the amplitude voltage of the MOS circuit is expressed by the following equation (3).

Generated voltage V _H of the amplitude voltage = step-down circuit - voltage V _SS ... (3) of the ground terminal also, n-type semiconductor substrate or a inter-N- well, the potential difference between the PMOS source is applied as the substrate bias of the PMOS The voltage is expressed by the following equation (4).

Substrate bias = power supply voltage V _CC −generated voltage V _{H of the} step-down circuit (4) The voltage values of the above equations (3) and (4) are, specifically, a power supply voltage V _CC of 5 V and a step-down circuit 4 the generated voltage V _H is 3V, the voltage applied substrate bias is set to a value of + 2V.

As described above, according to the circuit configuration example shown in FIG.
A substrate bias can be applied to a PMOS formed on a semiconductor substrate or an N-well without the conventional substrate bias generation circuit 7.

Further, an embodiment of the present invention will be described with reference to FIG. 3 with reference to the circuit configuration examples of FIG. 1 and FIG. In the figure, this embodiment is different from the circuit configuration example of FIGS. 1 and 2, the two step-down circuits 4a and 4b provided, generated voltage V _H of the step-down circuit 4a is, in the above CMOS circuit The high level side, that is, the source of the PMOS circuit 2, and the generated voltage _VL of the step-down circuit 4b are connected to the low level side of the CMOS circuit, that is, NM.
The point is that it is supplied to the source of the OS circuit 1. The other components are the same, and the same components are denoted by the same reference numerals and description thereof will be omitted.

With this configuration, the voltage of the p-type semiconductor substrate or P- wells of NMOS causes voltage V _SS and the potential of the ground terminal 6, also, the voltage of the n-type semiconductor substrate or N- well of the PMOS power supply terminal 3 And the same potential as the voltage V _CC .

Therefore, the amplitude voltage of the MOS circuit is expressed by the following equation (5).

Generated voltage V _H of the amplitude voltage = step-down circuit 4a - generated voltage V _L ... (5) the substrate bias of the step-down circuit 4b is the NMOS formed in a p-type semiconductor substrate or P- on wells, wherein the (2) The voltage shown in the equation is also formed on the n-type semiconductor substrate or N-well
The voltage represented by the above equation (4) is applied to the PMOS, respectively.

As described above, according to the present embodiment, a substrate bias is applied to an NMOS and a PMOS even without the substrate bias generation circuit 7.

Further, since the step-down circuit 4a and the step-down circuit 4b are both connected to the common power supply terminal 3 and the ground terminal 6, fluctuations in the output voltages of both become in-phase with fluctuations in the power supply voltage V _CC or the ground voltage V _SS , Therefore, the relative value, that is, the difference between the generated voltage _VH of the step-down circuit 4a and the generated voltage _VL of the
_It is hardly affected by variations in _CC and ground voltage V _SS , the operation voltage of the transistor inside the integrated circuit is relatively constant, the operation is stable, and the first step-down circuit and the second
By setting the intermediate value of the output voltage of each of the step-down circuits to substantially match the intermediate value of the voltage of the power supply terminal and the ground terminal voltage, specifically, the first circuit configuration example and the second
As described in the description of the circuit configuration example in the figure, when the external power supply voltage is 5 V, the voltage generated from the first step-down circuit is set to 2 V, and the voltage generated from the second step-down circuit is 3 V. By setting, the threshold value which is the intermediate value of the internal logic level is set to 2.5 V, which matches the logic level threshold of 2.5 V of the circuit directly connected between the external power supply line 5 V and the external ground line 0 V By doing so, it is possible to connect both logic circuits having different logic amplitude voltages without using a large-scale level conversion circuit.

(Effects of the Invention) As described above, according to the present invention, the PMOS and N-type MOS transistors can be used without providing the substrate bias generation circuit inside the semiconductor integrated circuit.
Substrate bias can be applied between each substrate and source of MOS, and problems such as substrate floating, injecting minority carriers into the substrate, or increasing power consumption, causing latch-up due to the substrate bias generation circuit Can all be eliminated. Further, stable operation can be performed with respect to fluctuations in the external power supply voltage, and logic circuits having different logic amplitude circuits can be connected without using a large-scale level conversion circuit.

[Brief description of the drawings]

1 and 2 are circuit diagrams showing an example of a circuit configuration for explaining a semiconductor integrated circuit according to the present invention, FIG. 3 is a circuit diagram showing an embodiment of the semiconductor integrated circuit of the present invention, and FIG. ,
It is a circuit diagram of a conventional semiconductor integrated circuit. 1 ... NMOS circuit, 2 ... PMOS circuit, 3 ... Power supply terminal, 4,
4a, 4b: Step-down circuit, 5, 10, 11: N-channel MOS transistor (NMOS), 6: Ground terminal, 7: Substrate bias generation circuit, 8: P-channel MOS transistor (PMOS),
9: ring oscillator, 12: amplifier, 13: capacitor, 14: smoothing capacitor.

Claims (2)

(57) [Claims] 1. A first step-down circuit formed on a semiconductor substrate for supplying a logic high-level voltage of a CMOS circuit integrated on the semiconductor substrate, and a power supply for an n-type semiconductor substrate or an N-well voltage Means for supplying from a terminal; a second step-down circuit formed on the semiconductor substrate for supplying a low-level voltage of the logic of the CMOS circuit; and supply of a voltage of a p-type semiconductor substrate or a P-well from a ground terminal. A semiconductor integrated circuit, comprising: 2. The semiconductor integrated circuit according to claim 1, wherein the first step-down circuit and the second step-down circuit use a common power supply terminal and a common ground terminal as reference potentials.