JP2906263B2 - Phase locked loop - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an improvement in a pull-in range and a phase noise in a phase locked loop.

<Prior Art> FIG. 3 shows a conventional phase locked loop (Phase Locked Loop Ci).
FIG. 3 is a configuration block diagram illustrating an example of a rcuit (PLL circuit).
After the output of the voltage controlled oscillator 1 is frequency-divided by the frequency divider 2, the phase of the output of the reference signal generator 4 is compared in the phase detector 3. The DC component is extracted from the output of the phase detector 3 by the loop filter 5 and applied to the voltage controlled oscillator 1 to control the oscillation frequency. There are roughly two types of phase detectors 3, the first of which is Motorola MC
The second type uses a flip-flop represented by 4044, and the second type is a multiplication type using a mixer or an EXOR (exclusive OR) circuit.

<Problems to be Solved by the Invention> However, the former has a disadvantage that the frequency range drawn into the PLL is infinite and wide, but the phase noise is large. Further, the latter has a drawback that the phase noise to be drawn is narrow, while the phase noise is small.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to realize a phase-locked loop circuit with small phase noise while keeping the pull-in frequency range wide.

<Means for Solving the Problems> A first aspect of the present invention is to compare a frequency-divided signal obtained by dividing the output of a voltage controlled oscillator with a reference signal by a multiplication type phase detector, and to compare the output of the phase detector with a loop filter. The present invention relates to a phase-locked loop that feeds back to the voltage controlled oscillator through a first counter that counts a frequency-divided signal, a second counter that counts a reference signal, and the first and second counters. Second
And a comparison circuit for comparing outputs from each other excluding predetermined consecutive lower-order bits including at least the LSB of the count value of the counter, and adding or subtracting a voltage to or from a control input of the voltage-controlled oscillator corresponding to the output of the comparison circuit. With an output circuit,
The configuration is such that the pull-in operation is performed when the frequency difference between the reference signal and the frequency-divided signal exceeds the pull-in frequency range of the phase detector.

(2) A second aspect of the present invention is that a frequency-divided signal obtained by dividing the output of a voltage-controlled oscillator is compared with a reference signal by a multiplication type phase detector, and the output of the phase detector is passed through a loop filter to the voltage-controlled oscillator. It is characterized by a frequency divider that divides the reference signal by a predetermined frequency division ratio, and counts the frequency-divided signal and is reset by the output of the frequency divider. A comparison circuit for comparing the count value of the counter with a value obtained by adding and subtracting a predetermined value from the value corresponding to the MSB, and a voltage input to the control input of the voltage controlled oscillator corresponding to the output of the comparison circuit. And an output circuit for adding or subtracting the phase difference from the reference signal, and when the frequency difference between the reference signal and the frequency-divided signal exceeds the pull-in frequency range of the phase detector, the pull-in operation is performed.

<Operation> By comparing the count value of the frequency-divided signal and the reference signal using a comparison circuit having a dead band in the lower bit, an out-of-lock state can be detected and the oscillation frequency can be pulled back into the pull-in frequency range.

<Example> Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the phase locked loop circuit according to the present invention. The same parts as those in FIG. 3 are denoted by the same symbols, and the description is omitted. The frequency divider 2 and the reference signal generator 4 in FIG. 3 are omitted in FIG.

6 a second divider for dividing the frequency f _V of the divided signal from the frequency divider 2 at a division ratio M, 7 a first counter for counting the output of the frequency divider 6, the counter 8 The first that holds the output of 7
Is a latch circuit. 9 a third divider for dividing the frequency f _R of the reference signal by the frequency division ratio M, 10 second counter for counting the output of the frequency divider 9, 11 first holds the output of the counter 10 2 is a latch circuit. Reference numeral 12 _denotes a comparison circuit comprising a digital comparator for comparing outputs (Q _{1 to} Q _n ) of the counters 8 and 11 except for the LSB (Q ₀ ) of the count value,
13, 14 are a positive voltage source Vs + and a negative voltage source Vs−, respectively.
The constant current sources SW1 and SW2 have one ends connected to them, and the other ends of the constant current sources 13 and 14 are connected to one ends of the constant current sources 13 and 14, respectively.
A> B output, a switch driven by A <B output,
Reference numeral 15 denotes a current / voltage converter in which the other ends of the switches SW1 and SW2 are connected to the input, and the output voltage is added to the control input of the voltage controlled oscillator 1. 13 to 15, SW1 and SW2 constitute an output circuit for adding or subtracting a voltage to or from a control input of the voltage controlled oscillator 1 in accordance with the output of the comparison circuit 12. The frequency f ₀ is applied to the reset terminals of the counters 7 and 10 and the clock terminals of the latch circuits 8 and 11.
/ 2 clock signal is applied.

Next, the operation of the phase locked loop circuit having the above configuration will be described. Frequency f _V of the divided signal and the frequency f _R of the reference signals are respectively frequency f _V / M is divided by the respective frequency divider 6 and 9, f _R /
M. Counter 7 and 10, together with the rise of the frequency f _0/2 of the clock signal, the count-up applied to the terminals frequency f _V / M, f counts the start of _R / M signal, the clock signal falling with 1 / f of ₀ second count value f _V / Mf ₀ , f _R /
Mf ₀ is held in the latch circuits 8 and 11, respectively. Outputs of the latch circuits 8 and 11 excluding LSB (Least Significant Bit) are A inputs (A ₀ to A ₀ ) of the digital comparator 12, respectively.
A _n-1 ) and B input (B _{0 to} B _n-1 ), so that f _V / Mf ₀
When is f _R / Mf ₀ than 2 or greater, i.e. A> B becomes when _{f V / Mf 0> f R} / Mf 0 +1 ∴f V> f R + Mf 0, SW1 is ON, SW2 is turned off. f _V
When / Mf ₀ is smaller than f _R / Mf ₀ by 2 or more, that is, when f _V / Mf ₀ <f _R / Mf ₀ -1 ∴f _V <f _R −Mf ₀ , A <B, SW1 is turned off, and SW2 is turned off. Turns on. Also when _{f R / Mf 0 <f V} <f R + Mf 0 SW1, SW2 are both turned off. When SW1 is turned on, the oscillation frequency f _out of the voltage controlled oscillator 1 decreases, and the frequency f _V
(= F _out / N) decreases. When SW2 is turned on, the oscillation frequency f _out of the voltage controlled oscillator 1 increases, and the frequency f _V increases. When both SW1 and SW2 are off, the PLL operation is performed via the phase detector 3. Therefore, if Mf ₀ is set corresponding to the pull-in frequency range of the multiplication type phase detector 3, the pull-in operation is performed when the frequency difference between the reference signal and the frequency-divided signal exceeds the pull-in frequency range of the phase detector 3. It can be configured to do so.

According to the phase-locked loop having such a configuration, the pull-in frequency range can be greatly expanded as compared with that of the multiplication type phase detector.

Further, since the multiplication type phase detector is used, the phase noise is small.

Also, since the counter and digital comparator are used as the frequency detector, unlike the conventional one,
There is no need to insert a low-pass filter, and miniaturization and IC integration are easy.

In the above embodiment, the output of the counter excluding the LSB is compared by the digital comparator. However, in accordance with the pull-in frequency range, the outputs excluding an arbitrary number of lower-order bits including the LSB are removed. for example Q ₃ to Q _n) can be compared.

The frequency dividers 6 and 9 are used to reduce the frequencies f _V and f _R to the operating frequency of the counter, but may be omitted when the oscillation frequency is low or when a high-speed counter is used.

Further, the configuration of the output circuit is not limited to the above configuration, and any circuit configuration capable of adding or subtracting a voltage to or from the control input of the voltage controlled oscillator according to the output of the comparator can be employed.

FIG. 2 is a configuration block diagram showing a second embodiment of the phase locked loop circuit according to the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted. Unlike FIG. 1, a reference signal is used as a clock pulse. 16 is the frequency divider 9
A fourth divider that divides the output of the above by a ^dividing ratio of 2 ⁿ , 17 is a divider
This is a toggle flip-flop circuit with 16 outputs as inputs. The output of the flip-flop circuit 17 is input to the reset terminal of the counter 7 and the clock terminal of the latch circuit 8. Reference numeral 18 uses the AND circuits 161, 164, the OR circuit 162, and the NOR circuit 163 to constitute a comparison circuit for comparing the output of the latch circuit 8 with a set value described later.

Next, the operation of the phase locked loop circuit having the above configuration will be described. The toggle switch 17 switches the output between high and low each time an input pulse is input. Since the signal of the frequency f _V / M for input to the clock terminal of the counter 7 is counted in a period of 2 ⁿ · M / f _R, is the count value ^{_{f V / M × (2 n}} · M / f R) = 2 ⁿ f _V / f _R (1) The output of the latch circuit 8 is a counter 7
Is larger than 2 ⁿ corresponding to the MSB (Most Significant Bit) of, that is, larger than 2 ⁿ +1; therefore, 2 ⁿ f _V / f _R > 2 ⁿ +1 ∴f _V > fR ・ (2 ⁿ +1) / At ²ⁿ , SW1 is turned on and SW2 is turned off. When the output of the latch circuit 8 is smaller than 2 ⁿ by 2 or more, that is, smaller than 2 ⁿ −1, therefore, 2 ⁿ f _V / f _R <2 ⁿ -1 ∴f _V > f _R. (2 ⁿ −1) / At ²ⁿ , SW1 is off and SW2 is on. Also the ^{_{f R · (2 n -1)}} / 2 n <f V <f R · (2 n +1) / 2 n are SW1, SW2 are both turned off when the. In other words, the comparison circuit 18 determines whether the count value of the counter 7 is larger than a value obtained by adding “1” from the value corresponding to the MSB, smaller than a value obtained by subtracting “1” from the value corresponding to the MSB, or ,
It is determined whether the value is between a value obtained by adding “1” from the value corresponding to the MSB and a value obtained by subtracting “1” from the value corresponding to the MSB,
SW1 ON SW2 OFF, SW1 OFF SW2 ON, or
Turn off both SW1 and SW2.

Therefore, by operating the output circuit in the same manner as in FIG. 1, if f _R / ²ⁿ is made to correspond to the pull-in frequency range of the phase detector 3, the difference between the frequency of the reference signal and the frequency of the frequency-divided signal is multiplied. When the frequency exceeds the pull-in frequency range of the phase detector 3,
It can be configured to perform a retracting operation.

According to the phase locked loop circuit having such a configuration, in addition to the advantage of the configuration of FIG. 1, the advantage of not requiring the clock signal of frequency f _0.

In the above embodiment, the comparison circuit 18 is a counter 7
Is compared with the value shifted up or down by the maximum value indicated by the LSB (that is, 1) with respect to the dividing ratio 2n, but is not limited thereto, and includes at least the LSB corresponding to the pull-in frequency range. The maximum value indicated by predetermined consecutive lower bits (for example, 2
In the case of a bit, it can be compared with a value shifted up or down by 3).

<Effects of the Invention> As described above, according to the present invention, it is possible to realize a phase-locked loop with low phase noise with a simple circuit configuration while keeping the pull-in frequency range wide.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a phase locked loop according to the present invention, FIG. 2 is a block diagram showing a configuration of a second embodiment of a phase locked loop according to the present invention, and FIG. FIG. 9 is a configuration block diagram illustrating a conventional phase locked loop circuit. 1 ... voltage controlled oscillator, 3 ... phase detector, 5 ... loop filter, 7 ... first counter, 10 ... second counter, 12, 18 ... comparison circuit, 13, 14 ... fixed Current circuit, 15…
... current-voltage conversion circuit, 16 ... frequency divider, SW1, SW2 ... switches.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03L 7/113

Claims (2)

(57) [Claims] 1. A phase control circuit which compares a frequency-divided signal obtained by dividing an output of a voltage controlled oscillator with a reference signal by a multiplication type phase detector, and returns an output of the phase detector to the voltage controlled oscillator via a loop filter. In the synchronous circuit, a first counter that counts a frequency-divided signal, a second counter that counts a reference signal, and at least LS of count values of the first and second counters
A comparison circuit for comparing outputs except for predetermined consecutive lower bits including B, and an output circuit for adding or subtracting a voltage to or from a control input of a voltage controlled oscillator corresponding to the output of the comparison circuit; A phase synchronization circuit characterized in that a pull-in operation is performed when a frequency difference between a signal and a frequency-divided signal exceeds a pull-in frequency range of a phase detector. 2. The phase control circuit according to claim 1, wherein a frequency-divided signal obtained by dividing the output of the voltage-controlled oscillator is compared with a reference signal by a multiplication type phase detector, and the output of the phase detector is fed back to the voltage-controlled oscillator via a loop filter. In a synchronous circuit, a frequency divider that divides a reference signal by a predetermined frequency division ratio, a counter that counts the frequency-divided signal and is reset by the output of the frequency divider, and that the count value of this counter corresponds to the MSB A comparison circuit for comparing a value obtained by adding and subtracting a predetermined value from a value to be output, and an output circuit for adding or subtracting a voltage to or from a control input of a voltage controlled oscillator corresponding to an output of the comparison circuit; A phase synchronization circuit configured to perform a pull-in operation when a difference between the frequency of the frequency-divided signal and the frequency of the divided signal exceeds a pull-in frequency range of the phase detector.