JP2906532B2 - Multilayer wiring semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring semiconductor integrated circuit, and more particularly to a layout of a plurality of dynamic signal lines.

[Prior Art] FIG. 6 is a circuit diagram for explaining the operation of a dynamic signal line.

Dynamic signal lines 16 to 18 are arranged in parallel, and P-type MO
The sources of SFETs (hereinafter referred to as PMOS) 4 to 6 are connected to the power supply terminal 1
(Hereinafter referred to as V _DD ) to the dynamic signal line 1
6 to 18 are connected to each other, and the gate is connected to clock input terminal 3.
The sources of the N-type MOSFETs (hereinafter referred to as NMOS) 7 to 9 are connected to the ground terminal 2 (hereinafter referred to as GND), the drains are connected to the dynamic signal lines 16 to 18, respectively, and the gates are set to the input terminals 10 to 12. The ends of the dynamic signal lines 16 to 18 are connected to inverter circuits 21 to 23, and the outputs of the inverters 21 to 23 are output terminals 13 to 15.

In this case, when a potential of the GND level is applied to the clock input terminal 3, all the PMOSs 4 to 6 are turned on, the dynamic signal lines 16 to 18 are precharged to the _VDD level, and the GND level is output to the output terminal. . At this time, input terminal 1
GND level potential is applied to 0 to 12 in advance.

Next, when a _VDD level potential is applied to the clock input terminal 3, the PMOSs 4 to 6 are turned off, and at the same time, an arbitrary input terminal 10 to 12 is selected and a _VDD level potential is applied to the selected input terminal. The selected NMOS becomes conductive, the dynamic signal line switches to the GND level, and the potential of the _VDD level is transmitted to the output terminal.

FIG. 5 is a sectional view of a semiconductor chip showing an arrangement of dynamic signal lines in a conventional semiconductor integrated circuit. Reference numeral 24 denotes a semiconductor substrate, 25 denotes a field insulating film, and 16 to 18 denote dynamic signal lines, which constitute one bus.

Usually, a passivation film for protecting the semiconductor integrated circuit is formed on the field insulating film 25 and the dynamic signal lines 16 to 18, but the passivation film is omitted below.

Dynamic signal line 17 has a capacitance between semiconductor substrate 24
In addition to C4, parasitic capacitances C1 and C2 are generated between wirings.

Here, the dynamic signal line 17 is dynamically held at the V _DD level, and the dynamic signal lines 16 and 18 are shifted from the V _DD level.
Dynamic signal line 1 when switching to GND level
7 potential V17 Becomes When the capacitances C1 and C2 between the wirings are larger, the potential drop of the dynamic signal line 17 becomes larger, and a common current flows through the inverter 22, or when the potential drop of the dynamic signal line 17 exceeds the theoretical threshold of the inverter 22,
The output of 22 is inverted and the wrong signal is transmitted.

[Problems to be solved by the invention]

In the above-described conventional semiconductor integrated circuit, it is sufficient to make the wiring interval sufficiently large in order to avoid malfunction due to parasitic capacitance between dynamic signal lines. However, if this is done, the area required for wiring increases, and high integration can be achieved. There is a drawback that you can not.

[Means for solving the problem]

According to the present invention, a power supply wiring or a ground wiring is provided in parallel immediately above or immediately below a plurality of dynamic signal lines formed in parallel on the same layer, or a plurality of power supply wirings or ground wirings formed in parallel on the same layer. A power supply line or a ground line is provided in parallel between the dynamic signal lines, and another dynamic signal line is formed in parallel immediately above or immediately below the power supply line or the ground line. A multilayer wiring semiconductor integrated circuit is obtained.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.

On the field insulating film 25, dynamic signal lines 16 to 18 constituting a bus are arranged in parallel in the first layer. Further, a ground wiring 19 is provided in the second layer via an interlayer insulating film 26 above the dynamic signal lines 16 to 18 constituting the bus arranged in the first layer. C6 and C7 are wiring capacitances, C4 is a capacitance between the dynamic signal line 17 and the semiconductor substrate 24, and C8 is a capacitance between the dynamic signal line 17 and the ground wiring 19.

Here, comparing the total capacitance C1 + C2 + C4 of the dynamic signal line 17 in the conventional example shown in FIG. 5 with the total capacitance C4 + C6 + C7 + C8 of the dynamic signal line 17 in the embodiment shown in FIG. Since there is a large capacitance C8, it is clear that C4 + C6 + C7 + C8> C1 + C2 + C4 (2).

Next, when the dynamic signal line 17 is at the _VDD level and the dynamic signal lines 16 and 18 are at the GND level,
2 and 3 show the lines of electric force generated from. However, the insulating film is omitted.

FIG. 2 is a schematic diagram showing lines of electric force in a conventional example. In this figure, the electric lines of force generated from the upper surface of the dynamic signal line 17 are terminated toward the dynamic signal lines 16 and 18.

FIG. 3 is a schematic diagram showing electric lines of force in one embodiment of the present invention. In this case, the lines of electric force generated from the upper surface of the dynamic signal line 17 are terminated toward the ground wiring 19 of the second layer.

2 and 3, it can be seen that the magnitude relationship between the inter-wiring capacitances C1 and C2 and the inter-wiring capacitances C6 and C7 is C1 or C2> C6 or C7 (3). It can be confirmed by simulation that the capacitances C6 and C7 between the normal wires are reduced by about 50% of the capacitances C1 and C2 between the wires. Here, the dynamic signal line 17 shown in FIG.
Dynamic signal is maintained at V _DD level, and dynamic signal 1
When 6, 18 are switched from the V _DD level to the GND level, the potential V ₁₇ ′ of the dynamic signal line 17 is obtained. Becomes Comparing this with equation (1), (2), (3)
It can be seen from the equation that V ₁₇ <V ₁₇ ′ and the potential drop of the dynamic signal line 17 can be suppressed.

Note that a power supply wiring may be provided instead of the ground wiring.
Further, the layer order of the bus and the ground wiring or the power supply wiring may be switched.

 FIG. 4 is a sectional view of the second embodiment.

In this embodiment, a part (dynamic signal lines 17) of the plurality of dynamic signal lines constituting the bus are arranged in a first layer, and the remaining (dynamic signal lines 16, 18) are arranged in a second layer. A ground wiring 19 is provided between the dynamic signal lines 16 and 18, and the ground wiring 19 is
It is provided directly above. Since the dynamic signal lines 16 and 18 are respectively obliquely above the dynamic signal lines 17, the inter-line capacitances C3 and C5 can be made lower than the inter-line capacitances C1 and C2 in FIG. C3 +
C4 + C5 + C9 is the total capacitance C4 of the dynamic signal line 17 in FIG.
There is an advantage that the switching speed is high because it can be made smaller than + C6 + C7 + C8.

As is clear from this embodiment, a plurality of dynamic signal lines of a certain layer arranged in parallel with a power supply wiring or a ground wiring interposed therebetween and a plurality of dynamic signal lines located immediately above the positions corresponding to the aforementioned power supply wiring or the ground wiring. Alternatively, the bus may be constituted by another dynamic signal line immediately below the lower layer.

〔The invention's effect〕

As described above, the present invention can reduce a potential drop due to a capacitance between wirings by arranging an electrode wiring or a ground wiring immediately above or immediately below a certain layer corresponding to a dynamic signal line of a certain layer. This has the effect of enabling high integration.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip showing a first embodiment of the present invention, FIGS. 2 and 3 are schematic views showing electric lines of force in the conventional example and the first embodiment, respectively, and FIG. FIG. 5 is a cross-sectional view of a semiconductor chip showing a second embodiment, FIG. 5 is a cross-sectional view of a semiconductor chip showing a conventional example, and FIG. 6 is a circuit diagram illustrating dynamic signal lines in a semiconductor integrated circuit. DESCRIPTION OF SYMBOLS 1 ... Power supply terminal, 2 ... Grounding terminal, 3 ... Clock input terminal, 4-6 ... P-type MOSFET, 7-9 ... N-type MOSFET,
10 to 12 Input terminals, 13 to 15 Output terminals, 16 to 18
Dynamic signal lines, 21 to 23: inverter, 24: semiconductor substrate, 25: field insulating film, 26: interlayer insulating film.

Claims (2)

(57) [Claims] A power supply wiring or a ground wiring is provided immediately above or immediately below a plurality of dynamic signal lines formed in parallel in the same layer, and in parallel with the plurality of dynamic signal lines. Wiring semiconductor integrated circuit. 2. A power supply wiring or a ground wiring is provided in parallel between a plurality of dynamic signal lines formed in parallel in the same layer and next to another dynamic signal immediately above or immediately below the power supply wiring or the ground wiring. A multilayer wiring semiconductor integrated circuit, wherein lines are formed in parallel.