JP2906670B2 - Highly efficient digital video signal encoding apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal encoding apparatus and method capable of compressing the transmission data amount of the digital video signal.

[0002]

2. Description of the Related Art There have been proposed various conventional high-efficiency coding apparatuses which can be applied to compress the transmission data amount of a digital video signal. As one of them, DPCM (differential PCM), BTC (block coding), and the like for encoding a difference are known. In these high-efficiency encoding apparatuses, for example, (value of 1: 2 bits of 01), (0:
00), (-1: 10) and (-2: 11).
Each pixel data is represented by four gradations by a bit code signal.

[0003]

In the above-mentioned conventional high-efficiency coding apparatus, the reference value of four gradations is adjusted to the (0) of the 2-bit code signal, so that the level range to be expressed is in each of the upper and lower directions. There was a problem that it was biased to one side. This causes a reduction in the efficiency of the compression. Therefore, an object of the present invention is to eliminate the bias of the conventional high efficiency coding apparatus,
An object of the present invention is to provide a high-efficiency coding apparatus and a method thereof with improved efficiency.

[0004]

According to a first aspect of the present invention, there is provided a digital video signal having a high efficiency which is encoded for each block composed of a plurality of pixel data adjacent to each other in the digital video signal to reduce the data amount. In the encoding device, a first value corresponding to an average value for each block, and second and third values corresponding to restored values having positive and negative differences ± Δ with respect to the average value , optionally. A selectable restoration value and a corresponding fourth value are prepared, the frequency distribution of the level of the pixel data for each block is detected, and the distribution of the detected frequency is 1 or more.
Also, pattern detection for classifying into four or less representative levels is performed.
, One or more and less than four representative levels
Against, respectively, first, second, a code signal for each pixel is generated by assigning the third or fourth value, comprising means for transmitting along with the average information of information and code signals of a difference A high efficiency coding apparatus for digital video signals, characterized in that: According to a second aspect of the present invention, there is provided a high-efficiency encoding method for a digital video signal, wherein encoding is performed for each block composed of a plurality of pixel data adjacent to each other in a digital video signal to reduce the data amount. a first value corresponding to the average of the second and third value corresponding to the restored value with each positive and negative difference ± delta a for the average value, a fourth value corresponding to the restored value to choose arbitrarily Is prepared, and the frequency distribution of the level of the pixel data for each block is detected, and the distribution of the detected frequencies is 1 or more and 4 or less.
Perform pattern detection to classify to the lower representative level, and
A first, second, third, or fourth value is assigned to each of the one or more and four or less representative levels to generate a code signal for each pixel. characterized in that so as to transmit along with the average value information
This is a highly efficient encoding method for digital video signals.

[0005]

The average value information as the reference value is located at the center of the level range to be expressed, the bias is eliminated, and the efficiency can be improved.

[0006]

An embodiment of the present invention will be described below with reference to the drawings. This embodiment is an example of a video signal recording apparatus that records a high-resolution video signal, for example, a high-vision signal on a magnetic tape by a rotating head.

In FIG. 1, reference numeral 1 designates an input terminal for a high-resolution digital video signal to be recorded. In this video signal, each pixel is digitized to 8 bits.
2 indicates a blocking circuit, and by the blocking circuit 2,
The pixel data in the raster scanning order is converted into (2 pixels × 2 lines) sub-block configuration data. As shown in FIG. 2, when the (2 pixels × 2 lines) sub-block is pixel data x11, x12, x21, x22, the block data from the blocking circuit 2 are arranged in the order of x11, x12, x21, x22. Is output. The size of the sub-block substantially corresponds to the ratio of the resolution or data amount between the high-resolution digital video signal and the standard digital video signal. The HDTV signal has approximately twice the number of pixels in the horizontal direction and the number of lines in the vertical direction as compared with the current NTSC system.
The resolution is about four times. Therefore, if the sub-block is 4
It is composed of pixels.

The output of the blocking circuit 2 is supplied to an average value forming circuit 3, a 4-sample delay circuit 9 and a distribution detecting circuit 13, respectively. The average value forming circuit 3 forms an average value y of the pixel data of each sub-block. As shown in FIG. 3, for example, an average value y11 (= x11 + x12 + x21 + x22 / 4) corresponding to pixel data x11, x12, x21, x22 is formed. Similarly, average values y12, y13,..., Y44 are formed for the other sub-blocks. Therefore, FIG.
(8 × 8 lines) from FIG. 3 (4 × 4 = 1)
6) An average value is formed. The data of this average value is A
It is supplied to the DRC encoder 4 and the latch 11.

A clock having a sampling frequency synchronized with the input digital video signal is supplied to an input terminal 5, and this clock is supplied to a frequency dividing circuit 6 to form a clock having a quarter frequency. The clock from the frequency dividing circuit 6 is supplied to the average value forming circuit 3, the latch 11, and the ADRC encoder 4, and these circuits operate in synchronization with the frequency divided clock. The latch 11 sequentially captures the average value of each sub-block.

The ADRC encoding is based on the proposal of the present applicant, and the maximum value M of the pixel data in the ADRC block is obtained.
This coding is adapted to a dynamic range DR which is a difference between AX and its minimum value MIN. In this example, the (4 × 4) average value data in FIG. 3 is used as an ADRC block. The ADRC encoder 4 detects the maximum value MAX and the minimum value MIN among the average values y11 to y44, and calculates (M
AX-MIN = DR), and a dynamic range DR is calculated, and each average value is quantized into a 4-bit length code signal in accordance with the dynamic range DR.
The quantization is a process of dividing the average value data by the quantization step obtained by (DR / 2 ⁴ ) and converting the quotient to an integer. The number of bits of the code signal generated by the ADRC encoder 4 is not limited to 4 bits, and a code signal having a variable number of bits may be formed.

The encoded output of the average value data from the ADRC encoder 4 is supplied to a rate conversion circuit 7. The clock from the input terminal 5 is supplied to the rate conversion circuit 7, and the data rate of the encoded output of the average value data is converted to the original rate, that is, the sampling rate of the high-resolution digital video signal. The output signal of the rate conversion circuit 7 is supplied to the framing circuit 8.

A four-sample delay circuit 9 delays the input video signal until an average value y is formed. The output of the delay circuit 9 is supplied to a subtraction circuit 10. The average value data from the latch 11 is supplied to the subtraction circuit 10. Accordingly, the subtraction circuit 10 detects a difference between the pixel data and the average value data for each sub-block. The difference data is supplied to the additional information generation circuit 12. The detection signal from the distribution detection circuit 13 and the clock from the input terminal 5 are supplied to the additional information generation circuit 12. The distribution detection circuit 13 generates a detection signal corresponding to the level distribution of each sub-block. Additional information is generated from the detection signal, the output signal of the subtraction circuit 10, and, if necessary, the allowable error information. The additional information is a difference signal Δ and a 2-bit signal corresponding to each pixel data.

FIG. 4 schematically shows the generation of additional information, in which pixel data of a sub-block is represented by a 2-bit additional code. When the additional code is (2 bits of 01: 1 value), the difference Δ
Is decoded, and the additional code is (00:
0), the average value y of the block is decoded, and when the additional code is (10: −1), y−Δ obtained by subtracting the difference Δ from the average value y of the block is decoded, and the additional code is ( In the case of 11: -2), decoding is performed as other cases.

The distribution detecting circuit 13 includes a synchronizing circuit 20 and a pattern detecting circuit 21 as shown by a broken line in FIG. An output signal is provided. The synchronizing circuit 20 outputs the pixel data of the sub-block, for example, x11, x13,
x21 and x22 are supplied to the pattern detection circuit 21 in parallel. The pattern detection circuit 21 detects the distribution pattern of the four pixel data, and generates a detection signal Pd. This detection signal Pd is supplied to the additional information generation circuit 12.
The permissible error information is supplied from the input terminal 23 to the pattern detection circuit 21 and the additional information generation circuit 12, and an allowable error range is set. Additional information generation circuit 12
Uses the difference signal from the input terminal 24, the detection signal Pd, and the permissible error information to form additional data for each sub-block, and the additional data is taken out to the output terminal 25.

The pattern detection performed by the pattern detection circuit 21 will be described with reference to FIGS. 6, 7, 8 and 9. In these figures, the horizontal axis is the level I of the pixel data in the sub-block, and the vertical axis is the occurrence frequency F. The distribution of the frequencies represented by this graph is m (m ≦
Classified into the representative level of 4). FIG. 6 shows (m = 1),
That is, it indicates a time when it can be expressed at one representative level. For the four pixel data in this case, a value of 0, that is, (00)
Are assigned. This code signal (00)
Is an average value y.

FIG. 7 shows the case of (m = 2). In this case, the additional data is formed using the values ± 1 and −2. The distribution represented by the graph on the left side of FIG.
The frequency of the level Δ is greater than the frequency 1 of the other level. In the first example , a value of 1, that is, two bits of (01) is assigned to pixel data of a higher frequency level, and a value of -2, that is, (1) is assigned to the other.
Two bits of 1) are allocated. Restored value x of (01)
″ (1) is y + Δ, and the restored value of (11) is represented by the following equation. x ″ (− 2) = (4 × y− (4-1) × x ″ (1)) ÷ l = y + ((4-1) ÷ 1) × Δ

The distribution represented by the graph in the center of FIG.
There are two frequencies, y + Δ level frequency and y−Δ level frequency. In the second example , one value, that is, two bits of (01) is allocated to pixel data of one frequency level, and a value of −1, that is, (1) is allocated to the other.
0) are allocated. Restored value x of (01)
″ (1) is y + Δ, and the restored value x ″ of (10)
(-1) is y-Δ.

The distribution represented by the graph on the right side of FIG.
The frequency of the level of the difference −Δ from the average value y is larger than the frequency 1 of the level that is not the difference −Δ. In the third example , a value of −1,
That is, two bits of (10) are allocated, and a value of −2, that is, two bits of (11) is allocated to the other. The restored value x ″ (− 1) of (01) is y−Δ,
The restored value x ″ (− 2) of (11) is calculated in the same manner as described above.

FIG. 8 shows the case of (m = 3). The distribution represented by the graph on the left side of FIG. 8 has the highest frequency of the average value y, the next highest is the frequency of the difference + Δ from the average value y, and the frequency of the other level is The least. In the first example , two bits (00) are assigned to pixel data having an average value y, and y +
Two bits of (01) are assigned to the pixel data of Δ, and two bits of (11) are assigned to the pixel data of another level.
Bits are assigned. The same treatment is performed when the frequency of the level of y-Δ is the second largest instead of y + Δ. That is, the first example of (m = 3) is a case where one of the three can be represented by (00). The restoration value x ″ (−
2) can be calculated as in the case of FIG.

The distribution represented by the graph on the right side of FIG.
In this case, two of the three can be represented by (1:01) and (-1: 10). That is, this is a case where the frequency of y + Δ or y−Δ is greater than the frequency of other levels. In the second example , (01) is applied to y + Δ pixel data.
Are assigned, two bits of (10) are assigned to pixel data of y-Δ, and two bits of (11) are assigned to pixel data of another level. The decoded value x ″ (− 2) is calculated by the following equation when the respective frequencies are set to 11, 12, and 13 as shown in FIG. x ″ (− 2) = (4 × y−12 × (y−Δ) −13 × (y + Δ)) ÷ 11 = y + (12/11) × Δ− (13/11) × Δ (m = 3 8) (third example) except for the case shown in FIG. 8 (third example) , quantization is performed ignoring the actual distribution, as in the conventional coding, and (0:00) (1:01) (−1: 10) 2 bits are formed. However, the code of (00) in this case is
It means the median, not the average. 4 sub-blocks
In this example consisting of pixels, the frequency of each level of FIG. 8 is respectively 1.

FIG. 9 shows the case of (m = 4). FIG.
Represents when three of the four levels can be represented by 0 and ± 1. In the distribution represented by the graph of FIG. 9, the frequency of the average value y is the largest, and the frequency of the second highest is the frequency of the y + Δ level and the frequency of the y−Δ level. The least. This first
In the example of (2), the pixel data of the average value y
Bits are assigned, two bits of (01) are assigned to pixel data of y + Δ, two bits of (10) are assigned to pixel data of y−Δ, and pixel data of another level is assigned. , (11) are allocated. The decoded value x ″ (− 2) is, as shown in FIG.
When the respective frequencies are set to l1, l2, l3 and l4, they are calculated by the following equations. x ″ (− 2) = ((4 × y−12 × (y−Δ) −13 × (y) −14 × (y + Δ)) ÷ 11 = y + (12/11) × Δ− (14/11 ) × Δ (m = 4) except for the case shown in FIG. 9 (second example) , quantization is performed ignoring the actual distribution, as in the conventional encoding, and (0:00) (1 : 01) (-1: 10), where the code of (00) is
It means the median, not the average. 4 sub-blocks
In this example composed of pixels, the frequency of each level in FIG.

In the case of a small sub-block such as (2 × 2) as in this embodiment, (m = 1) and (m
= 2) in most cases,
It hardly applies to other cases (m = 3) or (m = 4). On the reproduction side, an arithmetic expression for decoding the pixel data to which the two bits (11) are assigned is determined from the other two bits of information in the sub-block.

As described above, when (m = 1), (m =
In the case of 3 in (2), and in the case of 3 (m = 3), (m = 3)
4) A detection signal Pd capable of distinguishing the two cases is generated from the distribution detection circuit 13, and this detection signal Pd and the subtraction circuit 10
The additional information generation circuit 12 generates the difference information Δ and 2-bit data corresponding to each pixel using the information of the difference from. For example, when the output of the distribution detection circuit 13 is (m = 2) and indicates the second case (the distribution at the center in FIG. 7), two bits of (01) are output in response to the positive polarity of the output Δ of the subtraction circuit 10. Occurs, and two bits (11) are formed in response to the negative. These additional data are supplied to the framing circuit 8.

As described above, when (m = 1), (m =
For the third example of 2), when the third example of (m = 3),
A detection signal Pd that can identify the case of the second example of (m = 4)
Is generated from the distribution detection circuit 13, and using the detection signal Pd and the information on the difference from the subtraction circuit 10, the additional information generation circuit 12 generates difference information Δ and 2-bit data corresponding to each pixel. For example, when the output of the distribution detection circuit 13 is (m
= In the case of the second example of the 2) (when indicating the center of the distribution of FIG. 7), in response to the positive polarity of the output Δ of the subtracter circuit 10 (0
Two bits of (1) are generated, and two bits of (11) are formed in response to the negative. These additional data are supplied to the framing circuit 8.

.., Y44 (4 ×
When the ADRC block of 4) is encoded, its minimum value MIN (8 bits) and dynamic range DR (8
) And code signals (4 bits) y11 ',..., Y44' corresponding to each average value are arranged in order. Next, additional data relating to the sub-block consisting of x11, x12, x21, and x22, that is, difference data Δ (7 bits are required to represent the difference between 8-bit pixel data).
And two-bit code signals x11 '' to x22 ''. Therefore, a total of 1 for one sub-block
5 bits (= 7 + 2 × 4) additional data is generated, and 16 bits
The total of the additional data of the sub-blocks is 240 bits. Hereinafter, the additional data of each sub-block is sequentially arranged, and finally the additional data of the x77, x78, x87, and x88 sub-blocks are located.

The above-described output signal of the framing circuit 8 is supplied to the distribution circuit 14 and divided into four channels of recording signals. The recording signal of the first channel (referred to as channel A) is supplied to the recording circuit 15A, and the output signal of the recording circuit 15A is supplied to the rotary head HA. As with the first channel, the second, third and fourth channels (channel B,
The recording signals of channel C and channel D) are recorded by the recording circuit 1
The rotating heads HB, HC, and HD are supplied via 5B, 15C, and 15D, respectively. Recording circuit 15A-
15D includes a digital modulation circuit and a recording amplifier. The recording signal of channel A is only an encoded signal (MIN and DR and code signals y11 ',..., Y44') related to the average value in the recording data of FIG. 10A. Additional data is distributed to channels B, C and D, respectively.

FIG. 11 shows an example of the mechanism of the rotary head. A rotating head H is attached to a drum 31 rotating at a predetermined frequency.
A1, HB1, HC1, and HD1 are provided close to each other, and the rotary heads HA2, HB2,
HC2 and HD2 are provided adjacent to each other. Magnetic tape TP with a winding angle slightly larger than 180 ° around the drum 31
Are wound diagonally. The magnetic tape TP is sent at a constant speed. Therefore, as shown in FIG. 12, the rotary heads HA1, HB1, HC1, and HD1 are provided on the magnetic tape TP.
Tracks TA1, TB1, TC formed by
1, TD1, and rotary heads HA2, HB2, HC2, H
D4, four tracks TA2, TB2,
A track pattern in which TC2 and TD2 are alternately formed is formed. On the tracks TA1 and TA2, as described above, the recording signal of the channel A consisting of only the encoded output of the average value is recorded.

This embodiment is a VTR (referred to as an HD VTR) for recording a high-resolution video signal, but a VTR (SDVTR) for recording a standard-resolution video signal.
) Can also reproduce the magnetic tape TP recorded as described above. As shown in FIG. 13, the SDVTR has a pair of rotary heads HA11 and HA12 provided on a rotary drum at intervals of 180 °. Each head scans the magnetic tape TP alternately.

When the magnetic tape TP on which the track pattern shown in FIG. 12 is formed is sent at four times the speed by the HD VTR and reproduced by the SD VTR, the track crosses four tracks as shown by the broken lines in FIG. The scanning trajectories TA11 and TA12 are formed alternately. Rotating head HA11
By displacing the scanning position of HA12 and the scanning position of HA12 with the piezoelectric element, the tracks TA1 and TA2 are controlled so as to coincide with the scanning trajectories TA11 and TA12, respectively. Therefore, the SD VTR converts the coded signal related to the average value to A
By performing DRC decoding, it is possible to obtain a reproduced image (1/4 resolution of a high-resolution video signal) formed by the average value.

On the contrary, a tape recorded by an SD VTR can be reproduced by an HD VTR. In this sense, bidirectional compatibility can be achieved. SD VTR
The recording circuit compresses image data by ADRC without using differential encoding. As shown by the broken lines in FIGS. 2 and 3, in the SD VTR, (4 × 4 = 16 pixels)
4-bit fixed-length encoding as a DRC block is performed. Since four ADRC blocks are formed from the area of FIG. 2, the recording data shown in FIG. 10B is formed. ADR including, for example, x11, x12,..., X43, x44
The recording data corresponding to the C block includes a minimum value MIN, a dynamic range DR, and code signals x11 'and x12.
, X43 ', x44'. This recording data is recorded on the magnetic tape TP by the rotary head HA1 or the rotary head HA2.

When the magnetic tape on which the recording data shown in FIG. 10B is recorded is reproduced by the HD VTR, the running speed of the magnetic tape is reduced to 1/4 of the normal speed. The tracking deviation caused by the difference in the tape speed is corrected by the piezoelectric element. In the rotating head of HDVTR,
Output of rotary heads HA1 and HA2, ie channel A
Is treated as valid reproduction data, and the reproduction data of other channels is set to 0. The processing of the reproduced data is performed by the AD V provided in the reproduction circuit of the HD VTR.
This can be performed by an RC decoder. In this way,
The HDVTR has the same resolution as that reproduced by the SD VTR, and can obtain a reproduced image having the same number of pixels as the high-resolution video signal.

[0031]

According to the present invention, a value of 0 is assigned to the average value y, a value of +1 is assigned to the level of y + Δ, a value of −1 is assigned to the level of y−1, and so on. Is assigned a value of -2 to any level of. Therefore, the average value y can be obtained on the receiving side and there is no bias, so that there is an advantage that the efficiency is good.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating a part of an image to be processed.

FIG. 3 is a schematic diagram illustrating an average value of a part of an image to be processed.

FIG. 4 is a schematic diagram illustrating generation and restoration values of additional information.

FIG. 5 is a block diagram showing more specific configurations of a distribution detection circuit and an additional information generation circuit.

FIG. 6 is a schematic diagram illustrating a first example of a frequency distribution.

FIG. 7 is a schematic diagram illustrating a second example of a frequency distribution.

FIG. 8 is a schematic diagram illustrating a third example of a frequency distribution.

FIG. 9 is a schematic diagram illustrating a fourth example of a frequency distribution.

FIG. 10 is a schematic diagram illustrating a configuration of print data.

FIG. 11 is a schematic diagram showing an arrangement of a rotary head of a VTR for a high-resolution video signal.

FIG. 12 is a schematic diagram illustrating a recording pattern on a tape.

FIG. 13 is a schematic diagram showing an arrangement of a rotary head of a VTR for a standard resolution video signal.

[Explanation of symbols]

 Reference Signs List 3 average value forming circuit 4 ADRC encoder 8 framing circuit 10 subtraction circuit 12 additional information generation circuit 13 distribution detection circuit 21 pattern detection circuit

Claims (2)

(57) [Claims] 1. A high-efficiency digital video signal encoding apparatus which performs encoding for each block of a plurality of pixel data adjacent to each other in a digital video signal and compresses the data amount. a first value corresponding to said flat
A second and third value corresponding to the restored value with each positive and negative difference ± delta a for the average value, and a fourth value corresponding to the restored value to choose any are available, the level of the pixel data for each said block Frequency distribution of
The distribution of the detected frequencies is represented by one or more and four or less representative records.
Performs pattern detection to classify into bells and classifies one or more
In addition, a code signal for each pixel is generated by assigning the first, second, third or fourth value to each of the four or less representative levels, and the difference information and the code signal are generated. A high-efficiency encoding apparatus for digital video signals, comprising means for transmitting the information together with the average value information. 2. A high-efficiency encoding method for a digital video signal, wherein encoding is performed for each block of a plurality of pixel data adjacent to each other in a digital video signal to reduce a data amount. a first value corresponding to said flat
A second and third value corresponding to the restored value with each positive and negative difference ± delta a for the average value, and a fourth value corresponding to the restored value to choose any are available, the level of the pixel data for each said block Frequency distribution of
The distribution of the detected frequencies is represented by one or more and four or less representative records.
Performs pattern detection to classify into bells and classifies one or more
In addition, a code signal for each pixel is generated by assigning the first, second, third or fourth value to each of the four or less representative levels, and the difference information and the code signal are generated. it has to be transmitted together with the average information
A highly efficient encoding method for digital video signals , characterized in that :