JP2907224B2 - Constant voltage detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a constant voltage detection circuit, and an object of the invention is to provide a low power consumption type constant voltage detection circuit, which is connected between a first power supply and a second power supply. C-MOS
In a constant voltage detection circuit in which a plurality of inverters having a structure are connected in series, one P-channel type MOS transistor is arranged between a node portion of one of the plurality of inverters and the first power supply. , The gate of the P-channel type MOS transistor is connected to a detection signal generation circuit.

Further, the threshold value of the P-channel type MOS transistor is equal to that of the plurality of inverters.
It is configured to be set higher than the threshold value of the transistor.

Further, the detection signal generation circuit, when executing an operation of detecting a drop in the power supply voltage applied to the plurality of inverters, sends a signal for turning on the P-channel type MOS transistor to the gate of the P-channel type MOS transistor. Configure to supply.

[Industrial applications]

The present invention relates to a constant voltage detection circuit, and more particularly to a low power consumption type constant voltage detection circuit.

[Conventional technology]

Conventionally, various control circuits mainly using semiconductor circuits including computers, microcomputers, and the like have been generally used. In such circuits, for example, as long as their power supply voltages are at a certain level, Although there is no particular problem with the functions in those circuits, if the power supply voltage falls below a certain level, the logic state in each logic circuit becomes unstable, and an incorrect logic output is output to cause malfunction. Was causing it to wake up.

Therefore, in such a circuit, the power supply voltage supplied to the circuit is constantly monitored, and if the power supply voltage falls below a certain level, a warning is issued, or the operation of the device or the circuit is stopped. In practice, an LED is caused to emit light, a display means is caused to be blanked, or an alarm is sounded to notify the user of the decrease in the power supply voltage.

However, a circuit as shown in FIG. 2 is used as an example of the above-mentioned conventional constant voltage detection circuit. However, in such a circuit, detection of whether or not the voltage has become low is always executed. The power consumption is high, and the consumption of batteries and the like is so severe that it cannot be said that it is economical, and it is not an ideal low power consumption type constant voltage detection circuit.

That is, in the constant voltage detection circuit in Figure 2 the power supply voltage V _CC
Inverters having a C-MOS structure, for example, four inverters 1-4 connected between the inverter and a ground (GND)
The a circuit connected in series, between the at node portion N to the inverter 3 and the power supply voltage V _CC, arranged MOS transistor TRB of P-channel type, and the P-channel type MOS transistor TRB gate Is connected to ground (GND).

In such a constant voltage detection circuit, an L level signal is normally input to the input IN of the constant voltage detection circuit, and the signal is output through each of the inverters 1 to 4 as long as the signal is a normal power supply voltage V _CC. It is output as an L level signal from OUT.

However, if the power supply voltage V _CC drops and falls below a predetermined voltage level, for example, when the power supply voltage V _CC is 5 V in a 5 V circuit, the power supply voltage V _CC is 3 V or less. , The resistance of the P-channel type MOS transistor TRB and the ratio of the resistance of the N-channel type MOS transistor TRA connected to the MOS transistor TRB at the node N are determined by the relationship between While the output of N is low while the power supply voltage V _CC is normal, if the power supply voltage V _CC falls to 3 V or less, the output of the node N becomes higher. When the voltage rises and exceeds the threshold level of the inverter 3 in the next stage, the output OUT of the circuit is inverted and an H level signal is output.

Therefore, it is considered that the constant voltage detection is executed at the time of the inversion of the output, and an alarm is issued with the H level signal of the output OUT at that time.

However, in such a constant voltage detection circuit, the P
The channel type MOS transistor TRB is always in the ON state, and in the normal state, the N-channel type MOS transistor TRA is also in the ON state as described above, so that current always flows through both MOS transistors.

Of course, in the combination of the P-channel type and N-channel type MOS transistors TRB and TRA, when the power supply voltage V _{CC to} be determined to be low becomes about 3 V or less, the P-channel type MOS Due to the influence of the transistor TRC, a larger through current would flow, and it could not be said that the constant voltage detection circuit was a low power consumption type.

Further, in the above-described constant voltage detection circuit, since the threshold V _TH of the P-channel type TRB is low, it is not possible to accurately detect a drop in the power supply voltage V _CC , and Detection accuracy was insufficient.

[Problems to be solved by the invention]

The present invention solves the problems in the prior art and is a low-power-consumption type constant-voltage detection circuit, which can accurately determine the level drop of the power supply voltage V _CC to be detected. Is provided.

[Means for solving the problem]

The present invention employs the following technical configuration to achieve the above object. That is, the C-MOS connected between the first power supply and the second power supply
In a constant voltage detection circuit in which a plurality of inverters each having a structure are connected in series, one P-channel type MOS transistor is arranged between a node portion of one of the plurality of inverters and the first power supply. , The gate of the P-channel type MOS transistor is connected to a detection signal generation circuit.

Further, the threshold value of the P-channel type MOS transistor is equal to that of the plurality of inverters.
It is configured to be set higher than the threshold value of the transistor.

Further, the detection signal generation circuit, when executing an operation of detecting a drop in the power supply voltage applied to the plurality of inverters, sends a signal for turning on the P-channel type MOS transistor to the gate of the P-channel type MOS transistor. Configure to supply.

(Operation)

Since the present invention employs the above-described configuration, the detection of the presence or absence of a decrease in the power supply voltage V _CC is performed only when an L level signal is output from the detection signal generation circuit. Therefore, power consumption can be greatly reduced, and the P-channel type MOS transistor TRB
Since the is set higher than the threshold value V _TH of the other P-channel type MOS transistor so as say threshold V _TH for example, -3 V, precisely that the power supply voltage V _CC is lower than the predetermined voltage Can be detected.

〔Example〕

Hereinafter, a specific example of the constant voltage detection circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a specific example of a constant voltage detection circuit according to the present invention, in which a power supply having a voltage V _CC as a high-potential power supply (hereinafter referred to as a first power supply) and a ground used as a low-potential power supply A plurality of inverters 1 to 3 having a C-MOS structure connected between a power supply of a level (hereinafter referred to as a second power supply).
4 are connected in series, and the threshold voltage V _TH is set to another P-channel type MOS transistor between the node N in the inverter 2 of the inverter group and the first power supply (power supply voltage V _CC ). It arranged P-channel type MOS transistor TRB which is set higher than the threshold value V _TH of is and that connects the gate of the MOS transistor TRB on the detection signal generation circuit 5.

In the constant voltage detection circuit according to the present invention, the threshold V _TH of the P-channel type MOS transistor TRB is determined according to the level of the power supply voltage V _CC used by the constant voltage detection circuit. However, for example, when the constant voltage detection circuit is used in a system in which the power supply voltage V _CC is 5 V, the threshold V _TH is preferably set to −3 V.

-3V of the threshold V _TH is equal to the power supply voltage V
_Assuming that the allowable level of _CC reduction is 3 V, the power supply voltage V _CC is 3 V
Are those determined as can accurately detect when it becomes less, if you want the level of reduction of the power supply voltage V _CC to give該検and 2.5V therefore, the threshold value V _TH -2.5 V
It is good.

In the present invention, the detection signal generating circuit 5 supplies the gate of the P-channel type MOS transistor TRB with an L level voltage signal, that is, a ground level signal, only when it is desired to execute a detection operation.

The detection signal generating circuit according to the present invention is not limited as long as it has a function of generating an L-level voltage signal when it is desired to check whether the power supply voltage V _CC is lower than a predetermined voltage value. Circuits and devices can be used, and specifically, a clock and a timer built in the microcomputer, software instructions included in the microcomputer, and an appropriate external input device can be used.

In the present invention, the P-channel type MOS is used only when it is desired to check whether the power supply voltage V _CC has dropped as described above.
A ground level signal 6 is supplied from the detection signal generation circuit 5 to the gate of the transistor TRB.
Level signal is the P-channel type MOS transistor TRB
And the MOS transistor TRB
Since the MOS transistor TRB is turned off.
Since the current I _B that penetrates the said N-channel type MOS transistor TRA becomes intermittent, the power consumed is reduced here.

In the conventional constant voltage detection circuit, a current of 20 to 100 μA has been consumed. In the constant voltage detection circuit of the present invention, the current consumption can be suppressed to 0.1 μA.

Next, the operation of the constant voltage detection circuit according to the present invention will be described.

Now, since the threshold value V _TH of the P-channel type MOS transistor TRB of the constant voltage detection circuit in FIG. 1 is set to −3 V, when the power supply voltage V _CC is 5 V, the detection signal generation circuit When the ground level signal 6 is output from the MOS transistor 5, the MOS transistor TRB is ON. On the other hand, the N-channel type MOS transistor TRA has the power supply voltage V _CC applied to its gate, so that Channel type M
OS transistor TRA is also turned on, and both transistors TRB and TR
A current flows to A and the voltage at the node N is
It is maintained at a value determined by the ratio of the internal resistances of RB and TRA.

Therefore, when the power supply voltage V _CC decreases from 5V, as seen from FIGS. 3 and 4, the current I _B and the output voltage V _B that flows through the transistor TRB is rapidly reduced but is an internal resistance constant. On the other hand, since the internal resistance of the transistor TRA rises as the gate voltage decreases (that is, the resistance turns ON), the voltage of the node N rises and at some point the voltage of the node N becomes higher than that of the next inverter 3. output V _OUT becomes as exceeding the threshold value V _TH is applied inverted to the constant voltage detection, i.e. the power supply voltage V _CC is one that can be determined to have decreased.

In the present invention, the output inversion point is determined by the power supply voltage V _CC.
Is set to −3 V in order to cause the voltage drop to 3 V when the threshold voltage V _TH of the P-channel type MOS transistor TRB is set to −3 V.

(Effect)

Since the constant voltage detection circuit according to the present invention employs the above-described configuration, power consumption can be significantly reduced, and a low power consumption type constant voltage detection circuit can be realized. Was.

Further, in the present invention, it is possible to obtain a constant voltage detection circuit capable of accurately detecting that the power supply voltage V _CC has dropped below a predetermined voltage.

[Brief description of the drawings]

FIG. 1 is a diagram showing a specific example of a constant voltage detection circuit according to the present invention. FIG. 2 is a diagram showing an example of a conventional constant voltage detection circuit. 3 and 4 show a P-channel type MO according to the present invention.
FIG. 5 is a diagram showing VI characteristics of an S transistor TRB. 1,2,3,4 Inverter 5 Detection signal generation circuit 6 Detection signal TRB P-channel type MOS transistor TRA N-channel type MOS transistor N Node part

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-192212 (JP, A) JP-A-55-47727 (JP, A) JP-A-56-24623 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H03K 17/00-17/70

Claims (3)

(57) [Claims] 1. A constant voltage detection circuit in which a plurality of inverters having a C-MOS structure connected between a first power supply and a second power supply are connected in series, wherein one of the plurality of inverters is provided. , One P-channel type MOS transistor is arranged between the node portion in FIG.
A constant voltage detection circuit, wherein the gate of the OS transistor is connected to a detection signal generation circuit. 2. The semiconductor device according to claim 1, wherein the threshold value of said P-channel type MOS transistor is a P-channel type MOS transistor.
The constant voltage detection circuit according to claim 1, wherein the constant voltage detection circuit is set higher than a threshold value of the MOS transistor. 3. The P-channel type MOS transistor according to claim 3, wherein said detection signal generating circuit outputs a signal for turning on said P-channel type MOS transistor when performing an operation of detecting a decrease in power supply voltage applied to said plurality of inverters. The constant voltage detection circuit according to claim 1, wherein the constant voltage is supplied to a gate of the constant voltage detection circuit.