JP2908199B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has an array of pixels for performing photoelectric conversion and charge storage, and includes a solid-state image pickup device using a CCD (charge coupled device) and a driving device for driving the solid-state image pickup device. About the method. In particular, the present invention relates to a solid-state imaging device that greatly increases the maximum transfer charge amount.

[0002]

2. Description of the Related Art Various types of two-dimensional solid-state imaging devices are known, but charge-coupled device (CCD) type solid-state imaging devices are excellent in that they have low noise. In general, such CCD type solid-state imaging devices are roughly classified into an interline transfer type and a frame transfer type.
Interline transfer type CCD solid-state imaging devices that have high short-wavelength sensitivity, reduce false signals called "smear", and can be reduced in size have become mainstream.

FIG. 5A is a diagram schematically showing the configuration of a conventional interline transfer type CCD solid-state imaging device. The CCD solid-state imaging device includes a plurality of photosensitive elements (pixels) 1 for performing photoelectric conversion and charge accumulation.
The plurality of pixels 1 are arranged in a vertical and horizontal array along a first direction (hereinafter, vertical direction) and a second direction (hereinafter, horizontal direction) substantially perpendicular to the first direction. CCD
A solid-state imaging device further provided on the right side of each vertical column of the pixels 1 for vertically transferring a signal read from the pixels 1 and one end of each of the vertical charge transfer units 2 The horizontal charge transfer unit 3 is connected to the horizontal charge transfer unit 3, and is provided at one end of the horizontal charge transfer unit 3 to transfer a signal sent from the vertical charge transfer unit 2 in the horizontal direction. An output unit 4 that converts a signal into a video signal and outputs the video signal to an external device.

[0004] Each vertical charge transfer section 2 receives four-phase drive signals S (1), S (2), S (3), and S supplied from an external device.
It has a four-phase structure driven by (4). A pair of vertically adjacent pixels corresponds to one bit of each vertical charge transfer unit 2. For example, the pixels P1 and P2 and the pixels P3 and P4 are each one of the vertical charge transfer units 2.
Corresponds to a bit.

As shown in FIG. 5B, the conventional CCD type solid-state imaging device performs field accumulation and interlace reading. In particular, in the first (odd) field, the output signals from the vertically adjacent pixels P1 and P2 are output as one read unit signal a, and in the second (even) field, the output from the vertically adjacent pixels P2 and P3 are output. Signal 1
The read signal is treated as a read unit signal a '. In the next first field, the output signals from the pixels P3 and P4 adjacent to each other in the vertical direction are one read unit signal b. Is handled as one readout unit signal b '.

FIG. 6 is a diagram schematically showing a conventional signal processing method in the above-mentioned CCD type solid-state imaging device. In this schematic diagram, signal processing only in the first field is shown. The left side of FIG. 6 shows two ones each outputting one readout unit signal a, b,..., H in one pixel vertical column.
A set of pixels P1 + P2, P3 + P4,..., P15 + P16
Is shown. The right side of FIG. 6 shows the time lapse of the read unit signals a, b,..., H in one of the vertical charge transfer units 2 in time series.

FIG. 7 shows a potential distribution of one electrode of the vertical charge transfer unit 2 in a time series in order to show a signal transfer state in the vertical charge transfer unit 2.

In FIG. 7, as shown in FIG.
All signals a1, a captured at 1, P2, P3, P4,.
Are read out to the vertical charge transfer unit 2 at a time. Next, as shown in (2), one set of pixels P1 and P
2, two signals a1 and a2 read from P3 and P4,.
.. b1 and b2... are added to obtain signals (a1 + a2), (b1 + b2).

As shown in FIG. 7 (3) and FIG. 6, all signals existing in the vertical charge transfer section 2 are shifted vertically by one bit at a time, and a signal (a1 + a2), that is, the first read unit signal a To the horizontal charge transfer unit 3. Hereinafter, the read unit signal means a signal read from one unit of pixel. The transferred read unit signal a is horizontally transferred at high speed in the horizontal charge transfer unit 3 and sent to the output unit 4, where it is converted into a video signal and output to an external device.

After the processing of the first read unit signal a, as shown in FIG. 7D, a signal (b1 + b2) for the next one bit of the vertical charge transfer unit 2, that is, the second read unit signal b to the horizontal charge transfer unit 3. The transferred read-out unit signal b is horizontally transferred at high speed in the horizontal charge transfer unit 3 and sent to the output unit 4, where the output unit 4 converts it into a video signal and outputs it to an external device.

The third read unit signal c (FIG. 7 (5)), the fourth read unit signal d (FIG. 7 (6)) and the subsequent read unit signals are processed in the same manner as described above. . The horizontal charge transfer unit 3 transfers the signal corresponding to one bit of the vertical charge transfer unit 2 to the output unit 4 at a high speed every time the signal is received. The output unit 4 converts the signal into a video signal and outputs it to an external device.

In this manner, as shown in FIG.
The read unit signal corresponding to one bit of the vertical charge transfer unit 2 is sequentially sent to the horizontal charge transfer unit 3 for each horizontal scanning period 1H, and output from the output unit 4.

[0013]

Therefore, the conventional C
In the CD-type solid-state imaging device, one read unit signal corresponds to only one bit of the vertical charge transfer unit 2. That is, the maximum transfer charge amount that the vertical charge transfer unit 2 can handle is limited to the transfer charge amount in one bit. Since the dynamic range of the solid-state imaging device depends on the maximum transfer charge amount, the dynamic range of the solid-state imaging device is limited when the maximum transfer charge amount is limited to a specific amount. This becomes a problem when miniaturization of the solid-state imaging device is desired.

As a solution to this problem, two transfer methods are disclosed in JP-A-60-119182 (FIG. 8).
(A)) and JP-A-60-183881 (FIG.
(B)). Both of these methods are called a charge sweeping method, in which one readout unit signal is read out and spread in one vertical charge transfer unit, and the charge of the signal is read out within one horizontal transfer period. This is a method of collecting the data in a storage unit provided at one end of the storage device. However, the operation of collecting the signal charges into the storage section is performed by gradually expanding the potential barrier X in the method shown in FIG. 8A, and in the method shown in FIG. The transfer is performed by a plurality of transfer operations while dispersing the charge of the signal.

According to the above-described transfer method, the amount of transfer charge corresponding to one video signal that can be handled by the vertical charge transfer section can be greatly increased, but there are the following problems. That is, the operation of collecting the signal charge read from the pixel to the vertical charge transfer unit at one end of the vertical charge transfer unit is performed while the horizontal charge transfer unit performs the operation of transferring the signal charge to the output unit, that is, Since the operation is performed during the output of the video signal, a driving pulse signal for driving the vertical charge transfer unit may be mixed in the video signal to generate noise. In addition, since the signal charges are collected from the entire area in the vertical charge transfer section to the storage section provided at one end thereof, the number of drive pulse signals required for this collecting operation increases, and the power consumption also increases.

The present invention has been made to solve such problems of the prior art, and is intended to be handled by a vertical charge transfer section.
By increasing the maximum transfer charge that can be
The image required for reducing the size of the body imaging device and increasing the number of images
It is an object of the present invention to provide a solid-state imaging device capable of realizing high density .

Another object of the present invention is to provide a solid-state imaging device capable of preventing problems such as an increase in power consumption and the incorporation of clock noise into an output signal.

[0018]

A method of driving a solid-state imaging device according to the present invention comprises a pixel portion including n pixels for performing photoelectric conversion and charge storage arranged in a first direction, and connected to the pixel portion. A first charge transfer unit that transfers a signal read from each of the pixels arranged in the pixel unit in the first direction, and is connected to one end of the first charge transfer unit;
A second charge transfer means for receiving a signal transferred by the first charge transfer means and transferring the received signal in a second direction; and one end of the second charge transfer means, receives the signals transferred by the second charge transfer means, an output means for outputting to an external device converts the signal received the the video signal, the n-number of pixels, the first
From the pixel (i = 1) to the n-th pixel (i = n)
And the first pixel is connected to the second charge transfer means most.
And the n-th pixel is located at the second position
Is disposed farthest from the charge transfer means of
The first charge transfer means includes a first bit portion (i = 1)
To the n-th bit portion (i = n),
Is located at a position closest to the second charge transfer means.
And the n-th bit portion is the second charge transfer.
A method for driving a solid-state imaging device disposed at a position farthest from a sending unit , comprising: (1) starting from a first pixel (i = 1) of n pixels arranged in the pixel unit; Is transferred to the first bit portion (i =
Reading over k bits from 1) ,
(2) The read signal corresponding to k bits of the first charge transfer means is supplied to the first charge transfer means during one horizontal blanking period.
(3) the read first
A signal corresponding to k bits of the charge transfer means of (k-
1) Shifting toward the second charge transfer means by the amount of bits
After that, the signal from the (i + 1) -th pixel of the n pixels arranged in the pixel portion is k bits from the (i + 1) -th bit portion of the first charge transfer means. Reading step, (4) the steps (2) to
Repeating (3) for i = 1 to i = n−1 , and (5) after the n-th pixel farthest from the second charge transfer means has been read, Including the step of repeating (2) , where k is smaller than n
It is an integer of 2 or more, whereby the above object is achieved.

In one embodiment of the present invention, the transfer step (2) includes the step of converting the signal corresponding to k bits of the first charge transfer means into a first signal portion corresponding to (kp) bits. And dividing the signal portion into a second signal portion corresponding to p bits, and transferring the first signal portion and the second signal portion in the first direction during one horizontal blanking period. p may be an integer satisfying 1 ≦ p <k.

In another embodiment of the present invention, the pixel has a first pixel portion and a second pixel portion, and the signal comprises a signal from the first pixel portion and a signal from the second pixel portion. And the sum of

According to another aspect of the present invention, a solid-state imaging device includes a pixel portion including n pixels that perform photoelectric conversion and charge storage arranged in a first direction, and is connected to the pixel portion; A first charge transfer unit configured to transfer a signal read from each of the pixels arranged in the pixel unit in the first direction; a first charge transfer unit connected to one end of the first charge transfer unit; Second charge transfer means for receiving the signal transferred by the means and transferring the received signal in a second direction;
Output means connected to one end of the charge transfer means for receiving the signal transferred by the second charge transfer means, converting the received signal into a video signal, and outputting the video signal to an external device; Driving means for driving the charge transfer means ,
The n pixels are numbered from the first pixel (i = 1) to the n-th pixel.
Eye pixel (i = n), wherein the first pixel is the second pixel
Is disposed at the position closest to the charge transfer means of
The n-th pixel is located farthest from the second charge transfer means.
And the first charge transfer means comprises a first charge transfer means.
Bit portion (i = 1) to the n-th bit portion (i =
n) wherein the first bit portion comprises the second charge transfer
Means that is located closest to the
The cut portion is disposed at a position farthest from the second charge transfer means.
Have been. The driving means includes: (1) a signal from a first pixel (i = 1) of the n pixels arranged in the pixel section, i =
(1) reading over k bits from ( 1) , (2) transferring the read-out signal corresponding to k bits of the first charge transfer means in the first direction during one horizontal blanking period, 3) A signal corresponding to k bits of the read first charge transfer means is changed by (k-1) bits to the second charge transfer means .
After shifting toward the charge transfer means, the signal from the (i + 1) -th pixel of the n pixels arranged in the pixel portion is transferred to the (i + 1) -th <(i + 1) -th pixel of the first charge transfer means. (4) The steps (2) to (3) are read from i = 1 to i = n-1.
Repeat Te, (5) after the n-th pixel farthest from the charge transfer unit of the second is read, generates a plurality of driving signals for repeating said step (2), k
Is an integer of 2 or more smaller than n . This achieves the above object.

In one embodiment of the present invention, the signal corresponding to k bits of the first charge transfer means in the step (2) is a first signal portion corresponding to (kp) bits and p It is divided into a second signal portion corresponding to bits, and the first signal portion and the second signal portion are transferred in the first direction during one horizontal blanking period, and p is 1 ≦ p <
It can be an integer that satisfies k.

In another embodiment of the present invention, each of the pixels has a first pixel portion and a second pixel portion, and the signal comprises a signal from the first pixel portion and a second pixel portion. And the sum of the signals.

[0024]

According to the present invention, one read unit signal is read over the k-bit portion of the vertical charge transfer section. With this configuration, the maximum transfer charge amount of the vertical charge transfer unit can be increased k times.

Further, according to the present invention, the vertical charge transfer unit reads out a signal as one readout unit signal from one or a plurality of pixels, and puts the signal into the k-bit portion of the vertical charge transfer unit. The signal corresponding to the k-bit part is called a k-bit signal. After the (k-1) -bit signal of the k-bit signal is transferred, the next readout unit signal from one or more pixels is read out and put into the k-bit portion of the vertical charge transfer unit. The k-bit portion of the next read unit signal is shifted vertically by one bit from the k-bit portion of the previous read unit signal to a position farther from the horizontal charge transfer unit. Therefore, the signals read to the vertical charge transfer unit are always arranged without any empty bit portion therebetween, and the utilization efficiency of the vertical charge transfer unit is high. In the vertical charge transfer section, the signal transfer operation only needs to be performed during the horizontal blanking period. Therefore, since the driving pulse signal is applied to the electrodes of the vertical charge transfer section only during the horizontal blanking period, the increase in power consumption does not matter, and the problem of noise generation in the output signal can be prevented.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 3A is a schematic view showing the structure of a solid-state imaging device according to the present invention. This solid-state imaging device includes photoelectric conversion devices arranged in a vertical and horizontal array along a first direction (hereinafter, vertical direction) and a second direction (hereinafter, horizontal direction) substantially perpendicular to the first direction. And a plurality of pixels 1 for performing charge accumulation. The solid-state imaging device further includes a vertical charge transfer unit 2 that is provided adjacent to each vertical column of the pixel 1 and transfers a signal read from the pixel 1 in the vertical direction. A horizontal charge transfer unit 3 connected to one end and transferring a signal sent from the vertical charge transfer unit 2; and a horizontal charge transfer unit 3 connected to one end of the horizontal charge transfer unit 3 and sent from the horizontal charge transfer unit 3. An output unit 4 converts an incoming signal into a video signal and outputs it to an external device, and a drive circuit 5.

The vertical charge transfer section 2 is formed in a four-phase structure.
Four electrodes are provided as one group corresponding to 1-bit signal transfer of the vertical charge transfer unit 2. On the other hand, the driving circuit 5 has different driving signals S (1), S (2),
S (3), S (4), S (5),... Are generated, and the driving signals are applied to the electrodes of the vertical charge transfer unit 2, respectively.
These drive signals S (1), S (2), S (3), S
(4), S (5)... Are for reading the signal of the pixel 1 to the vertical charge transfer unit 2 and then shifting the signal in the vertical charge transfer unit 2 in the vertical direction. The type of the generated drive signal and a method of applying the drive signal to the electrodes of the vertical charge transfer unit 2 will be described below.

As shown in FIG. 3B, the solid-state imaging device according to the present embodiment performs field accumulation and interlace reading. In the first (odd) field, the output signals from the vertically adjacent pixels P1 and P2 are read out as one unit signal 2a. In the second (even) field, the output signals from the vertically adjacent pixels P2 and P3 are read out. In the next first field, the output signals from the vertically adjacent pixels P3 and P4 are treated as one readout unit signal 2b, and in the second field, the vertically adjacent pixels P4 and P5 are read out in the second field. Is handled as one readout unit signal 2b '. The read mode is not limited to the above mode, and the present invention is applicable to other read modes. For example, each pixel P
It will be understood by those skilled in the art that the present invention can be applied to a case where output signals from 1, P2, P3, P4,... Are each treated as one read unit signal.

FIG. 1 is a schematic diagram showing an example of a signal read and transfer operation used for the solid-state imaging device of the present embodiment. In this schematic diagram, a signal read operation only in the first field is shown. The left side of FIG. 1 shows one readout unit signal a, b,
.., H each output a pair of pixels P1 + P2,
P3 + P4,..., P15 + P16. Instead of reading out signals from each pair of pixels as one readout unit signal, it is also possible to read out signals from each pixel as one readout unit signal. The right side of FIG. 1 shows the read unit signals a, b,..., H in one vertical charge transfer unit 2.
Are shown in time series.

FIG. 2 shows the potential distribution of the electrodes of the vertical charge transfer section 2 in order to show the state of signal transfer in the vertical charge transfer section 2.

Referring to FIGS. 1 and 2, a method of reading a signal as one read unit signal to the vertical charge transfer unit 2 and a method of transferring the read signal to the horizontal charge transfer unit 3 will be described below. I do. First, as shown in FIG. 2A, signals a1, a2 formed in two pixels P1 and P2,
a2 is read out to the vertical charge transfer unit 2. Next, as shown in (2), the signals a1 and a2 are added over two bits of the vertical charge transfer unit 2 to add a signal a1 + a2 (ie, 2a).
Get. Next, as shown in (3), the signal a1 + a2 is divided into two (a1 + a2) / 2 signals (that is, a).
Get. That is, the first unit read signal 2a corresponding to the first video signal is converted to the first pixel unit, for example, 2
The data is read out from the two pixels P1 and P2 and put into the 2-bit portion of the vertical charge transfer unit 2 (see FIG. 1). Hereinafter, a signal corresponding to k bits of the vertical charge transfer unit 2 is referred to as a k-bit signal.

Next, as shown in (4), the signal existing in the vertical charge transfer unit 2 is vertically shifted by one bit, and
The first read unit signal a is transferred to the horizontal charge transfer unit 3.

Next, as shown in (5), the next signals b1 and b2 are read from the next two pixels P3 and P4. (6)
As shown in the figure, both signals b1 and b2 are
The signal b1 + b2 (that is, 2
Obtain b). Thereafter, the signal b1 + b2 is divided to obtain two (b1 + b2) / 2 signals (that is, b). That is, the second unit read signal 2b is read from the second pixel unit, for example, from the two pixels P3 and P4, and is input to the 2-bit portion of the vertical charge transfer unit 2 (see FIG. 1). The 2-bit portion of the second read unit signal is shifted vertically by one bit from the 2-bit portion of the first read signal to a position farther from the horizontal charge transfer section 3. As shown in (7), all signals existing in the vertical charge transfer unit 2 are shifted by one bit in the vertical direction, and the signal a for the second one bit is transferred to the horizontal charge transfer unit 3. The signal a for one bit and the signal a for one bit transferred earlier are added in the horizontal charge transfer unit 3 to obtain a signal (a1 + a2) corresponding to one video signal. A signal (a) corresponding to one video signal
The processing consisting of (1) to (7) for obtaining (1 + a2) is performed during one horizontal blanking period.

Thereafter, as shown in (8), during the horizontal transfer period, the signal (a1 + a2) is transferred in the horizontal charge transfer unit 3 at high speed to the output unit 4 in the horizontal direction, and the output unit 4 converts the signal into an output signal. Convert.

The above signal read and transfer operations are repeated for each of the read unit signals 2b, 2c,..., 2h at every horizontal transfer cycle 1H as shown in (9) to (15). Readout unit signal 2 from a pixel unit farthest from 3 (for example, two pixels P15 and P16)
h, and read out the signal as a signal (h, h).
Into the other two-bit part of As a result, each signal corresponding to one readout unit signal is transferred to the output unit 4 by the horizontal charge transfer unit 3 at intervals of the horizontal scanning period 1H.

Thereafter, the vertical charge transfer section 2 performs only the signal transfer operation. That is, the signals e and e, f and f, g and g, and h and h read into the vertical charge transfer unit 2 over two bits are transferred to the horizontal charge transfer unit 3 as shown in FIG. These signals are added in the horizontal charge transfer unit 3 to generate signals (e + e), (f + f), (g +
g) and (h + h) are read out to the output unit 4.

When the signal read and transfer operation in the first field is completed, the signal read and transfer operation in the second field of the same vertical column of pixels is performed in the same manner as before.

As described above, in the solid-state imaging device of the present embodiment, since the vertical charge transfer unit 2 reads one read unit signal over two bits, the maximum transfer charge amount of the vertical charge transfer unit 2 is doubled. Can be.

After shifting one bit signal of the two-bit signal in the vertical charge transfer unit 2, the next one read unit signal is read out to another two-bit portion of the vertical charge transfer unit 2. The 2-bit portion of the read unit signal is shifted by one bit from the first 2-bit position of the read unit signal to a position farther from the horizontal charge transfer unit 3 in the vertical direction.
Therefore, the signals read to the vertical charge transfer unit 2 are always lined up in the vertical charge transfer unit 2 without any empty bits, and the utilization efficiency of the vertical charge transfer unit 2 is high. The signal transfer operation in the vertical charge transfer section is performed only during the horizontal blanking period. Therefore, the drive signal only needs to be applied during the horizontal blanking period, and there is no problem of an increase in power consumption and no problem of noise generation in the output signal.

FIG. 9 shows an example of the circuit configuration of the drive circuit 5. The transfer pulse generator 10 generates pulse signals φ _V1 , φ _V2 ,
Generate φ _V3 and φ _V4 . These pulse signals are supplied to the scanner 13. Read level supply unit 11
Supplies a voltage signal V _H indicating the read level to the scanner 14.
To supply. Accumulation level supplier 12 supplies a voltage signal V _M to the scanner 15, which indicates accumulation level. Scanner 1
3 receives the pulse signal phi _G, the scanner 14 receives a pulse signal phi _T, the scanner 15 receives a pulse signal phi _ST. The scanners 13, 14, and 15 also receive a clock signal φ _CK for synchronization. Each scanner generates a signal according to a predetermined logic, as described in detail below. As a result, the drive signal S
(1), S (2), S (3)... Are generated. These drive signals are respectively applied to the electrodes of the vertical charge transfer unit 2.

FIG. 10 shows pulse signals φ _{V1 to} φ _V4 , φ _G ,
The waveforms of φ _T , φ _ST , and clock signal φ _CK are shown, respectively. In FIG. 10, the portions omitted by vertical dashed lines correspond to the effective horizontal scanning period, and the portions between the omitted portions correspond to the horizontal blanking period. In FIG. 10, a pulse signal φ _V1
Portion surrounded by the dashed line in the waveform of the to [phi] _V4 are omitted for convenience. FIG. 11 shows the omitted part. FIG.
1 indicates a four-phase pulse signal. In FIG. 11, n is an integer. For example, when n = 1, the drive signal S (1)
Is the top waveform in FIG. 11, and the drive signal S (2) is the second waveform from the top.

FIG. 12 shows a circuit configuration corresponding to the j-th electrode (hereinafter, referred to as a gate _Sj ) of the vertical charge transfer section 2 in order to make the operation of each scanner easy to understand. The pulse signals φ _G , φ _T , and φ _ST are supplied to corresponding switching elements in each scanner via logic units in each scanner. When the pulse signals φ _G , φ _T and φ _ST are at a high level, the corresponding switching elements are turned on, and the pulse signals φ _{V1 to} φ _V4 and the voltage signal V
_H and V _M is applied to the gate S _j. Pulse signals φ _G , φ
_{When T} and φ _ST are at the low level, the corresponding switching element is turned off, and the capacitance C _{j of the} gate S _j itself is set.
As a result, the DC level immediately before switching is maintained.

The scanners 13, 14, and 15 have logic units 16, 17, and 18, respectively. The configuration of each logic unit differs depending on the value of k corresponding to the k-bit signal. The configuration of each logic unit when k = 2 will be described below. The logic unit 16 in the scanner 13 has 1 ≦
The pulse signal φ _G is supplied to the switching elements T _{1, j} satisfying the relationship j ≦ 4m + 4. Here, m is an integer indicating the cycle number of the clock signal φ _CK counted from the start of one field. The switching element T _{1, j} is a j-th switching element connected to the gate S _j in the scanner 13. Logic unit 17 in the scanner 14 supplies the pulse signal phi _T to the switching element T _{2, j} which satisfies the relationship of j = 4m-3 or j = 4m-1. Here, the switching element T _{2, j} is connected to the scanner 14
, A j-th switching element connected to the gate S _j . The logic unit 18 in the scanner 15 supplies the pulse signal φ _ST to the switching elements T _{3, j} satisfying the relationship of 4m−3 ≦ j ≦ 4m + 4. Here, the switching element T _{3, j} is a j-th switching element connected to the gate S _j in the scanner 15.

FIG. 13 shows the driving circuit 5 as described above.
Drive signals S (1), S (2), S
(3) shows the waveforms. In FIG. 13, a portion of the waveform surrounded by a broken line is omitted for convenience. The omitted part is shown in FIG. By applying a drive signal having the waveform shown in FIG. 13 to the electrodes of the vertical charge transfer unit 2, a signal read and transfer operation substantially equivalent to the signal read and transfer operation shown in FIGS. 1 and 2 is realized. Is done.

(Embodiment 2) FIG. 4 schematically shows signal read and transfer operations used for a solid-state imaging device according to a second embodiment of the present invention. On the left side of FIG. 4, the readout unit signals 4a, 4b,.
h, each of which outputs a pair of pixels P1 + P2, P3
+ P4,..., P15 + P16. Instead of reading out the signals from one set of two pixels as one readout unit signal,
It is also possible to read out signals from individual pixels as one readout unit signal. 4 shows the time lapse of the signals 4a, 4b,..., 4h in one vertical charge transfer unit 2 in time series.

Referring to FIG. 4, a signal is applied to vertical charge transfer section 2.
A method of reading the read signal as one read unit signal and a method of transferring the read signal to the horizontal charge transfer unit 3 will be described in detail below. First, a pair of pixels P1, P2
Are read out to the vertical charge transfer unit 2. Next, the signals a1 and a2 are added over the 4-bit portion of the vertical charge transfer unit 2, and the signals a1 + a2 (ie, 4a) are added.
Get. Next, the signal a1 + a2 is divided to obtain four (a1 + a2) / 4 signals (that is, a). That is, the first read unit signal 4a is read from the first pixel unit, for example, a set of two pixels P1 and P2,
It is stored in the 4-bit portion of the vertical charge transfer section 2. As a result,
The signal (a, a, a, a) is formed in a 4-bit portion of the vertical charge transfer unit 2. Next, the signal (a, a, a, a) present in the vertical charge transfer unit 2 is shifted by 3 bits in the vertical direction, and a signal 3 a corresponding to 3 bits of the vertical charge transfer unit 2 is sent to the horizontal charge transfer unit 3. Forward. After that, the second readout unit signal 4b is read out from the second pixel unit, for example, from a pair of pixels P3 and P4, and is input to another 4-bit portion of the vertical charge transfer unit 2. As a result, while the signal a corresponding to one bit of the vertical charge transfer unit 2 is left in the vertical charge transfer unit 2, the signal (b,
b, b, b) are formed. The 4-bit portion of the second readout unit signal is shifted by one bit from the 4-bit portion of the first readout unit signal to a position farther from the horizontal charge transfer unit 3 in the vertical direction.

Next, all the signals present in the vertical charge transfer unit 2 are shifted by one bit in the vertical direction, and the signal a for the remaining one bit is transferred to the horizontal charge transfer unit 3. In this manner, the signal (a, a, a, a) is transferred to the vertical charge transfer unit 3 with three bits divided into the first transfer and one bit divided into the second transfer. After that, 3
The vertical charge transfer unit 3 adds the signal for one bit and the signal for one bit newly transferred to obtain a signal (3a + a).
Get. The processing until the signal (3a + a) is obtained is performed during one horizontal blanking period.

Thereafter, the first signal (3a + a) is transferred in the horizontal charge transfer section 3 at high speed to the output section 4 at high speed during the horizontal transfer period, and is converted into a video signal by the output section 4.

Next, the signal (b, b, b, b) existing in the vertical charge transfer section 2 is shifted by 2 bits in the vertical direction,
The signal 2b is transferred to the horizontal charge transfer unit 3. Thereafter, the third readout unit signal 4c is read out from the third pixel unit, for example, from a set of pixels P5 and P6, and is input to the other 4-bit portion of the vertical charge transfer unit 2. As a result, the signal (c, c, c, c) is newly added to the 4-bit portion of the vertical charge transfer section 2 while the signal 2b corresponding to the two bits of the vertical charge transfer section 2 is left in the vertical charge transfer section 2. Formed. Next, all signals existing in the vertical charge transfer unit 2 are shifted by 2 bits in the vertical direction, and the remaining signal 2b is transferred to the horizontal charge transfer unit 3. In this way, the signals (b, b,
In (b, b), two bits are transferred to the horizontal charge transfer unit 3 in the first transfer and two bits in the second transfer.
Thereafter, the horizontal charge transfer unit 3 adds the previously transferred two-bit signal and the newly transferred two-bit signal to obtain a signal (2b + 2b). Signal (2b + 2
The processing for obtaining b) is performed during one horizontal blanking period.

Thereafter, the second signal (2b + 2b)
Is transferred to the output unit 4 in the horizontal direction at high speed in the horizontal charge transfer unit 3 during the horizontal transfer period, and the output unit 4 converts the video signal into a video signal. Next, the signals (c, c) existing in the vertical charge transfer
c, c, c) is shifted by one bit in the vertical direction, and the signal c is transferred to the horizontal charge transfer unit 3. Thereafter, the fourth readout unit signal d is read out from the fourth pixel unit, for example, from a set of pixels P7 and P8, and is input to the other 4-bit portion of the vertical charge transfer unit 2. As a result, the signal (d, d, d, d) is transferred to the vertical charge transfer unit 2 with the signal 3c corresponding to three bits of the vertical charge transfer unit 2 remaining in the vertical charge transfer unit 2.
Is formed in the 4-bit portion.

Next, all signals existing in the vertical charge transfer section 2 are shifted by 3 bits in the vertical direction,
To transfer the signal 3c for 3 bits. In this way,
The signal (c, c, c, c) is such that 1 bit is the first transfer, 3
The bit is divided into two in the second transfer and the horizontal charge transfer unit 3
Transferred to The one bit transferred earlier and the newly transferred three bits are added in the horizontal charge transfer unit 3 to obtain one pixel signal (c + 3c). Processing for obtaining this signal (c + 3c) is performed during one horizontal blanking period.

Thereafter, the third signal (c + 3c) is
During the horizontal transfer period, the data is transferred to the output unit 4 in the horizontal charge transfer unit 3 in the horizontal direction at a high speed, and the output unit 4 converts the video signal into a video signal.

After that, the fifth readout unit signal 4e is read out from the fifth pixel unit, for example, from a set of pixels P9 and P10, and is input to the other 4-bit portion of the vertical charge transfer unit 2. As a result, the signals (d, d,
The signal (e, e, e, e) is formed in the 4-bit portion of the vertical charge transfer unit 2 while leaving (d, d).

Next, all the signals existing in the vertical charge transfer unit 2 are shifted by 3 bits in the vertical direction, and a signal 3 d corresponding to 3 bits of the vertical charge transfer unit 2 is transferred to the horizontal charge transfer unit 3. .

Thereafter, the sixth read unit signal 4f is read from the sixth pixel unit, for example, a set of pixels P11 and P12, and is input to the other 4-bit portion of the vertical charge transfer unit 2. As a result, the signal d and the signal (e, e, e) corresponding to one bit of the vertical charge transfer unit 2 are transmitted to the vertical charge transfer unit 2.
The signal (f, f, f, f) is newly formed in the 4-bit portion of the vertical charge transfer unit 2 while leaving e, e).

Next, all the signals existing in the vertical charge transfer unit 2 are shifted by one bit in the vertical direction, and the remaining signal d is transferred to the horizontal charge transfer unit 3. Thereafter, the horizontal charge transfer unit 3 adds the previously transferred 3 bits 3d and the newly transferred 1 bit d to generate a signal (3d + d).
Get. Processing for obtaining this signal (3d + d) is performed during one horizontal blanking period.

Thereafter, the fourth signal (3d + d) is
During the horizontal transfer period, the data is transferred to the output unit 4 in the horizontal charge transfer unit 3 in the horizontal direction at a high speed, and the output unit 4 converts the video signal into a video signal.

The above-described signal readout and transfer operations are repeated, and the eighth pixel unit farthest from the horizontal charge transfer unit 3,
For example, the eighth signal 4 from one set of pixels P15 and P16
h is read and put into another 4-bit portion of the vertical charge transfer section 2. At this time, the transfer of the signal (e, e, e, e) to the horizontal charge transfer unit 3 is performed by dividing two bits into the first transfer and two bits into the second transfer twice. .

Thereafter, in the vertical charge transfer section 2, only the signal transfer operation is performed. That is, 4 in the vertical charge transfer section 2
The signal (f, f, f,
f), (g, g, g, g) and (h, h, h, h)
1 bit and 3 bits for signal (f, f, f, f), 3 bits and 1 bit for signal (g, g, g, g), signal (h, h, h, h) For 2 bits and 2
Each of the bits is transferred to the horizontal charge transfer unit 3 separately.
These separately transferred signals are added in the horizontal charge transfer unit 3, and the signals (f + 3f), (3g + g),
(2h + 2h) are obtained. These signals are transferred to the output unit 4.

When the signal read and transfer operation in the first field is completed, the signal read and transfer operation in the second field of the same vertical column of pixels is performed in the same manner as before. According to the solid-state imaging device of the present embodiment, since the vertical charge transfer unit 2 reads one read unit signal over a 4-bit portion, the maximum transfer charge amount of the vertical charge transfer unit can be quadrupled. Further, similarly to the first embodiment, the vertical charge transfer unit 2 can be used efficiently, and there is no problem of an increase in power consumption and generation of noise in an output signal.

In the above embodiment, each read unit signal is read over 2 bits or 4 bits in the vertical charge transfer section. However, the configuration of the solid-state imaging device according to the present invention is not limited to the above configuration. . 1
Assuming that the number of pixels forming one vertical column is m, one readout unit signal can be read out over k bits of the vertical charge transfer unit 2. Here, k is smaller than m 2
Is an integer greater than or equal to. In this case, similarly to the method described in the above embodiment, the maximum transfer charge amount of the vertical charge transfer unit can be increased by k times.

Further, according to the present invention, the vertical charge transfer section reads a signal as one read unit signal, and puts the signal into the k-bit portion of the vertical charge transfer section. A signal corresponding to k bits is called a k-bit signal. After transferring the (k-1) -bit signal of the k-bit signal, the next one read unit signal is read from the pixel, and the read signal is input to another 4-bit portion of the vertical charge transfer unit. The k-bit portion of the next read unit signal is shifted by one bit from the k-bit portion of the previous read unit signal to a position farther in the vertical direction from the horizontal charge transfer unit. Therefore, the signals read to the vertical charge transfer unit are always arranged without any empty bits therebetween, and the utilization efficiency of the vertical charge transfer unit is high. In the vertical charge transfer section, the signal transfer operation is performed only during the horizontal blanking period. Therefore, the drive signal only needs to be applied during the horizontal blanking period, and there is no problem of an increase in power consumption and no problem of noise generation in the output signal.

As in the first embodiment, the signal read and transfer operations shown in FIG. 4 can be performed by a drive circuit having the same configuration as the circuit configuration shown in FIG.

In the above embodiment, the vertical charge transfer section is provided on the right side of each vertical column of pixels. However, the above-described read and transfer operation is performed by setting the vertical charge transfer section on the left side of each vertical column of pixels. The present invention is also applicable to a solid-state imaging device.

Further, in the above embodiment, the horizontal charge transfer section is 1
However, the read and transfer operations described above are also applicable to a solid-state imaging device having a plurality of vertical charge transfer units.

[0067]

As described in detail above, according to the signal processing method for a solid-state imaging device of the present invention, it is possible to greatly increase the transfer charge amount of the vertical charge transfer section, and thereby the dimensions of the solid-state imaging device can be increased. It is advantageous to increase the pixel density required for reducing the size and increasing the number of images. Further, as compared with the conventional driving method, reading of one pixel signal and transfer of several bits are only added during the horizontal blanking period.
Problems such as an increase in power consumption and a jump in clock noise do not occur, which is extremely advantageous in practical use.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating read and transfer operations in a solid-state imaging device according to the present invention.

FIG. 2 is a potential distribution diagram illustrating signal transfer in a vertical charge transfer unit of the solid-state imaging device according to the present invention.

FIGS. 3A and 3B are schematic diagrams illustrating a configuration of a solid-state imaging device according to the present invention.

FIG. 4 is a schematic diagram showing read and transfer operations in another solid-state imaging device according to the present invention.

FIGS. 5A and 5B are schematic diagrams illustrating a configuration of a conventional solid-state imaging device.

FIG. 6 is a schematic diagram showing read and transfer operations in a conventional solid-state imaging device.

FIG. 7 is a potential distribution diagram showing a state of signal transfer in a vertical charge transfer unit of a conventional solid-state imaging device.

8A and 8B are potential distribution diagrams in a shift register of another conventional solid-state imaging device.

FIG. 9 is a circuit diagram showing a driving circuit of the solid-state imaging device according to the present invention.

FIG. 10 is a diagram showing a waveform of a pulse signal used in the solid-state imaging device according to the present invention.

FIG. 11 is a diagram showing a four-phase pulse signal used for the solid-state imaging device according to the present invention.

FIG. 12 is a diagram showing a circuit configuration of an electrode of a vertical charge transfer unit according to the present invention.

FIG. 13 is a diagram showing a waveform of a drive signal generated by a drive circuit of the solid-state imaging device according to the present invention.

[Explanation of symbols]

 1 pixel 2 vertical charge transfer section 3 horizontal charge transfer section 4 output section 5 drive circuit

Claims (6)

(57) [Claims] 1. A pixel portion including n pixels that perform photoelectric conversion and charge storage arranged in a first direction, and are connected to the pixel portion and read out from each of the pixels arranged in the pixel portion. Charge transfer means for transferring the signal in the first direction, connected to one end of the first charge transfer means, for receiving a signal transferred by the first charge transfer means, Charge transfer means for transferring the signal in a second direction; and a signal connected to one end of the second charge transfer means for receiving a signal transferred by the second charge transfer means; the provided output means for outputting to an external device into a video signal, the n-number of pixels, the n-th from the first pixel (i = 1)
Eye pixel (i = n), wherein the first pixel is the second pixel
Is disposed at the position closest to the charge transfer means of
The n-th pixel is located farthest from the second charge transfer means.
, And the first charge transfer means includes a first bit portion (i =
1) to the n-th bit part (i = n),
The second bit portion is located closest to the second charge transfer means.
And the n-th bit portion is the second power supply.
Is located farthest from the load transfer means, a method of driving the solid-state imaging device, (1) the first of the n pixels arranged in the pixel portion
From the pixel (i = 1) of the first charge transfer means.
Reading k bits from the first bit portion (i = 1) over the k bits; (2) reading the read signals corresponding to k bits of the first charge transfer means during one horizontal blanking period The first
(3) transferring a signal corresponding to k bits of the read first charge transfer means by (k-1) bits to the second charge
After shifting toward the transfer means, the signal from the (i + 1) -th pixel of the n pixels arranged in the pixel portion is transferred to the (i + 1) -th bit of the first charge transfer means. (4) Steps (2) to (3) are read from i = 1 to i = n−
And (5) repeating the step (2) after the n-th pixel farthest from the second charge transfer means has been read out , where k is A method for driving a solid-state imaging device, wherein the integer is 2 or more and an integer smaller than n . 2. The method according to claim 1, wherein the transfer step (2) comprises: transmitting the signal corresponding to k bits of the first charge transfer means to (k-
p) dividing a first signal portion corresponding to bits and a second signal portion corresponding to p bits, and dividing the first signal portion and the second signal portion during one horizontal blanking period. Transferring in one direction, p
The method according to claim 1, wherein is an integer satisfying 1 ≦ p <k. 3. The pixel having a first pixel portion and a second pixel portion, wherein the signal is a sum of a signal from the first pixel portion and a signal from the second pixel portion. Item 6. A method for driving a solid-state imaging device according to item 1. 4. A pixel portion including n pixels that perform photoelectric conversion and charge storage arranged in a first direction, and are connected to the pixel portion and read out from each of the pixels arranged in the pixel portion. Charge transfer means for transferring the signal in the first direction, connected to one end of the first charge transfer means, for receiving a signal transferred by the first charge transfer means, Charge transfer means for transferring the signal in a second direction, connected to one end of the second charge transfer means, receiving a signal transferred by the second charge transfer means, and receiving the received signal. output means for outputting to an external device into a video signal, a driving means for driving the charge transfer means of said first, said n pixels, the n-th from the first pixel (i = 1)
Eye pixel (i = n), wherein the first pixel is the second pixel
Is disposed at the position closest to the charge transfer means of
The n-th pixel is located farthest from the second charge transfer means.
, And the first charge transfer means includes a first bit portion (i =
1) to the n-th bit part (i = n),
The second bit portion is located closest to the second charge transfer means.
And the n-th bit portion is the second power supply.
Is located farthest from the load transfer means, a solid-state imaging device, said drive means (1) 1st of n pixels arranged in the pixel portion
From the pixel (i = 1) of the first charge transfer means.
K bits are read from the first bit portion (i = 1) , and (2) the read signal corresponding to k bits of the first charge transfer means is read out during one horizontal blanking period. First
(3) A signal corresponding to k bits of the read first charge transfer means is transferred by (k-1) bits to the second charge.
After shifting towards the transfer means, it is arranged in the pixel portion
The out of the n pieces of pixels (i + 1) -th read over k bit minutes signals from the pixels from the (i + 1) th bit <br/> bets portion of the charge transfer means of the first, (4 ) Steps (2) to (3) are performed from i = 1 to i = n−
Repeated for 1, (5) after the n-th pixel farthest from the charge transfer unit of the second is read, generates a plurality of driving signals for repeating said steps (2) , K is smaller than n
A solid-state imaging device, which is an integer of 2 or more . 5. The signal corresponding to k bits of the first charge transfer means in the step (2) is (k−p)
The first signal portion corresponding to the bits and the second signal portion corresponding to the p bits are divided, and the first signal portion and the second signal portion are transferred in the first direction during one horizontal blanking period. The solid-state imaging device according to claim 4, wherein p is an integer satisfying 1 ≦ p <k. 6. Each of the pixels has a first pixel portion and a second pixel portion, and the signal is a sum of a signal from the first pixel portion and a signal from the second pixel portion. The solid-state imaging device according to claim 4.