JP2908513B2 - Inspection method of variable capacitance element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to an assembly pairing (Pairin) of a variable capacitance element.
g) The method for inspecting a variable capacitance element suitable for performing with high efficiency and high yield, in particular, divides a scribe line (Scribe Line) formed on a semiconductor wafer (Wafer) (Bra).
Direct Pairing System, in which semiconductor chips (Chip) obtained by performing a king), ie, variable capacitance elements, are sequentially put into an assembling apparatus to perform pairing.
Alternatively, it is suitable for a probe test of a semiconductor wafer for a semiconductor device formed by incorporating a plurality of elements in one package.

(Prior Art) In a semiconductor device manufacturing process, a so-called die sorter (Di-
e Sorter) A test process is performed, and as a part of this process, a probe test is generally performed. In a die sorter test for an integrated circuit, a method using a so-called probe card (Card) is adopted, whereas a slightly different method is adopted for an individual semiconductor element. That is, for example, the base of a transistor (Transister) (Bas
e) and each probe needle for the emitter
It is characterized in that it is provided on a probe arm (Probe Arm) that can move in two-dimensional directions like a Y-table. However, even in the case of an individual semiconductor element having a high degree of integration, that is, an element having a large number of electrodes, a probe card is used similarly to the integrated circuit element.

In the case of a variable capacitance element, which is a type of an individual semiconductor, a step of slightly shaving the back surface of a silicon (Silicon) substrate by, for example, mechanical means to form a back electrode is performed. It is customary. In addition, the variable capacitance element undergoing this process is subjected to a probe test before a breaking step in which a semiconductor chip (Chip) built on a silicon substrate is divided along a so-called scribe line, thereby achieving material efficiency and production. To improve the performance.

In addition, the probe test related to the capacitance of the variable capacitance element
They are selected non-defective from the upper and lower limit (Limit) C _max capacity standards to C _min by the electrical characteristics standards specified bias (Bias). Incidentally, Japanese Patent Application Laid-Open No. Sho 59-147497 discloses a taping body for a semiconductor component. In this technique, when the number of semiconductor components for assembling a tuner is N, for example, as one circuit or device, each of N successive (n + N-1) th N characteristics sequentially arranged by taping is used. For example, the cv characteristic of the variable capacitance element is within a predetermined characteristic deviation value, and (n +
The taping is performed so that the characteristics of each of the N consecutive semiconductor components from the 1) th to the (n + 1) + N-1 = (n + N) th are also within the above-mentioned predetermined characteristic deviation value. Specifically, when the circuit or device to be assembled is a television tuner, the number N of variable capacitance elements used in one kit is N = 4 to 8, and the capacitance deviation is 2.5% to 3.5%. It must be within the value. At this time,
Adjacent taping elements are arranged with variable capacitance elements having characteristics within this 2.5% to 3.5% capacitance deviation value, and even if N adjacent parts are taken out, each has a capacitance deviation of 2.5% to 3.5%. A method of selecting a value within the value is adopted.

(Problems to be Solved by the Invention) When using a system in which non-defective variable capacitance elements that have undergone such a probe test are sequentially put into an assembling apparatus and pairing is directly performed, or when a plurality of elements are integrated in one package In addition, element characteristics adjacent to each other are not always uniform, and a matching failure has occurred. Generally, this defect increases as the number of elements to be paired increases. Matching is M = (C
_max −C _min ) / C _min × 100% is defined as C _max , C
_min is the maximum and minimum element capacity in the continuous guarantee pair.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and reduces a pairing defect generated due to a variation in characteristics of a semiconductor chip divided along a scribe line formed on a semiconductor wafer, thereby reducing the yield of an assembly process. The purpose is to improve.

[Configuration of the invention]

(Means for Solving the Problem) In the variable capacitance element group, in order to remove an element whose capacitance value is far apart, the element capacitance C _{i to} be inspected is equal to n average capacitances C just before inspection. and to follow the logical expression _{C / K ≦ C i ≦ CK} ... it is within the width K, the inspection device capacitance C _i
Of the variable capacitance element according to the present invention is that a probe test is performed by providing a limit in accordance with a logical expression C _im / L ≦ C _i ≦ C _im L. There is a characteristic of the inspection method.

(Operation) The probe test is performed before the breaking step of dividing into the respective variable capacitance elements, that is, in the state of the semiconductor wafer, in consideration of the defect due to the cutting step of the back surface of the semiconductor wafer which is inevitable for the back electrode of the variable capacitance element. Will be

FIG. 1 shows the capacitance characteristics of the variable capacitance elements built in the semiconductor wafer by contour lines, and FIG. 2 shows the results of arranging the capacitance characteristic values of the semiconductor wafer in a horizontal line. As is clear from these figures, among a large number of variable capacitance elements built in the semiconductor wafer, the value of the variable capacitance element located at the peripheral part is larger than that at the central part. The probe test for such a variable capacitance element employs a method of measuring a plurality of locations in the diameter direction of the semiconductor wafer with a probe needle. Therefore, the point a in FIG. 2 is substantially at the center.

On the other hand, the variable capacitance element is used for TV in addition to the AM and FM devices, and the capacitance characteristic required for the AM and FM variable capacitance element is 2 V, either 10 V or 14 V, 20 V , 25V
For special devices, a probe test is performed by applying a bias of 7 V and 28 V (Bias). For example, when applying a 10V bias, 10V
A 2 to 24% element is selected, and 2% of the variable element for pairing is extracted.

From this viewpoint, in order to smoothly perform the probe test, the device capacitance under test C _i is n
(C) / K ≦ C _i ≦ CK, and a restriction according to (C _im ) / L ≦ C _i ≦ CL is added to the capacitance C _im before m. K and L are constants for eliminating variations and capacitance. Here C _i is the test element amount, C is the average device capacitance, C _im is m Ke previous device capacitance than C _i of N Ke, K, L are determined standard value.

(Example) January 23, 1990 based on the present invention and the so-called "first-to-last request"
The "Assembly method of semiconductor device" filed as Japanese Patent Application No. 2-013312 is also used for the method of inspecting a variable capacitance element according to the present invention, that is, a direct pairing system. It consists in a series of machines. Here, the assembling method will be briefly described. Among the assembling means for assembling the variable capacitance element, those having a large difference in performance are arranged with a transport line (Line) interposed therebetween to adjust the entire line. In addition, there is a buffer between each assembly means.
Trouble that occurs in assembly means by installing functions (Troubl
e) Help prevent and also increase the number of transport lines. Furthermore, in order to sort by the type of the semiconductor element, two types, one in which a mark such as a hole, that is, a marker is provided, and the other in which no marker is provided are formed in the sealing resin layer constituting the envelope, and the time for putting it into the assembling means is determined. Adopt the shifting method. As a result,
It is possible to switch from lot (Lot) unit processing of work to continuous processing of single items.

The equipment used for the assembling means is Die Bonde
r) process, wire bonding (Wire Bonding) process, resin sealing process, deflash (Difrash) process,
Solder exterior finishing process, mark process, lead bend process, test process, and taping process are the targets. Each of these steps is performed by a dedicated assembling apparatus, but in the arrangement, a die bonder, a wire bonder, a mark machine, and a single line for transporting the variable capacitance element are sandwiched.
A lead bending machine, a tester, and a taping machine are installed, and each process is performed. The indexes of the resin encapsulation process, deflash process, and solder exterior finishing process are about half that of the other processes, and have different capacities. Is required. Therefore, a buffer function is provided between such assembling means to prepare for an unexpected accident or maintenance of an index of a series of machines due to a difference in performance.

Further, between the processes having different indexes, specifically, between the wire bonding process and the mark process, and between the mark process and the lead bending process, a robot (Robot) is installed to directly connect each assembling means and separately install a sensor (Senso).
The marker is discriminated by interlocking with r), and the envelope for each type is sorted. As described above, between processes having different indexes, a stocker is installed and a buffer function for adjusting the quantity required for the next process is installed. This plays a role of maintaining the function as a series machine by stocking the variable capacitance elements flowing in each step even when a trouble occurs in a part of the line. In such a series of machines, it is not limited to a single line for variable capacity, and for example, two lines may be installed. In this case, a line other than a resin sealing device, a deflash man, a solder armoring machine is used. Can be installed on both sides and between the lines, so a total of two units can be installed. Since it is now possible to process single items from such lot-by-lot processing, labor savings of about 80% can be achieved. In addition, equipment costs for small to medium production scale (up to 6 million pieces / month) Approximately 90% of conventional time and lead time can be saved.

In the direct pairing system applied to the method for inspecting a variable capacitance element according to the present invention, the above-described series machine is used, and as described above, about 2% of the variable capacitance element for pairing is selected by the inspection process. In addition, a variable capacitance element having a capacitance value within a predetermined deviation value is provided in an action column in order to make N characteristics from the (n + 1) th to (n + 1) + N-1th also equal to the predetermined capacitance value. As shown, it is necessary to select elements having characteristic values that are far apart.

By the way, the approximate capacitance value of the plurality of variable capacitance elements formed on the wafer tends to be lower at the center portion of the wafer and higher at the peripheral portion as shown in FIG. Revealed in the figure. In other words, there is a variable capacitance element having a far-off value, and there is a variable capacitance element whose absolute value is 0.0K but must be excluded from the matching of pairing. Therefore, probe test software (Soft W
aire) was prepared and the sorting process was performed.

That is, in this capacitance measurement, the deviation of the capacitance value is examined to determine whether or not there is a sudden change as shown in the continuity of FIG. For example, it is electrically connected to the capacitance measurement process. Of course, differences depending on the type and model are adjusted here.

In an item to adjust whether a value close to what% ± respect C _i, are determined by whether dividing or multiplying by as the K example 1.01. In contrast, determining the one change before or one after the C _i to either multiplying or dividing by L. Yuunareba K as standard width is compared to the average value C _x and m Ke previous value C _im circadian inspection capacity n Ke for inspection capacitance C, was installed L. Therefore, the variable capacitance element having a distant capacitance value is selected in, and the inclination of the capacitance value sequence is restricted even if the variable capacitance element passes in the previous section.
As described above, a probe test software in which a test is added to a normal probe test is added to provide a variable capacitance element inspection method. While the average value of n Ke by C in this example, changing the reference value even median C _m even most Hakado value C,
It is added that the value is in the range of the separated value in the method of the present invention.

〔The invention's effect〕

According to the method of inspecting a variable element according to the present invention, the matching failure rate is reduced by half to 3% as compared with the conventional 6%, and the productivity is extremely improved. Furthermore, the M / C operation rate of the direct pairing system has been improved by 5% compared to the conventional system.

[Brief description of the drawings]

FIG. 1 is a capacitance contour diagram of a wafer, FIG. 2 is a diagram illustrating a capacitance transition in which capacitances of variable capacitance elements formed on a wafer are arranged in a horizontal line, and FIG. 3 is a diagram illustrating a flow of a probe test in the present invention. .

Continued on the front page (72) Inventor Kazu Yasuhara 50 Himeji Plant, Yobe-ku, Himeji City, Hyogo Prefecture Inside the Toshiba Himeji Plant Co., Ltd. (56) reference Patent Sho 63-32944 (JP, a) JP Akira 62-39779 (JP, a) JP Akira 53-108782 (JP, a) (58 ) investigated the field (Int.Cl. ⁶ , DB name) H01L 21/66 G01R 31/26 H01L 29/93

Claims (1)

(57) [Claims] Among 1. A variable capacitance element group, for removing element capacitance value was Tobihanare, within a width K in the inspection device capacitance C _i is for n immediately before already inspected average capacitance C and that according to some logical expression _{C / K ≦ C i ≦ CK} ..., the inspected element capacitance C _i
A variable capacitance element inspection characterized by providing a limit according to a logical expression C _im / L ≦ C _i ≦ C _im L... Method.