JP2908646B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to, for example, a dynamic random access memory.
The present invention relates to a semiconductor device such as an access memory (hereinafter, referred to as a DRAM) and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 14 is a sectional structural view showing a DRAM having a stacked type capacitor as a conventional semiconductor device.

In FIG. 1, reference numeral 1 denotes a P-type single crystal silicon substrate having a crystal orientation of ( 100 ) , and 2 denotes an isolation oxide film (for element isolation) formed in a predetermined region on a main surface of the single crystal silicon substrate 1. A thick silicon oxide film), 4a and 4b, a pair of n ⁺ impurity implantation layers (source / drain regions) formed so as to sandwich the channel region 3 at predetermined intervals in a region surrounded by the isolation oxide film 2; 6 is the channel area 3
A gate electrode 7 formed thereon via a gate oxide film 5;
Is formed so as to cover the entire surface, has an interlayer insulating film having contact holes 8a and 8b on n ⁺ impurity implantation layers 4a and 4b, and 10 is connected to n ⁺ impurity implantation layer 4a and extends on interlayer insulation film 7. This is a capacitor lower electrode made of low-resistance polycrystalline silicon formed as described above.

Reference numeral 11 denotes a single-layer film such as a thermal oxide film formed on the capacitor lower electrode 10, a multilayer film such as a triple structure of a silicon oxide film / silicon nitride film / silicon oxide film, or a single-layer film of a high dielectric film. T _{a 2} O ₅ and the like capacitor dielectric film, 12 is a capacitor upper electrode formed of a low-resistance polycrystalline silicon formed on the capacitor dielectric film 11, 1
3 is formed so as to cover the entire surface, and the n ⁺ impurity implantation layer 4b is formed.
Above the interlayer insulating film having an opening 14 of, 15a is n ⁺
The interlayer insulating film 13 electrically connected to the impurity implantation layer 4b
Polycrystalline silicon film formed so as to extend above, 15
b denotes WS _i2 formed on the polycrystalline silicon film 15a.
And 16 is the silicide film 1
An interlayer insulating film 17 formed on 5b is an aluminum wiring formed on the interlayer insulating film 16 at a predetermined interval so as to correspond to the gate electrode 6.

Here, a pair of n ⁺ impurity implanted layers 4a and 4b and a gate electrode 6 constitute a switching MOS transistor, and a capacitor lower electrode 10, a capacitor dielectric film 11, and a capacitor upper electrode 12 Constitute a stacked type capacitor for storing charges corresponding to the data signal, and the polycrystalline silicon 15a and the silicide film 15b constitute the bit line 15.

FIGS. 15 to 23 are sectional structural views showing the steps of manufacturing the dynamic random access memory shown in FIG. Next, a method of manufacturing the DRAM will be described with reference to FIGS. First, as shown in FIG. 15, a LOCOS (Loca ) is formed in a predetermined region on the main surface of a P-type single crystal silicon substrate 1 having a crystal orientation of ( 100 ).
An isolation oxide film (thick silicon oxide film) 2 for element isolation is formed by using an oxidation of silicon (lOxidation of Silicon) method.

Next, as shown in FIG. 16, a gate oxide film layer (not shown) is formed on the entire surface by a thermal oxidation method, and a CVD (Chemical Vap) is formed on the gate oxide film layer.
A low-resistance polycrystalline silicon layer (not shown) is deposited using an or deposition method. Then, the gate oxide film 5 and the gate electrode 6 are patterned by lithography and dry etching.
To form

[0008] Next, as shown in FIG.
As a mask, by arsenic (As) is ion-implanted under the conditions of ^{50keV, 3 × 10 1 3 /} cm 2, 1
A pair of n ⁺ impurity implanted layers (source / drain regions) 4a and 4b are formed in a self-aligned manner. Thereafter, heat treatment is performed to electrically activate n ⁺ impurity implanted layers 4a and 4b.

Next, as shown in FIG.
The interlayer insulating film 7 is formed by using the method. Next, as shown in FIG. 19, a contact hole 8a is formed in a region of the interlayer insulating film 7 located on the n ⁺ impurity implantation layer 4a by using a lithography technique and a dry etching technique. Due to the formation of the contact hole 8a, a part of the surface of the n ⁺ impurity implantation layer 4a is exposed to the air, so that a natural oxide film 9 of, for example, about 10 angstroms is formed.

Next, as shown in FIG. 20, a low-resistance polycrystalline silicon layer (not shown) is formed by using a CVD method, and then patterned by using a lithography technique and a dry etching technique to form a contact. Hall 8
A capacitor lower electrode 10 is formed in a portion a so as to extend to a predetermined region on the interlayer insulating film 7. Next, as shown in FIG. 21, a capacitor dielectric film 11 is formed on the capacitor lower electrode 10. After forming a low-resistance polycrystalline silicon film layer (not shown) using a CVD method, patterning is performed using a lithography technique and a dry etching technique to form a capacitor upper electrode 12 on the capacitor dielectric film 11. I do. Then, an interlayer insulating film 13 is formed on the entire surface by using the CVD method.

Next, as shown in FIG. 22, an interlayer insulating film 1 is formed by using a lithography technique and a dry etching technique.
An opening 14 and a contact hole 8b are formed in a region penetrating through 3 and 7 and located above the n ⁺ impurity implantation layer 4b. Thereby, a part of n ⁺ impurity implantation layer 4b is exposed. A low-resistance polycrystalline silicon film 15a is formed so as to be electrically connected to n ⁺ impurity implantation layer 4b exposed by using the CVD method and to extend on interlayer insulating film 13.
A silicide film 15b such as WS _i2 is formed on the polycrystalline silicon film 15a by using a sputtering method. Then
The data line 15 is formed by patterning the single crystal silicon film 15a and the silicide film 15b by using a lithography technique and a dry etching technique. Then, an interlayer insulating film 16 is formed on the entire surface of the data line 15 by using the CVD method.
To form

Finally, as shown in FIG. 23, aluminum wirings 17 are formed at predetermined intervals. Thus, the conventional DRAM has been formed.

[0013]

Since the conventional semiconductor device is manufactured in the above-described steps and configured as described above, as shown in FIG. 14, the capacitor lower electrode 10 and the n ⁺ impurity implantation layer 4a are formed. The contact resistance between the capacitor lower electrode 10 and the n ⁺ impurity implanted layer is increased due to the presence of the native oxide film 9 on the contact surface of the semiconductor device. However, there was a problem that writing failure occurred.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and a semiconductor device and a method of manufacturing the same capable of lowering the contact resistance between a capacitor lower electrode and an impurity-implanted layer and particularly preventing writing failure. The purpose is to obtain.

[0015]

A semiconductor device according to the present invention has a main surface, a first conductivity type semiconductor substrate having a slope at a predetermined portion of the main surface, and a semiconductor device having a main surface having a main surface. First and second impurity regions of the second conductivity type formed at predetermined intervals so as to sandwich the channel region;
A gate electrode formed on the channel region via a gate oxide film, and electrically connected to the first impurity region on an inclined surface of the semiconductor substrate, and a first impurity on a main surface of the semiconductor substrate. And a capacitor lower electrode that is not electrically connected to the region. Further, the inclined surface is an inclined surface constituted by a crystal plane having a higher density than the main surface of the semiconductor substrate .

Further, in the method of manufacturing a semiconductor device according to the present invention, the semiconductor device of the first conductivity type may be provided on a predetermined portion of a main surface of a semiconductor substrate.
Forming an inclined surface constituted by a crystal plane having a higher density than the main surface of the semiconductor substrate ; forming a gate electrode on the main surface of the semiconductor substrate via a gate oxide film; Is used as a mask to ion-implant impurities into the semiconductor substrate.
Forming an insulating film so as to have an opening in the first impurity region and on an inclined surface of the semiconductor substrate; and forming a first impurity in the opening in the first impurity region. Forming a capacitor lower electrode on the impurity region.

[0017]

In the semiconductor device according to the present invention, an inclined surface is provided at a predetermined portion of the main surface of the semiconductor substrate of the first conductivity type.
The capacitor lower electrode is electrically connected to the first impurity region on the inclined surface of the semiconductor substrate. Thus, the thickness of the natural oxide film formed on the first impurity region is reduced.

In the method of manufacturing a semiconductor device according to the present invention, an inclined surface is formed on a predetermined portion of a main surface of a semiconductor substrate of a first conductivity type, and a gate oxide film is formed on the main surface of the semiconductor substrate via a gate oxide film. A gate electrode is formed, and impurities are ion-implanted into the semiconductor substrate using the gate electrode as a mask to form first and second impurity regions of the second conductivity type. An insulating film is formed so as to have an opening on the inclined surface of the substrate, a capacitor lower electrode is formed on the first impurity region in the opening, and the growth of a natural oxide film after forming a contact hole is suppressed.

[0019]

[Embodiment 1] In the following, the drawings will be described by taking an example in which one embodiment of the present invention is applied to a DRAM. FIG. 1 shows a DRA having a stacked type capacitor according to an embodiment of the present invention.
FIG. 15 is a cross-sectional structural view of M, in which parts corresponding to those in FIG. 14 are denoted by the same reference numerals, and detailed description thereof will be omitted. In the figure, reference numeral 20 denotes a P-type single crystal silicon substrate having a ( 100 ) crystal orientation as a first conductivity type semiconductor substrate, and 20a denotes an azimuth plane formed on a predetermined portion of a main surface of the single crystal silicon substrate 20. ( 111 ) inclined surface, 21a, 21b
Is a pair of n ⁺ impurity implantation layers (source / drain regions) as first and second impurity regions formed so as to sandwich the channel region 3, and 22 a and 22 b are on the n ⁺ impurity implantation layers 21 a and 21 b The contact holes 24 formed respectively are connected to the n ⁺ impurity implantation layer 21a, and the capacitor lower electrode made of low-resistance polycrystalline silicon formed so as to extend on the interlayer insulating film 7, and 25 is the capacitor lower electrode 24. A single-layer film such as a thermal oxide film such as a thermal oxide film formed thereon, a multilayer film such as a triple structure of a silicon oxide film / silicon nitride film / silicon oxide film, or a single-layer film having a high dielectric constant _{Ta 2} O ₅ 26, a capacitor dielectric film made of
Is a capacitor upper electrode made of low-resistance polycrystalline silicon formed on the capacitor dielectric film 25.

Here, a pair of n ⁺ impurity implanted layers 21a and 21b and the gate electrode 6 form a switching MOS.
A transistor is formed, and the capacitor lower electrode 24, the capacitor dielectric film 25, and the capacitor upper electrode 26 form a stacked type capacitor for storing charges corresponding to the data signal.

FIGS. 2 to 13 are cross-sectional views showing the steps of manufacturing the DRAM shown in FIG. Next, a method of manufacturing the DRAM will be described with reference to FIGS. First, as shown in FIG. 2, an oxide film (not shown) is formed on the entire main surface of a P-type single-crystal silicon substrate 1 having a crystal orientation of ( 100 ) , and is formed by using a lithography technique and a dry etching technique. Oxide film 2 by patterning
7 is formed. Next, as shown in FIG. 3, the mask oxide film 27, the silicon substrate 1 is etched by U E Tsu preparative etching having anisotropy with respect to the crystal surface due to aqueous potassium hydroxide solution, whereby a predetermined portion of the main surface A P-type single crystal silicon substrate 20 having an inclined surface 20a having a plane orientation of ( 111 ) is formed.

Next, as shown in FIG. 4, to remove the oxide film 27 by U E Tsu preparative etching such as hydrogen fluoride solution. Next, as shown in FIG. 5, a LOCOS (Local) is formed in a predetermined region on the main surface of the single crystal silicon substrate 20.
Isolation oxide film (thick silicon oxide film) for element isolation using Oxidation of Silicon method
Form 2 This isolation oxide film 2 is lower than the isolation oxide film 2 in FIG. 15 from the main surface of the single crystal silicon substrate 20. Next, as shown in FIG. 6, a gate oxide film layer (not shown) is formed on the entire surface using a thermal oxidation method, and a low-resistance polycrystalline silicon layer (not shown) is formed on the gate oxide film layer using a CVD method. (Not shown). Then, a gate oxide film 5 and a gate electrode 6 are formed by performing patterning using a lithography technique and a dry etching technique.

Next, as shown in FIG. 7, the gate electrode 6 as a ^{mask, 50keV, 3 × 10 1 3} / cm arsenic (As) is ion-implanted under the conditions of ^2, of which the pair n ⁺ Impurity injection layer (source region / drain region) 21a
And 21b are formed in a self-aligned manner. N ⁺ impurity implantation layer 21a is formed near the lower portion of inclined surface 20a. Thereafter, a heat treatment is performed so that the n ⁺ impurity implantation layer 21a is formed.
And 21b are electrically activated. Next, as shown in FIG. 8, an interlayer insulating film 7 is formed on the entire surface by using a CVD method.

Next, as shown in FIG. 9, a lithography technique and a dry etching technique are applied to a region of the interlayer insulating film 7 located on the inclined surface 20a forming a part of the surface of the n ⁺ impurity implantation layer 21a. The contact hole 22a is formed by using this. The contact hole 22a may be larger or smaller than the inclined surface 20a. Due to the formation of the contact hole 22a, a part of the surface of the n ⁺ impurity implantation layer 21a, that is, the inclined surface 20a is exposed to the atmosphere, whereby a natural oxide film 23 is formed on the inclined surface 20a. However, in the region where the natural oxide film 23 is formed, the azimuthal plane of the single crystal silicon substrate 20 is ( 11).
1 ) is the inclined surface 20a, and since the ( 111 ) plane has a higher silicon surface density than the ( 100 ) plane and does not easily oxidize, the growth of the natural oxide film 23 is ( 10).
0 ) plane, the thickness of the native oxide film 23 is reduced. The thickness of the natural oxide film 23 depends on the conditions such as the time left from the formation of the contact hole 22a to the formation of the capacitor lower electrode 24, but it is at least about 5 angstroms that does not cause writing failure. It is as follows.

Next, as shown in FIG. 10, after a low-resistance polycrystalline silicon layer (not shown) is formed by using the CVD method, patterning is performed by using a lithography technique and a dry etching technique. A capacitor lower electrode 24 is formed in the contact hole 22a so as to extend to a predetermined region on the interlayer insulating film 7.

Next, as shown in FIG. 11, a capacitor dielectric film 25 is formed on the capacitor lower electrode 24. C
Low resistance polycrystalline silicon film layer using VD method (not shown)
Is formed, patterning is performed using a lithography technique and a dry etching technique to form a capacitor upper electrode 26 on the capacitor dielectric side film 25. The capacitor upper electrode 26, it can be seen that become a separation oxide film 2 only the amount that is formed at a position lower Tan Taira 5. Then, an interlayer insulating film 13 is formed on the entire surface by using the CVD method.

Next, as shown in FIG. 12, an interlayer insulating film 1 is formed by using a lithography technique and a dry etching technique.
3 and 7 in the region located above the through to n ⁺ impurity-implanted layer 21b of the openings 14 and the contact hole 22 b <br/> form. Thereby, a part of n ⁺ impurity implantation layer 21b is exposed. The interlayer insulating film 13 is electrically connected to the n ⁺ impurity implantation layer 21b exposed using the CVD method.
A low-resistance polycrystalline silicon film 15a is formed to extend upward. A silicide film 15b such as WS _i2 is formed on the polycrystalline silicon film 15a by using a sputtering method.
Next, the polycrystalline silicon film 15a and the silicide film 15b are formed by using a lithography technique and a dry etching technique.
Is patterned to form the data line 15. Then, the interlayer insulating film 1 is formed on the entire surface of the data line 15 by using the CVD method.
6 is formed. Finally, as shown in FIG. 13, aluminum wirings 17 are formed at predetermined intervals.

As described above, in this embodiment, when the contact hole 22a is formed, the n ⁺
The thickness of the natural oxide film 23 formed by exposing a part of the surface of the substrate 1a to the atmosphere is
Since the azimuth plane is on the ( 111 ) inclined plane 20a, it becomes thin, and the contact resistance between the capacitor lower electrode 24 and the n ⁺ impurity implantation layer 21a can be reduced.

Embodiment 2 FIG. In the above embodiment has been described what if the crystal orientation of the P-type monocrystalline silicon substrate of (100) crystal orientation is (1
00 ) may be used, and the same effects as in the above embodiment can be obtained.

[0030]

As described above, according to the present invention, the semiconductor device has a main surface, and the main surface of the semiconductor substrate is provided on a predetermined portion of the main surface.
A semiconductor substrate of a first conductivity type having an inclined surface having a higher density than the surface; and first and second semiconductor substrates of a second conductivity type formed at predetermined intervals on a main surface of the semiconductor substrate so as to sandwich a channel region. An impurity region, a gate electrode formed on the channel region via a gate oxide film, and electrically connected to the first impurity region on an inclined surface of the semiconductor substrate. A capacitor lower electrode that is not electrically connected to the first impurity region; and the inclined surface is closer than a main surface of the semiconductor substrate.
Is also an inclined plane composed of high-density crystal planes,
There is an effect that the contact resistance between the capacitor lower electrode and the impurity-implanted layer can be reduced, and in particular, writing defects can be prevented.

[0031]

Further, according to the present invention, the main surface of the semiconductor substrate to a predetermined portion of the main surface of a first conductivity type semiconductor substrate
Forming a higher-density inclined surface, forming a gate electrode on the main surface of the semiconductor substrate via a gate oxide film, and ion-implanting impurities into the semiconductor substrate using the gate electrode as a mask. Thereby forming the first and second impurity regions of the second conductivity type, and forming an insulating film so as to have an opening in the first impurity region and on the inclined surface of the semiconductor substrate. And forming a capacitor lower electrode on the first impurity region in the opening, thereby suppressing the growth of the native oxide film after the formation of the contact hole. This has the effect that the contact resistance can be reduced, and in particular, writing defects can be prevented.

[Brief description of the drawings]

FIG. 1 is a sectional structural view showing one embodiment of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional structure diagram for explaining a manufacturing process of one embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional structure diagram for explaining a manufacturing process of one embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional structure diagram for explaining a manufacturing process of one embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 5 is a cross-sectional structure diagram for explaining a manufacturing process of one embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a sectional structural view for explaining a manufacturing process of one embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 7 is a sectional structural view for explaining a manufacturing process of one embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 8 is a cross-sectional structure diagram for explaining a manufacturing process of one embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a cross-sectional structure diagram for explaining a manufacturing process of one embodiment of a method of manufacturing a semiconductor device according to the present invention.

10 is a sectional view for explaining a manufacturing process of an embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 11 is a sectional structural view for explaining a manufacturing process of one embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 12 is a sectional structural view for explaining a manufacturing process of one embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 13 is a sectional structural view for explaining a manufacturing process of one embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 14 is a sectional structural view showing one embodiment of a conventional semiconductor device.

FIG. 15 is a cross-sectional structure diagram for explaining a manufacturing process of one embodiment of a conventional method for manufacturing a semiconductor device.

FIG. 16 is a cross-sectional structure diagram for explaining a manufacturing process of an embodiment of a conventional method for manufacturing a semiconductor device.

FIG. 17 is a cross-sectional structure diagram for explaining a manufacturing process of one embodiment of a conventional method for manufacturing a semiconductor device.

FIG. 18 is a cross-sectional structure diagram for explaining a manufacturing process of one embodiment of a conventional method for manufacturing a semiconductor device.

FIG. 19 is a cross-sectional structure diagram for explaining a manufacturing process in one embodiment of a conventional method for manufacturing a semiconductor device.

FIG. 20 is a cross-sectional structure diagram for explaining a manufacturing process of one embodiment of a conventional method for manufacturing a semiconductor device.

FIG. 21 is a sectional structural view for explaining a manufacturing process of an embodiment of a conventional semiconductor device manufacturing method.

FIG. 22 is a cross-sectional structure diagram for explaining a manufacturing process in one embodiment of a conventional method for manufacturing a semiconductor device.

FIG. 23 is a cross-sectional structure diagram for explaining a manufacturing process in one embodiment of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 3 channel region 5 gate oxide film 6 gate electrode 7, 13 interlayer insulating film 20 p-type single crystal silicon substrate 20a inclined surface 21a, 21b n ⁺ impurity implantation layer 22a contact hole 23 natural oxide film 24 capacitor lower electrode

Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (3)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type having a main surface and an inclined surface at a predetermined portion of the main surface, and formed on the main surface of the semiconductor substrate at a predetermined interval so as to sandwich a channel region. The first and second impurity regions of the second conductivity type, a gate electrode formed on the channel region via a gate oxide film, and electrically connecting the first impurity region to the inclined surface of the semiconductor substrate. And a capacitor lower electrode electrically connected to the first impurity region on a main surface of the semiconductor substrate. 2. A step of forming an inclined surface constituted by a crystal plane having a higher density than the main surface of the semiconductor substrate on a predetermined portion of the main surface of the semiconductor substrate of the first conductivity type; Forming a gate electrode thereon with a gate oxide film interposed therebetween, and ion-implanting impurities into the semiconductor substrate using the gate electrode as a mask, thereby forming first and second impurity regions of a second conductivity type. Forming an insulating film in the first impurity region so as to have an opening in the inclined surface of the semiconductor substrate; and forming a capacitor lower electrode on the first impurity region in the opening. Forming a semiconductor device. 3. The semiconductor device according to claim 1, wherein the inclined surface is closer to a main surface of the semiconductor substrate.
2. The semiconductor device according to claim 1, wherein the semiconductor device is an inclined surface formed of a high-density crystal plane.