JP2909095B2 - Video signal transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a processor that is an external device, for example, a video signal including a chrominance signal in a color difference line sequential mode output from a recording unit or the like of an electronic still camera. The present invention relates to a video signal transmission system that transmits a video signal to a recording device via a computer and records the video signal.

[Conventional technology]

2. Description of the Related Art In recent years, various electronic still cameras have been developed which record video signals electronically imaged using a solid-state imaging device such as a CCD on a recording medium such as an SVF (still video floppy disk). This type of camera generally forms about 50 recording tracks concentrically on the SVF and records one (one field) electronic still image (still video signal) for each recording track. It has become.

Recently, a system for transmitting a reproduced still video signal output from a recording unit of such an electronic still camera to a recorder via a processor and re-recording the video signal has been considered.
FIG. 14 is a circuit block diagram showing an example of the configuration.
In the figure, 1 is a processor, 2 is a recorder, and these processors 1 and recorder 2 are detachably connected by a cable 3 using a connector.

First, in the processor 1, a luminance signal Y + S and a chrominance signal RY / BY including a synchronizing signal output from an electronic still camera (not shown) are converted into digital signals by analog / digital converters (A / D) 11 and 12, respectively. After that, they are temporarily stored in the luminance memory 13 and the chrominance memory 14, respectively. These memories 13 and 14 are for performing dropout correction, skew correction, and the like on the luminance signal Y + S and the line-sequential chrominance signals RY / BY, and each control of writing and reading is performed by the memory. This is performed by the control circuit 15. The luminance signal Y + S and the chrominance signal R-Y / B-Y read from the memories 13 and 14, respectively.
Are digital-to-analog converters (D / A) 16,17
The signal is returned to an analog signal, and then transmitted to the recorder 2 via the cable 3.

On the other hand, in the recorder 2, the luminance signal Y + S and the chrominance signal RY / B transmitted from the processor 1 are transmitted.
−Y is modulated by modulators (MOD) 21 and 22, respectively.
The two are synthesized by the adder 23 and supplied to the recording head 24,
The recording is performed on the SVF 25 by the recording head 24. Reference numeral 26 denotes a spindle motor for driving the SVF 25 to rotate.

By the way, the current electronic still camera system uses SVF
For the purpose of reducing the storage capacity of the chrominance signal component with respect to the chrominance signal, it is specified by standards that the chrominance signal be constituted by a signal obtained by performing color difference line sequential processing. The color difference line sequentialization generally means that the color difference signals RY and BY are separated into a color difference signal RY and a color difference signal BY.
Are alternately output every one horizontal scanning period. The color difference line-sequentialized chrominance signal is
In the case of recording data in the horizontal blanking interval, it is necessary to provide a difference in the DC potential during the horizontal blanking period so that the two can be distinguished.

Therefore, in the conventional system, a step circuit 28 is provided in the recording machine 2 as shown in FIG. 14, and a step is provided in the chrominance signal by the step circuit 28. FIG. 15 shows an example of the configuration of the step circuit 28. Two power supplies for generating predetermined offset voltages V1 and V2 corresponding to the respective color difference signals RY and BY of the chrominance signals are shown in FIG. The offset voltage V1, V2 is selected by a changeover switch 28a, and the selected offset voltage V1, V2 is selected by a switch 28b.
By outputting V2 at a predetermined timing, the respective color difference signals RY and BY of the chrominance signals RY / BY are clamped by the offset voltages V1 and V2. The changeover of the changeover switch 28a is performed by the processor 1
This is performed by a line index signal LIND sent from the controller 3 via the cable 3. On / off of the switch 28b is performed by a clamp pulse CS output from the clamp pulse generation circuit 27. This clamp pulse CS is generated based on the vertical synchronization signal included in the luminance signal Y + S. FIG. 16 shows the operation of the step circuit 28 described above.

[Problems to be solved by the invention]

However, in such a conventional system, the index signal LIND necessary for selecting the offset voltages V1 and V2 in the step circuit 28 of the recording machine 2 is transmitted from the processor 1 to the cable 3
To transfer through. For this reason, the processor 1 and the recorder 2 are used to re-record the video as described above.
It is necessary to prepare a cable including at least three signal lines for this purpose, including the signal line for transmitting the line index signal LIND, for the purpose. Therefore, a connector for connecting a cable requires three terminals for this purpose. Therefore, there is a problem that the number of cables and connectors cannot be further reduced in order for the system to have a function for re-recording a video. In addition, if the number of contacts of the connector is increased by one, an extra force for inserting and removing the connector is required, which causes operational problems such as difficulty in attaching / detaching the connector, and also causes troubles such as poor contact. And reduced reliability.

Therefore, the present invention focuses on the above circumstances, eliminates the need for transmission of the line index, and thereby simplifies the connection configuration through the number of signal lines connecting two opposing systems,
Accordingly, it is an object to provide a video signal transmission system capable of improving operability and reliability.

[Means for solving the problem]

The present invention provides a system for transmitting a chrominance signal in a line-sequential manner from a first system to a second system, wherein the first system stores a luminance system memory storing a luminance signal including a synchronization signal, and the chrominance signal. Chrominance memories for storing chrominance signals, and readout control means for these memories. The readout control means sequentially reads chrominance signals as respective elements from the chrominance memory to form the line-sequential chrominance signals. And the synchronization signal in the luminance signal read from the luminance memory is read out so as to maintain a specific phase relationship, and the second system is provided with discriminating means. Each element in the chrominance signal is determined based on the synchronization signal contained in the luminance signal transmitted from the first system. So as to discriminate the order sequence,
This discrimination result is provided to, for example, a process for providing a step of a DC level for each element of the chrominance signal.

(Operation)

As a result, according to the present invention, in the second system on the receiving side of the luminance signal and the chrominance signal, it is possible to generate a signal representing an order sequence of each color difference signal of the chrominance signal from the synchronization signal included in the luminance signal. Becomes Therefore, there is no need to transmit the line index signal from the first system to the second system, thereby reducing the number of signal lines for transmitting the line index signal to simplify the connection structure of cables, connectors, and the like. be able to. In addition, since the connection structure is simplified, the connection operation is simplified, and the fear of occurrence of troubles such as poor contact is reduced, so that operability and reliability are improved.

〔Example〕

FIG. 1 is a circuit block diagram showing a configuration of a video signal transmission system according to one embodiment of the present invention. 14, the same parts as those in FIG. 14 are denoted by the same reference numerals, and detailed description is omitted.

First, the processor 10 converts the luminance signals Y + S and the respective color difference signals R-Y, B of the luminance signals into digital signals.
A luminance system write control circuit 51 and a chrominance system write control circuit 52 for writing -Y to the luminance system memory 13 and the chrominance system memory 14, respectively. Of these, the chrominance-related write control circuit 52 is, for example, as shown in FIG.
P) 55, a vertical synchronization signal extraction circuit (VSEP) 56, a horizontal counter 57, a decoder 58, and an address counter 59.

The horizontal synchronizing signal extracting circuit 55 and the vertical synchronizing signal extracting circuit 56 receive the synchronizing signal SYNC extracted from the luminance signal Y + S by the synchronizing signal extracting circuit (SYNCSEP) 60, respectively. The vertical synchronization signal VS is separated and extracted. The horizontal counter 57 outputs the horizontal synchronization signal every time the vertical synchronization signal VS is input.
The HS starts counting, and outputs a count value indicating the vertical scanning position for each field. By monitoring the count value, the decoder 58 monitors the memory active pulse only during the period corresponding to the effective screen for each of the odd field and the even field of one frame.
Generates MWAT. The address counter 59 counts the horizontal synchronization signal HS and outputs the memory active pulse MWAT
Generates a 7-bit memory write address WRAD (WA0 to WA7) during the period when is active. The address counter 59 outputs the least significant bit WA0 of the memory write address WRAD as a line index signal PLIND for the chrominance signals RY and BY input from the electronic still camera. The line index signal PLIND is composed of the respective color difference signals R-Y, B of the chrominance signal.
Switch 19 (first switch) for selectively inputting -Y.
) Is supplied as the switching control signal.

The processor 10 also includes a luminance read control circuit 53 and a chrominance read control circuit 53 for reading the luminance signal Y + S and the chrominance signals RY and BY stored in the luminance memory 13 and the chrominance memory 14, respectively. It has 54. Of these, the chrominance read control circuit 54 is, as shown in FIG.
A reference oscillator (CXO) 61 for generating a 14.3 MHz reference signal,
A counter 62 that counts the reference signal in 910 to generate a horizontal synchronizing signal HS, and further counts the horizontal synchronizing signal HS output from the counter 62 in 525 to calculate a count value representing a vertical scanning position for each field. It comprises a counter 63 for outputting, a decoder 64, and an address counter 65.

The decoder 64 monitors the count value output from the counter 63, and generates a memory active pulse MRAT only for a period corresponding to the effective screen for each of the odd field and the even field of one frame. The address counter 65 counts the horizontal synchronizing signal HS generated from the counter 62, and generates a 7-bit memory read address RDAD (RA0 to RA7) while the memory active pulse MRAT is active. 66 is a luminance circuit for generating a read address for luminance memory based on the count value output from each of the counters 62 and 63, and 67 is a synchronous circuit for generating a synchronous signal SYNC for adding to the luminance signal. It is a signal generation circuit.

On the other hand, the recorder 20 converts the luminance signal Y + S transmitted from the processor 10 through the cable 30 into a synchronization signal SY.
Synchronization signal extraction circuit (SYNCSEP) 31 for extracting NC
And the synchronization signal SY output from the synchronization signal detection circuit 31
Clamp pulse generation circuit (CP) 32 that generates crank pulse CS based on NC, and line index generation circuit (LIND
GEN) 33. The line index generation circuit 33 converts the line index signal LIND for switching the offset voltages V1 and V2 of the step circuit 28 into the synchronization signal SY.
It is generated based on the NC, and is configured, for example, as shown in FIG. That is, the line index generation circuit 33 includes a horizontal synchronization signal extraction circuit 35 that extracts the horizontal synchronization signal HS from the synchronization signal SYNC, and a D-type flip-flop 38 that connects between a terminal and a D input terminal. By supplying the horizontal synchronization signal HS to the clock input terminal of the D-type flip-flop 38, the line index signal LIND is output from the Q terminal of the D-type flip-flop 38. Further, it is necessary to make the phase of the line index signal LIND different between the odd field and the even field. For this reason, a field discriminating circuit 34 is provided to discriminate an odd field and an even field, and the AND gate 36 is gate-controlled by the discrimination output FS.
Only the rotation pulse PG (pulse generated from the rotation drive unit of the SVF for each rotation) in the even field is passed. And one-shot multivibrator 37
Then, a preset pulse OS synchronized with the rising edge of the output signal of the AND circuit 36 is generated, and the D-type flip-flop 38 is preset by the preset pulse OS.

The field discrimination circuit 34 can discriminate between the odd field and the even field by focusing on the relative phase between the synchronization signal SYNC and the horizontal synchronization signal HS. That is, the relative phase between the synchronization signal SYNC and the horizontal synchronization signal HS coincides with each other in the odd field as shown in FIGS. 5A and 5B. Become. Therefore, the synchronization signal SYNC and the horizontal synchronization signal
By monitoring the relative phase with the HS, it is easy to determine whether the field is an odd field or an even field.

Next, the operation of the system configured as described above will be described.

Luminance signal Y + from an electronic still camera (not shown)
When the S and chrominance signals RY and BY are input to the processor 10, the processor 10 first outputs a synchronization signal extracting circuit.
The synchronization signal SYNC is extracted from the luminance signal Y + S by 60, and the write address WRAD is generated by each of the luminance and chrominance write control circuits 51 and 52 based on the synchronization signal SYNC. Here, the chrominance write control circuit 52 according to the features of the present invention will be described.

That is, when the synchronization signal SYNC is input, the horizontal synchronization signal HS and the vertical synchronization signal VS are separately extracted from the synchronization signal SYNC by the horizontal synchronization signal extraction circuit 55 and the vertical synchronization signal extraction circuit 56, respectively. Then, a count value representing the vertical scanning position is output from the horizontal counter 57 based on these synchronization signals HS and VS, and based on the count value, the decoder 58 outputs a memory active pulse representing the effective screen period for each field from each field. MWAT is output.

For example, in an odd field, the effective screen period is, for example, 20
H, the memory active pulse MWAT is generated from the decoder 58 when the count value of the horizontal counter 57 becomes 20H or later.
Thereafter, the output of the memory write address WRAD is started as shown in FIG. At the same time, the address counter 59 outputs a line index signal as shown in FIG.
PLIND is generated, and according to the line index signal PLIND, the changeover switch 19 switches to the RY side when PLIND = "L" and to the BY side when PLIND = "H". Therefore, the chrominance memory 14 receives the color difference signal RY when the line index signal PLIND is at "L" level and the color difference signal BY when it is at "H" level, as shown in FIG. These color difference signals are sequentially written to the memory 14 according to the write address WRAD generated from the address counter 59.

In the even field, the effective screen period is set to 283.5H or later. For this reason, the memory active pulse MWAT is output from the decoder 58 when, for example, the count output of the horizontal counter 57 becomes 284H or later, whereby the output of the memory write address WRAD is output from the address counter 59 as shown in FIG. Be started. At the same time, a line index signal PLIND is generated from the address counter 59 as shown in FIG. 7, and the changeover switch 19 is switched according to the line index signal PLIND. Therefore, even in the case of this even field, as shown in FIG. 7, the chrominance system memory 14 receives the color difference signal RY when the line index signal PLIND is at the "L" level and the chrominance signal RY when the line index signal PLIND is at the "H" level. The color difference signals BY are input, and these color difference signals are sequentially written to the memory 14 in accordance with the write address WRAD generated from the address counter 59. FIG. 8 schematically shows the writing state.

On the other hand, in the chrominance system memory read control circuit 54, the memory read control is performed independently of the memory write control operation by the write control circuit 52. That is, based on the reference signal output from the reference oscillator 61, the counter 62 generates the horizontal synchronizing signal HS, and the counter 63 generates the count output indicating the vertical scanning position for each field. Then, from the decoder 64, the counter
A memory active pulse MRAT representing an effective screen period is output for each field based on the count output of 63, and address counter 65 generates a read address RDAD according to the memory active pulse MRAT.

For example, in the odd field, when the count output of the counter 63 reaches 20H, the memory active pulse MRAT is output from the decoder 64, whereby the address counter 65 starts generating the read address RDAD as shown in FIG. . For this reason, the chrominance memory 14 outputs a color difference signal according to the read address RDAD.
They are read out in the order of Y, BY. In the even field, when the count output of the counter 63 reaches 284H, the memory active pulse MRAT is output from the decoder 64,
Thus, the address counter 65 starts generating the read address RDAD as shown in FIG. For this reason, the color difference signals RY and BY are sequentially read from the chrominance memory 14 in accordance with the read address RDAD.

That is, from the chrominance memory 14, the ninth
As shown in FIG. 10 and FIG. 10, the color difference signal R-Y is obtained when the number of the horizontal scanning line of the luminance signal Y + S read from the luminance memory 13 is even in both the odd field and the even field. When the number is odd, the color difference signals BY are read out correspondingly.

Then, the luminance signal Y + S and the chrominance signal RY / BY read from the luminance memory 13 and the chrominance memory 14 are returned to the analog signals by the D / A 16 and 17, respectively. Via recording machine 20
Is transmitted to

In the recording machine 20, when the luminance signal Y + S and the chrominance signal RY / BY arrive from the processor 10, the synchronizing signal extraction circuit 31 outputs the luminance signal Y + S.
The synchronization signal SYNC is extracted from + S, and the clamp pulse generation circuit 32 generates a clamp pulse CS based on the synchronization signal SYNC. In the line index generation circuit 33,
The line index signal LIND is generated based on the synchronization signal SYNC as follows.

That is, first, the horizontal synchronization signal HS is separated and extracted from the synchronization signal SYNC by the horizontal synchronization signal extraction circuit 35 (FIG. 3), and the horizontal synchronization signal HS is supplied to the D-type flip-flop 38 as a clock. Therefore, the D-type flip-flop 38 outputs a line index signal LIND synchronized with the synchronization signal SYNC as shown in FIG. At this time, the field discriminating circuit 34 outputs the synchronization signal SY
A field discrimination is performed based on the NC, and as shown in FIG. 11, a discrimination signal FS that outputs an "H" level for an even field and an "L" level for an odd field is output. Therefore, the AND gate 36 becomes conductive only during the even-numbered field according to the field discrimination signal FS, and the rotation pulse PG generated from the spindle motor 26 during the even-numbered field is applied to the one-shot multivibrator 37.
Supplied to Then, the one-shot multivibrator 37 outputs the rotation pulse as shown in FIG.
Since the preset pulse OS is generated in synchronization with the rising edge of PG, the D-type flip-flop 38 is preset to the “H” level at this time. Thus, the line index signal LI generated from the D-type flip-flop 38
ND is phase-controlled immediately before shifting to the odd field. Therefore, the line index signal LIND becomes “H” level when the vertical scanning number is odd and “L” level when it is even in the odd field period as well as the even field period.

When such a line index signal LIND is generated, the changeover switch 28a (15th switch) of the step circuit 28 (FIG. 1)
In the figure, the line index signal LIND is switched to the offset voltage V1 side when it is at "L" level, and is switched to the offset voltage V2 side when it is at "H" level. At this time, the chrominance signal sent from the processor 10 is
As described above, the color difference signal RY is set to correspond when the horizontal scanning number of the luminance signal is even, and the color difference signal BY is set to correspond when the horizontal scanning number of the luminance signal is odd. Therefore, in the step circuit 28, the offset voltage V1 is selected when the color difference signal RY is input, and the offset voltage V2 is selected when the color difference signal BY is input, and is output via the switch 28b. Will be. Therefore, each color difference signal RY, BY has a DC level step as shown in FIG. Figures 12 and 13 show the recorder
Synchronization signal SYNC and line index signal at 20
The phase relationship between LIND and the chrominance signal RY / BY is
FIG. 4 is a diagram showing each of an odd field and an even field.

As described above, in the present embodiment, in the processor 10, the luminance signal Y + S and the chrominance signal R− are output from the luminance memory 13 and the chrominance memory 14, respectively.
When reading out Y / B-Y, the phase relation is determined when the number of horizontal scanning lines of the luminance signal Y + S is an even number.
When Y is an odd number, the color difference signals BY are determined so as to correspond to each other. Further, a line index signal generation circuit 33 is provided in the recorder 20, and the circuit 33 generates a line index signal LIND based on the synchronization signal SYNC sent from the processor 10, and this line index signal LI
The step circuit 28 is controlled according to ND.

Therefore, based on the luminance signal Y + S sent from the processor 10, the recorder 20 itself uses the line index signal.
A LIND can be generated, so that there is no need to transmit the line index signal LIND from the processor 10. Therefore, the number of signal lines of the cable 30 for connecting the processor 10 and the recorder 20 is only two for the luminance signal and the chrominance signal for transmitting and recording the video signal as described above. As a result, a general-purpose and inexpensive cable 30 can be used. Also, as for the connector for connecting the cable 30 at the same time, a connector with a small number of pins can be used, so that a simple and inexpensive connector can be used,
Thereby, the reliability of the connection structure can be improved. Further, a connector having a small number of pins requires less insertion / extraction force than a connector having a large number of pins, so that attachment / detachment is facilitated and operability is improved.

The present invention is not limited to the above embodiment.
For example, in the above embodiment, the case where the video signal is transmitted from the processor 10 to the recording device 20 has been described as an example, but the case where the video signal is transmitted from the electronic still camera to the processor, The same applies to the case of transmitting a video signal. Further, as still another application example, when a process circuit unit, an imaging circuit unit, a recording circuit unit, and the like are each independently configured by a circuit board or the like in a video device such as an electronic still camera, these components may be used. The configuration of the present invention may be applied when a video signal is transmitted between unitized circuits. Further, in the above-described embodiment, a system related to an electronic still camera has been described as an example. However, as long as the system transmits a chrominance signal in a color difference line sequential mode, the same applies to other systems using a video camera or an optical video disk. Can be applied. further,
In the above embodiment, the memory read control system of the processor 10 is provided independently of the write control system. However, by inputting the synchronization signal SYNC used in the write control system to the read control system, the read control system It may be configured to operate in synchronization with the system. This eliminates the need for a circuit for generating the synchronization signal SYNC or the like in the read control system, thereby simplifying the circuit configuration. Further, the line index signal LIND may be used for other purposes as necessary, in addition to being used for switching control of the offset voltage in the step circuit. In addition, the configuration of the reading control means for the chrominance signal in the first system and the means for generating the line index signal in the second system, the phase relationship between the luminance signal and each color difference signal of the chrominance signal, etc. Various modifications can be made without departing from the scope of the invention.

〔The invention's effect〕

As described above in detail, the present invention relates to a system for transmitting a chrominance signal in a line-sequential manner from a first system to a second system, wherein the first system stores a luminance signal including a synchronization signal in the first system. A chrominance memory for storing the chrominance signal; and read control means for reading and writing the chrominance signal. The read control means serves as elements for forming the line-sequential chrominance signal from the chrominance memory. When sequentially reading out the chrominance signals, the chrominance signals are read out so as to maintain a specific phase relationship with a synchronization signal in the luminance signal read out from the luminance system memory, and
Is provided with a discriminating means, and the first discriminating means is provided by the discriminating means.
Based on the synchronization signal included in the luminance signal transmitted from the system, the sequence of each element in the chrominance signal is discriminated, and the discrimination result is, for example, a step of the DC level with respect to each element of the chrominance signal. It is provided for processing for providing.

Therefore, according to the present invention, transmission of the line index signal can be made unnecessary, thereby reducing the number of signal lines connecting the two systems to simplify the connection configuration, thereby improving operability and reliability. A video signal transmission system that can be improved can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a video signal transmission system according to an embodiment of the present invention, FIG. 2 is a circuit block diagram showing a configuration of a memory write control circuit of the system, and FIG. 3 is a memory read control circuit. FIG. 4 is a circuit block diagram showing a circuit configuration of a line index signal generating circuit, FIG. 5 is a timing chart for explaining a field discriminating method, and FIGS. It is used to explain the operation of the system shown in FIG.
FIG. 7, FIG. 7, and FIG. 9 to FIG. 13 are timing diagrams showing the phase relationship between the signals, FIG. 8 is a schematic diagram showing an example of the state of writing the chrominance signal in the memory, and FIG. FIG. 15 is a circuit block diagram illustrating a schematic configuration of a signal transmission system, FIG. 15 is a diagram illustrating an example of a configuration of a step circuit, FIG.
FIG. 16 is a signal waveform diagram used for explaining the operation of the step circuit. 10 ... Processor, 20 ... Recorder, 25 ... SVF, 26 ...
Spindle motor, 28: Step circuit, 28a: Changeover switch, 28b: Clamp switch, 30: Cable, 31: Synchronous signal extraction circuit, 32: Clamp pulse generation circuit, 33: Line index signal Generator circuit, 34 ...
... Field discriminating circuit, 35,55 ... Horizontal synchronization signal extracting circuit, 36 ... And gate, 37 ... One-shot multivibrator, 38 ... D-type flip-flop, 51 ... Luminance write control circuit, 52 ... Chrominance write control circuit, 53 ... Luminance read control circuit, 54 ...
Chrominance readout control circuit, 56 ... vertical synchronization signal extraction circuit, 57 ... vertical counter, 58,64 ... decoder, 59,
65 ... Address counter, 61 ... Reference oscillator, 62,63 ...
... Counter, Y + S ... Luminance signal, SYNC ... Sync signal, HS ... Horizontal sync signal, VS ... Vertical sync signal, R-
Y, BY-color difference signal, MWAT, MRAT-memory active pulse, WRAD-write address, RDAD-read address, PLIND, LIND-line index signal, PG-
Rotation pulse, FS: Field discrimination signal, CS: Clamp pulse.

Claims (1)

(57) [Claims] 1. A luminance signal including a synchronization signal generated in a first system and a chrominance signal in a line-sequential mode are transmitted to a second system via one transmission channel, respectively. Within the first of the chrominance signals
A video signal transmission system adapted to be able to discriminate a line-sequential sequence configuration in a state matched with a chrominance signal in the system, wherein the first system is a luminance memory storing the luminance signal; A chrominance memory for storing the chrominance signal, and a synchronizing signal in the luminance signal read from the luminance memory for sequentially reading the chrominance signals as the respective elements to form the line-sequential chrominance signal from the chrominance memory. And read control means for reading the data so that a specific phase relationship is maintained. The second system is configured to control the chrominance signal based on a synchronization signal included in the luminance signal transmitted from the first system. Video signal transmission system comprising a discriminating means for discriminating an ordered sequence of each element in the video signal