JP2910909B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field-effect transistor excellent in high-speed characteristics and high-frequency characteristics, and more particularly to InAlN
The present invention relates to a field-effect transistor using an As layer as an electron supply layer.

[0002]

2. Description of the Related Art A conventional example of a general structure of a field effect transistor having an InGaAs active layer and an InAlAs electron supply layer is disclosed by PCE Chao et al. IEEE Electron Device Lett.), EDL-11,
59, 1990.

[0003] This report discloses a high-purity InGaAs layer provided on a semi-insulating InP substrate in lattice-matching therewith, and an InGaAs layer that forms a heterojunction discontinuously in a conduction band with the high-purity InGaAs layer.
After successively growing an AlAs electron supply layer (consisting of an n-type dopant added layer and an undoped layer),
The present invention relates to a field-effect transistor having a gate electrode formed on an AlAs electron supply layer.

However, in this structure, since the gate electrode is formed on the InAlAs electron supply layer, the InAlAs layer is exposed on the surface after the formation of the gate electrode.
Impurities such as F easily adhere to the surface of the InAlAs layer, and the impurities diffuse to the n-type dopant added layer in the InAlAs electron supply layer during the heat treatment step. as a result,
There is a problem in that the n-type dopant in the InAlAs electron supply layer is inactivated, thereby deteriorating device characteristics such as a decrease in current and mutual conductance.

As a structure to solve this problem, InAl
An InGaP layer is stacked on the As electron supply layer, and the InG
A structure in which a gate electrode is formed on an aP layer has been described by Fujita et al. in IEEE Electron Device Letters, EDL-14,
259, 1993. FIG. 2 shows the cross-sectional structure. Here, 21 is a semi-insulating InP substrate, 2
2 is an undoped InP layer, 23 is an undoped InGaAs
s layer, 24a is undoped InAlAs layer, 24b is n
Type InAlAs layer, 25 is an undoped InGaP layer, 2
6 is an n-type InGaAs layer, 27 is a source electrode, 28 is a drain electrode, and 29 is a gate electrode. In this structure,
By covering an n-type InAlAs layer 24b for supplying electrons to the channel with an undoped InGaP layer 25 and forming a gate electrode 29 on the InGaP layer 25,
The nAlAs layer 24b is shielded from the external atmosphere.

As another solution, InAlAs
A structure in which a GaAs protective layer is stacked on an electron supply layer and a gate is formed on the GaAs protective layer has been proposed in Japanese Patent Application Laid-Open No. 6-84958. The structure is shown in FIG. Here, 31 is a semi-insulating InP substrate, 32 is undoped I
nAlAs layer, 33 is an undoped InGaAs layer, 34
Is an n-type InAlAs layer, 35 is undoped GaAs
Layer, 36 is an n-type InGaAs layer, 37 is a GaAs layer, 3
8 is a source electrode, 39 is a drain electrode, and 40 is a gate electrode. In this structure, n supplies electrons to the channel.
The type InAlAs layer 34 is covered with a GaAs layer 37,
By forming the gate electrode 40 on the aAs layer 37, the n-type InAlAs layer 34 is shielded from the external atmosphere.

[0007]

However, IEE ELECTRON DEVICE LETTERS (IEEE
Electron Device Lett., EDL-14, 259 pages,
In the structure shown in (1993), the InP composition ratio of the InGaP layer on which the gate electrode is placed is high, so that the Schottky barrier height is lower than that in the case where the gate electrode is placed on a normal InAlAs layer. However, there is a problem that the gate leak current increases.

On the other hand, in the structure proposed in Japanese Patent Application Laid-Open No. 6-84958, the critical thickness at which a GaAs layer can be grown on an InP substrate without dislocation is as small as about 3 nm. Type InGaAs
When removing the s layer by etching, there is a problem that it is difficult to stop the etching in the GaAs layer due to a variation in the etching amount, and therefore it is difficult to manufacture the s layer at a high yield.

The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to manufacture a field effect transistor having an InAlAs electron supply layer at a high yield without deteriorating characteristics. It is to be able to do.

[0010]

According to a first aspect of the present invention, there is provided a field effect transistor in which an InAlAs electron supply layer is formed on a semiconductor layer forming a channel. above, Ri do a material not containing Al in degree dislocations due to lattice mismatch is not introduced thickness, and a function as an electron supply layer
It is characterized in that a protective layer and an InAlAs Schottky layer which are not provided are formed.

[0011]

According to the present invention, a protective layer made of a material not containing Al, such as a GaAs layer, is introduced on the surface side of the InAlAs electron supply layer, thereby shielding the electron supply layer from the external atmosphere. In other words, the diffusion of impurities that have entered from the surface in a protective layer such as a GaAs layer can be prevented.
Inactivation of the n-type dopant in the s electron supply layer can be prevented. Therefore, deterioration of device characteristics such as a decrease in drain current and a decrease in transconductance caused by a heat treatment process, which is a problem in the conventional structure, can be avoided, and a highly reliable field effect transistor can be realized.

In addition, since the gate electrode is formed on the InAlAs layer in the same manner as the element structure which has been widely used in the past, the conventional method can be used as a pretreatment method when forming the gate electrode. A gate breakdown voltage comparable to the structure can be ensured.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a main part of an embodiment of the present invention. In the figure, 1 is semi-insulating InP
Substrate, 2 is a high-purity InAlAs buffer layer, 3 is a high-purity InGaAs channel layer, 4 is modulation-doped InAl
The As electron supply layer 5 is made of high-purity GaAs serving as a protective layer.
The layer 6 is a high-purity InAlAs Schottky layer, 7 is an n-type InGaAs ohmic contact layer, 8 is a source electrode, 9 is a drain electrode, and 10 is a gate electrode.

The field effect transistor of this embodiment can be formed as follows. First, a 300-nm high-purity InAlAs buffer layer 2, a 40-nm high-purity InGaAs channel layer 3, and a 3-nm high-purity InAlAs layer, for example, are formed on a semi-insulating InP substrate 1.
10 nm thick InAl doped with 5 × 10 ¹⁸ cm ⁻³
An InAlAs electron supply layer 4 composed of three layers of an As layer and a high-purity InAlAs layer having a thickness of 15 nm;
An aAs layer 5, a 3 nm-thick high-purity InAlAs Schottky layer 6, and a 50 nm-thick n-type InGaAs ohmic contact layer 7 doped with 5 × 10 ¹⁸ cm ^{−3 of} Si are sequentially grown.

Subsequently, after element isolation such as mesa etching is performed, for example, AuGe, Ni, and Au are deposited on the ohmic contact layer, and alloy processing is performed to form the source electrode 8 and the drain electrode 9. Further, after partially removing the n-type InGaAs ohmic contact layer 7 between the source electrode 8 and the drain electrode 9, the exposed high-purity InAlA
Ti, Pt, and Au are sequentially deposited on the s-Schottky layer 6 to form the gate electrode 10, and the fabrication of the field-effect transistor according to the present embodiment is completed.

When the n-type InGaAs ohmic contact layer is removed by etching, for example, if an aqueous solution comprising citric acid and hydrogen peroxide is used, only the InGaAs layer is removed by etching with a high selectivity to the InAlAs layer. it can. When this method is used, the etching is stopped at the InAlAs layer, so that the GaAs protective layer is not removed by etching.

While the preferred embodiment has been described above,
The present invention is not limited to the above embodiment, and various modifications are possible. The thickness of each layer and the additive concentration of the dopant are not limited to the values of the present embodiment.
A high-purity InAlAs layer of about 6 nm, a layer in which Si is added as an n-type impurity to about 5 × 10 ¹² cm ⁻² , and a high-purity InAlAs layer of about 15 nm can be used. The thickness of the GaAs layer is not limited to 3 nm, but can be set to another value as long as it is equal to or less than the critical thickness. Further, the protective layer can be formed of another material.

[0018]

As described above, the field-effect transistor of the present invention has a structure in which an InAlAs electron supply layer is provided on an operation layer made of InGaAs or the like.
Since a protective layer made of GaAs or the like is introduced on the surface side of the lAs electron supply layer to shut off the electron supply layer from the external atmosphere, the n-type dopant in the InAlAs electron supply layer is inactivated by external impurities. Can be prevented. Therefore, according to the present invention, it is possible to avoid deterioration of device characteristics such as a decrease in drain current and a decrease in transconductance.

Further, InA, which has been widely used in the past,
Since the gate electrode is formed on the lAs layer, a conventional method can be used as a pretreatment method at the time of forming the gate electrode, and a gate breakdown voltage equivalent to that of the conventional structure can be secured. Further, at the time of recess etching in the gate forming step, InA provided on the surface side of the protective layer is formed.
Since the etching can be stopped at the lAs layer,
The protective layer can be reliably left.

[Brief description of the drawings]

FIG. 1 is a sectional view of one embodiment of the present invention.

FIG. 2 is a sectional view of a conventional example.

FIG. 3 is a sectional view of another conventional example.

[Explanation of symbols]

 1, 21, 31 semi-insulating InP substrate 2 high-purity InAlAs buffer layer 3 high-purity InGaAs channel layer 4 InAlAs electron supply layer 5 high-purity GaAs layer 6 high-purity InAlAs Schottky layer 7 n-type InGaAs ohmic contact layer 8, 27, 38 source electrode 9, 28, 39 drain electrode 10, 29, 40 gate electrode 22 undoped InP layer 23, 33 undoped InGaAs layer 24a undoped InAlAs layer 24b, 34 n-type InAlAs layer 25 undoped InGaP layer 26, 36 n-type InGaAs layer 32 Undoped InAlAs layer 35, 37 GaAs layer

Claims (4)

(57) [Claims] An InA is formed on a semiconductor layer forming a channel.
In the field effect transistor lAs electron supply layer is formed, the InAlAs electron supply layer, to the extent that dislocations due to lattice mismatch is not introduced Ri Do a material not containing Al of thickness, and, as the electron supply layer With function
Field effect transistor, characterized in that had not protective layer and the InAlAs Schottky layer is formed. 2. The field effect transistor according to claim 1, wherein said protective layer is formed of GaAs. 3. The field effect transistor according to claim 1, wherein said InAlAs electron supply layer is formed as a modulation doping layer including an undoped layer and an n-type dopant added layer. 4. The field effect transistor according to claim 1, wherein no dopant is intentionally added to the protective layer and the InAlAs Schottky layer.