JP2912166B2 - Data selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in an optical data transmission system for multiplexing and distributing high-speed data. In particular, it is used as a simpler method as one of methods for extracting only necessary data from a large-capacity signal such as image distribution and information services.

[0002]

2. Description of the Related Art Conventionally, in a high-speed data communication system in which N types of data are time-division multiplexed and transmitted, literature (Japanese Unexamined Patent Publication No.
As a method for extracting a multiplexed signal as disclosed in Japanese Patent Application Laid-Open No. 70135/1995, a method using a time division multiplexing circuit is known. FIG. 6 shows a configuration example when data is divided by four.
FIG. 7 shows a time chart of this configuration example.

[0003] D-type flip-flops 12, 13, 14,
Reference numerals 15, 27, 28, 29, and 30 constitute a speed conversion unit 41 that converts high-speed data into a plurality of low-speed data. A clock signal having the same speed as the high-speed data at the data input terminal 11 is supplied to the clock input terminal 16, and the clock signal at the clock input terminal 16 is supplied to the clock terminals C of the D-type flip-flops 12, 13, 14, and 15 through the inverter 42. And D-type flip-flops 12, 13, 1
Reference numerals 4 and 15 constitute a four-stage shift register. The output Q-bar of each of the D-type flip-flops 12, 13, 14, 15 is connected to a D-type flip-flop 27, 28, 29,
30 is input to the input terminal D. Where the Q bar is

[0004]

[Outside 1]

[0005] The same applies hereinafter.

[0006] The synchronization switching control circuit 42 is connected to the input terminal 3
7 is supplied to the input terminal T of the toggle flip-flop 38, and the output Q of the toggle flip-flop 38 is connected to the input terminal T of the toggle flip-flop 39.
The output terminal Q of the toggle flip-flop 39 is supplied to the gates 32 and 34 of the switching circuit 40, and the output terminal Q of the toggle flip-flop 39 is supplied to the switching circuit 40. The output terminal Q of the toggle flip-flop 39 is supplied to the gates 34 and 35 in the
Are supplied to the gates 32 and 33 in the inside.

The clock signal shown in FIG. 7A is supplied to the clock input terminal 16, and the clock signal shown in FIG.
7 is supplied, and a synchronization command signal shown in FIG. The signal input from the clock terminal 16 is a toggle flip-flop 18, 19,
FIG. 6 shows the structure of FIG.
D, E, F, and G, four clocks which are shifted by one clock from the input clocks are output. Before the synchronization command signal arrives, the output terminal Q bar of the toggle flip-flop 38 is at a high level, the output terminal Q bar of the toggle flip-flop 39 is at a high level, and only the gate 32 is opened. At this time, the output from the output terminal Q of the D-type flip-flop 20 is selected as the output of the switching circuit 35 as shown in FIG.
It is input to clock input terminals C and 9, and outputs a signal divided into four. When the synchronization command signal is input, the output Q of the toggle flip-flop 39 becomes high level, and the output Q of the toggle flip-flop 39 becomes high level. At this time, the gate 35 in the switching circuit 30 is opened, and the output of the switching circuit 40 outputs the G output of FIG.
The outputs 28, 29 and 30 output signals of different channels. Similarly, each time the synchronization command signal is input, the gates that open in the switching circuit are shifted to 34 and 33, whereby the D-type flip-flops 27, 28, 29 and 30 are opened.
Output changes.

[0008]

In the above method, the conventional method is considered suitable for transmitting and receiving various types of data on a communication network. However, when considering a high-speed optical subscriber system, In many cases, only one piece of data is required on the subscriber side, and the conventional method has a problem that the apparatus scale and power consumption increase and control becomes complicated.

It is an object of the present invention to provide a data selection device capable of constructing a network having a small device scale and greatly reducing the power consumption of each receiver.

[0010]

A data selection device according to the present invention.
In the method using the input signal, the phase of a synchronization signal obtained by dividing an input signal obtained by time-division multiplexing N low-speed signals into 1 / N or 1 / (N + M) of a clock signal having the same speed as the input signal. When the frequency division ratio of the synchronization signal is 1 / N, one selected low-speed signal is output from the input signal,
By changing the frequency division ratio of the synchronization signal to 1 / (N + M) during the N + M periods of the clock signal, a low-speed signal separated by M bits from the selected low-speed signal is output.

In the above method, N and N + M are relatively prime, and the frequency division ratio is changed continuously or intermittently N times at the maximum to select any one of the low-speed signals. It is characterized by doing.

The data selection device of the present invention uses a D-type flip-flop and an OR circuit as a frequency dividing circuit for dividing a clock signal having the same speed as an input signal into 1 / N, and uses a 1 / (N + M ).
(N> M and N and N + M are mutually prime) a variable frequency dividing circuit capable of changing the frequency dividing ratio , and an identification circuit for identifying the input signal according to the output phase of the variable frequency dividing circuit. wherein, one signal of the sometimes time-division multiplexed N signals of the division of the variable frequency division circuit 1 / N and outputs the identification circuit, in the variable frequency divider circuit, a frequency dividing ratio Synchronous life to change
When the command signal is input, the frequency division ratio is changed to 1 / (N + M) during the N + M period of the clock signal , and the synchronization command signal is input.
No. The by inputting the maximum N times, and selects any one of the signals time-division multiplexed in the N

[0013]

The data selection method according to the present invention will be described with reference to FIG.

As shown in FIG. 1, N types of time-division multiplexed signals are input to D-type flip-flops for data identification. A clock signal having the same speed as that of the signal is input to a variable frequency dividing circuit capable of dividing the frequency by 1 / N or 1 / (N + M) (N> M and N and M are relatively prime). It is input to the clock input of a flip-flop.
Here, the variable frequency dividing circuit changes the frequency dividing ratio according to the synchronization command signal.

The operation will be described with reference to FIG. Normally, the output of the variable frequency dividing circuit is 1 / N as shown in FIG. 2C, and one signal sequence is selected from the N-multiplexed signals as shown in FIG. 2E. At this time, when a synchronization command signal as shown at D in FIG. 2 is input for at most (N + M) clocks, the output of the variable frequency dividing circuit becomes 1 / (N + M) as shown at C in FIG.
M), and a signal delayed by M bits from the selected signal is selected. At this time, the output of the variable frequency dividing circuit outputs a 1 / N clock until the synchronization command signal is input again, and selects a signal sequence delayed by M bits. At this time, an arbitrary signal can be obtained by the pulse width of the synchronization command signal.

[0016]

FIG. 3 is a diagram for explaining a first embodiment of the present invention. FIG. 4 shows a time chart for explaining the first embodiment. This embodiment shows a case where one channel is selected when four signals are multiplexed. In FIG. 4, A is a clock signal, B is a high-speed signal, C is a selection command signal, D is a 1/4 frequency-divided clock signal, and E is an output signal.

The high-speed data from the data input terminal 11 is D
It is supplied to the data terminal D of the flip-flop 12.
A clock signal having the same speed as the high-speed data at the data input terminal 11 is supplied to the clock input terminal 16, and the clock signal at the clock input terminal 16 is supplied to the D-type flip-flop 21,
22 and 23, respectively. D
The output Q of the flip-flop 21 is supplied to the input D of the D-type flip-flop 22 and the clock input terminal C of the D-type flip-flop 12,
Is supplied to an OR circuit 26, an output of the OR circuit 26 is supplied to an input D of a D-type flip-flop, an output Q bar of the D-type flip-flop 22 is supplied to an OR circuit 25, and a D-type flip-flop 23 Is supplied to the OR circuit 25, and the output of the OR circuit 25 is supplied to the input D of the D-type flip-flop 21.

A clock signal shown in FIG. 4A is supplied to the clock input terminal 16, a high-speed signal shown in FIG. 4B is supplied to the signal input terminal 11, and a signal shown in FIG.
Is supplied to the OR circuit 26.
Before the selection command signal arrives, the input of D-type flip-flop 23 is at H level, and the output of Q bar is always at L level. At this time, the D-type flip-flops 21, 2
2 forms a 1/4 frequency dividing circuit, and a D-type flip-flop 21
The output Q of the clock input terminal 16 as shown in FIG.
A clock generated by dividing the clock input from the by 1/4 is generated. As a result, as shown in FIG. 4E, only one signal sequence X can be extracted from the four time-division multiplexed signals.

When a selection command signal is input, D-type flip-flops 21, 22, and 23 output a clock obtained by dividing the input clock by ５.

In the data selection, the time for generating the selection command signal is set to the H level for five clocks with respect to the input clock, so that the clock division timing changes, and the obtained quarter-divided clock is one time. The slot changes, and the signal sequence Y is selected. Similarly, an arbitrary signal can be selected by changing the pulse width of the selection command signal.

It is possible to select a channel for an arbitrary N, not only in the case of four multiplexes as in the first embodiment. In the second embodiment, a case will be described in which one channel is selected from eight multiplexed signals. FIG. 5 is a diagram for explaining the second embodiment.

As in the first embodiment, the circuit comprises a variable frequency dividing circuit and an identification circuit. At this time, the variable frequency dividing circuit is realized by further connecting a toggle flip-flop to the variable frequency dividing circuit of the first embodiment. Until the selection command signal is input, the output of the variable frequency dividing circuit outputs a 1/8 frequency-divided clock, and selects one of the eight multiplexed signals. When the selection command signal is input, the variable frequency dividing circuit outputs a 1/9 frequency-divided clock. In signal selection, the time for issuing the selection command signal is set to the H level for nine clocks with respect to the input clock, so that the clock frequency-dividing timing changes and the adjacent channel is selected. Similarly, an arbitrary signal can be selected by changing the pulse width of the selection command signal.

Although a D-type flip-flop is used as a gate in the above embodiment, it goes without saying that any gate that satisfies the same function may be used.
The variable frequency divider and the frequency division ratio in any configuration and division ratio
There may be.

[0024]

According to the present invention, it is possible to extract a desired signal in a high-speed digital multiplexed signal system with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating the present invention.

FIG. 2 is a time chart illustrating the operation of the present invention.

FIG. 3 is a block diagram showing a first embodiment of the present invention.

FIG. 4 is a time chart illustrating the first embodiment of the present invention.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a conventional data separation circuit.

FIG. 7 is a time chart illustrating a conventional data separation circuit.

[Explanation of symbols]

11 High-speed data input terminal 12, 13, 14, 15, 20, 21, 22, 23, 2
7, 28, 29, 30 D flip-flop 16 Clock input terminal 17 Synchronization command signal input terminal 18, 19, 38, 39 Toggle flip-flop 25, 26, 36 OR circuit 31, 32, 33, 34, 35 AND circuit 40 Clock switching circuit 41 Speed converter 42 Synchronization switching control circuit

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-316532 (JP, A) JP-A-2-70135 (JP, A) JP-A 62-133439 (JP, U)

Claims (1)

(57) [Claims] A clock signal having the same speed as an input signal is 1 / N
A variable frequency dividing circuit capable of changing the frequency dividing ratio to 1 / (N + M ) (N> M and N and N + M are prime) by using a D-type flip-flop and an OR circuit as a frequency dividing circuit. If the input signal includes identification circuit that performs identification in accordance with the phase of the output of the variable frequency divider, the division of the variable frequency division circuit is sometimes time-division multiplexed N signals of 1 / N one signal of the internal output by the identification circuit, in the variable frequency division circuit,
When synchronization instruction signal for changing the frequency dividing ratio is input, between the N + M cycle of the clock signal, the frequency division ratio 1 / (N + M)
Is changed, and the synchronization command signal is input at most N times to select any one of N time-division multiplexed signals.