JP2912210B2 - Asynchronous serial data transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an asynchronous serial data transmission device.

[0002]

2. Description of the Related Art Conventionally, in this type of data transmission, a start-stop synchronization method is used in which a start bit and a stop bit are added before and after data for each word of communication data.

[0003]

In the above-mentioned conventional asynchronous serial data transmission system, first, means for adding a start bit and a stop bit before and after transmission data is required, so that the circuit configuration becomes complicated. There is a problem that becomes. In particular, when the size of one word is variable, the circuit configuration must be particularly conscious of the number of the stop bit to be transmitted from the start of data transmission, which is more complicated. Secondly, since two bits of additional information are required for one word of data, there is a problem that transmission efficiency is reduced.

An object of the present invention is to improve hardware simplification and transmission efficiency by adopting a configuration of transmission data that can add additional information to one bit per word. is there.

[0005]

According to the present invention, there is provided an asynchronous serial data transmission apparatus, comprising: means for transmitting, to a transmission side, a start bit at the beginning of each word of transmission data;
Means for continuously outputting the last bit of one word to the transmission path;
It has a means for setting the start bit to a value having a polarity opposite to that of the last bit, a means for detecting the start bit on a receiving side, and a means for removing a start bit from received data and extracting a data part. Features.

[Operation] In the present invention, since the last bit of the transmission data is held on the transmission path, it can also serve as the mark state of the transmission path. Therefore, the state of the transmission path can be changed by the conventional start-stop synchronization method. A stop bit for returning to the mark state is not required.

[0007]

Next, embodiments of the present invention will be described in detail.

In one embodiment of the present invention shown in FIG. 1, data consisting of three bits in one word is transmitted from the host device 1 on the transmitting side to the host device 9 on the receiving side.

First, the configuration of the host device 1 which is the transmission source will be described. On the host device 1 side, a shift register 2 for performing parallel-serial conversion, a transmission clock generation circuit 3 for generating a transmission timing clock, and a value of the least significant bit of the shift register 2 are inverted and input to the shift register 2 again. It has a circuit to return as a value and a driver 5 to the transmission line.

The shift register 2 has a 4-bit length that is 1 bit longer than 3 bits, which is one word length of the transmission data, shifts from the upper to the lower direction in response to the transmission clock 7, and transmits the value of the least significant bit. This is a configuration for outputting to the road 8.

The transmission data from the host device 1 is
The upper three bits are written in response to the write strobe signal 6, and at the same time, the value of the least significant bit is inverted.

The transmission clock generation circuit 3 is a clock source for performing a shift operation of the shift register 2. The transmission clock generation circuit 3 starts clock generation when transmission data is written from the host device 1 to the shift register 2, and generates one-word data. After transmission, that is, after outputting three clocks, the operation is stopped.

Next, the configuration on the receiving side will be described. On the receiving side,
It has a shift register 10 for performing serial-parallel data conversion, a reception clock generation circuit 11, a start bit detection circuit 12, and a receiver 13.

The shift register 10 is 3 bits long,
Similarly to the shift register 2 on the transmission side, the upper bit is shifted from the upper bit to the lower bit, and the shift input of the most significant bit is input data from the transmission line 8.

The start bit detection circuit 12 is connected to the transmission line 8
And a differentiating circuit for detecting a change in received data from the receiving clock generator. When a start bit is detected, the receiving clock generating circuit 11 is started. Thereafter, during data reception, detection of a change in the reception data is suppressed, and after receiving a reception completion notification from the clock generation circuit 11, detection of the start bit is started again.

The reception clock generation circuit 11 outputs three reception clocks in response to the start bit detection notification from the start bit detection circuit 12, and after the output is completed,
The host device 9 and the start bit detection circuit 12 are notified of the completion of the reception.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. This time chart is for an operation example when transmitting two words of data.

The value of the first word is 101 in a binary number, and the value of the second word is 010. The time charts are all positive logic descriptions, the initial values of the shift registers are all 0, and the transmission line 8 is a logical 0 mark state.

In this state, first, transmission data is written from the host device 1 to the shift register 2. This is the T2 phase of the time chart of FIG. 2, and when the write strobe signal 6 is triggered, the value of the shift register 2 becomes 1 from the top.
011. The least significant bit of the shift register 2 is T
One phase changes from logic 0 to logic 1, which becomes a start bit and is also reflected on the transmission line 8.

In response to the write strobe signal 6, the transmission clock generation circuit 3 changes the transmission clock 7 from T3 to T
Outputs 3 clocks in 5 phases and stops. This allows
Following the start bit, transmission data is output to the transmission line 8 in order from the least significant bit. After the transmission of the last bit, the value of the last bit is held as it is, and this becomes the mark state. At this time, the state of the transmission line 8 becomes logic 1 contrary to the mark state of the T1 phase.

Next, the data receiving operation will be described.

As described above, when the host device 1 writes the transmission data into the shift register 2, the transmission path 8
Changes from logic 0 to logic 1. The start bit detection circuit 12 detects this change in the transmission path in the T2 phase and activates the reception clock generation circuit 11.

The reception clock generation circuit 11 outputs three reception clocks from T3 to T5 in response to this, and the data of the transmission line 8 is sequentially taken in from the top of the shift register 10.

After outputting three clocks, the reception clock generation circuit 11 notifies the host device 9 and the start bit detection circuit 12 of the completion of reception. In response to this, the host device reads the value of the shift register 10 and the start bit detection circuit resumes monitoring the state change of the transmission line 8 again.

Subsequently, in the T6 phase, the host device 1
When the word is written into the shift register 2, the least significant bit of the shift register 2 changes from logic 1 to logic 0 and becomes a start bit.

Thereafter, as in the case of the first word, data is sequentially transmitted from the T7 phase to the T9 phase.

In this way, asynchronous data transmission with one start bit is performed.

Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. In this embodiment, the bit length of one word of the transmission data can be arbitrarily set within a range of 3 bits to 5 bits.

A bit length register 116 and a bit length register 117 for holding the number of bits are added to both the transmission side and the reception side. The transmission clock generation circuit 103 and the reception clock generation circuit 111 Output clock.

Shift register 102 and shift register 1
10 corresponds to the maximum length of the transmission data, and can be 6 bits or 5 bits, respectively.

Further, the host device 101 on the transmitting side fixes the least significant bit position of the data to be written into the shift register 102 regardless of the bit length of the transmission data. Conversely, the host device 109 on the receiving side stores the shift register 11
The circuit configuration is such that the most significant bit position of 0 is read out as fixed.

With the above configuration, arbitrary data of 3 to 5 bits can be transmitted and received. Further, by following this embodiment, a configuration in which the data bit length is extended to 5 or more can be easily realized.

Next, as a third embodiment of the present invention, a description will be given of an asynchronous serial data transmission apparatus of the present invention capable of mutually transmitting and receiving with a conventional start-stop synchronous apparatus.

First, the transmission side will be described. In the first embodiment shown in FIG.
As the shift input to the most significant bit of the data, a value having the polarity of the stop bit in the start-stop synchronization method is fixedly input, and one clock is added to the transmission clock to make four clocks, thereby transmitting data of the start-stop synchronization method. I can do things.

Also, on the receiving side, by adding one bit to the shift register and setting the receiving clock to four bits, it is possible to receive data transmitted by the start-stop synchronization method.

[0036]

As a result of adopting the above configuration, the present invention does not require a means for transmitting a stop bit at any bit from the start of data transmission unlike the conventional start-stop synchronization system. Therefore, there is an effect that a transmission / reception circuit can be configured very easily even when the length of one word is variable. Secondly, since only one bit of additional information per data of one word is required for two words of the start-stop synchronization method, there is an effect that data transmission efficiency is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 host device 2 shift register 3 transmission clock generation circuit 4 inverter 5 driver 6 write strobe signal 7 transmission clock 8 transmission line 9 host device 10 shift register 11 reception clock generation circuit 12 start bit detection circuit 13 receiver 14 start bit detection signal 15 reception Clock 101 Host device 102 Shift register 103 Transmission clock generation circuit 104 Inverter 105 Driver 106 Write strobe 107 Transmission clock 108 Transmission line 109 Host device 110 Shift register 111 Receive clock generation circuit 112 Start bit detection circuit 113 Receiver 114 Start bit detection signal 115 Reception Clock 116 bit length register 117 bit length register.

Claims (4)

(57) [Claims] A transmitting unit that adds a start bit to the beginning of each word of transmission data and transmits the last bit of the word to a transmission path; An asynchronous serial device comprising: means for setting the value of the polarity opposite to that of the bit; means for detecting the start bit on the receiving side; and means for removing the start bit from the received data and extracting the data part. Data transmission device. 2. A bit output from a transmission side shift register for bit-shifting data written in parallel from the transmission side host device from an upper order to a lower order in response to a transmission clock in series in response to a reception clock. An asynchronous serial data transmission device that receives data at a receiving-side shift register and writes the data in parallel to a receiving-side host device, wherein the inverted output of the transmitting-side shift register is written in synchronization with the writing. A start bit, and the written data is sequentially output in response to the transmission clock, and a bit that maintains the output state at that time after the transmission clock is stopped is added to the lowest order. Item 2. The asynchronous serial data transmission device according to Item 1. 3. The transmission side and the reception side are provided with a bit length register capable of setting a bit length of data transmission from each host device, wherein the transmission clock and the reception clock are output by the same number as the bit length, and 3. The transmission side shift register is shifted to the least significant bit side and the parallel writing is performed, and the reception side shift register is configured to receive the same number of bits as the bit length in a transmission path. An asynchronous serial data transmission device as described. 4. A fixedly input value having a polarity of a stop bit in an asynchronous system as a shift input to a most significant bit of the transmission side shift register, and adding only one clock, and One bit is added to the reception side shift register and the reception clock is set to 1
3. The asynchronous serial data transmission device according to claim 2, wherein the transmission and reception can be performed mutually with a data transmission device of an asynchronous system by adding only one.