JP2912508B2 - Method of manufacturing vertical MOS transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical MOS transistor, particularly a vertical MOS transistor having a high withstand voltage and low on-resistance for power use having a trench structure, and to an improvement in a method of manufacturing the same.

[0002]

2. Description of the Related Art Some vertical MOS transistors are shown in FIGS.

FIG. 8 is a schematic sectional view of a VMOS in which a V-shaped groove is formed in a gate portion. An N ^-- type epitaxial layer 22 is formed on the surface of an N ⁺ -type substrate 21, and a P-type epitaxial layer 22 is formed on the surface.
Diffusion layers 23 and 23-1 are formed. The left P-type diffusion layer 23-1 is for a guard ring. A plurality of regions of N ⁺ -type diffusion layers 24 and 2 are provided on the surface of P-type diffusion layer 23 on the right side.
4 are formed. Each of the N ⁺ -type diffusion layers 24 has a V-shaped groove 2 reaching the N ⁻ -type epitaxial layer 22.
5, 25... Are provided. An oxide film 26 such as SiO ₂ is formed on the entire surface.
7 is deposited to form a gate electrode and a source electrode, and become a gate terminal G and a source terminal S. A metal film 28 is also deposited on the back surface, and a drain electrode is formed.
Becomes

FIG. 9 is a schematic sectional view of a DMOS having a double diffusion structure. An N ^-- type epitaxial layer 22 is formed on the surface of an N ⁺ -type substrate 21, and a plurality of P-type diffusion layers 2 are formed on the surface.
3, 23-1 are formed. Left P-type diffusion layer 23
-1 is for a guard ring. On the surface of the right P-type diffusion layer 23, a plurality of N ⁺ -type diffusion layers 24 are formed by double diffusion. A polysilicon layer 29 buried in an oxide film 26 such as SiO ₂ is formed so as to extend over the N ⁺ -type diffusion layers 24 formed on the surfaces of the adjacent P-type diffusion layers 23, 23, thereby forming a gate. The whole surface is an oxide film 26
Drill holes in necessary places covered with
A source electrode is formed. A metal film 28 is also deposited on the back surface to form a drain electrode. Each electrode becomes a gate terminal G, a source terminal S, and a drain terminal D.

The above-mentioned VMOS and DMOS are usually
Each has a multi-cell structure in which a large number of FETs are connected in parallel within the device.

FIG. 10 is a schematic sectional view of a TDMOS having a gate of a trench structure. An N ^-- type epitaxial layer 22 is formed on the surface of an N ⁺ -type substrate 21, and a P-type diffusion layer 23 serving as a well diffusion layer and an N ⁺ -type diffusion layer 24 serving as a source diffusion layer are formed on the surface by double diffusion. I do. A plurality of trenches 30 are formed from the surface, and an oxide film 26 is formed.
Is formed, a polysilicon layer 29 for a gate is buried, an oxide film 26 is formed on the entire surface, holes are formed in necessary places, a metal film 27 is deposited on the surface, and a source electrode and a gate electrode are formed. A terminal S and a gate terminal G are provided. A metal film 28 is also deposited on the back surface to form a drain electrode, which becomes a drain terminal D. A part of the source electrode reaches the P-type diffusion layer 23, and the gate electrode is connected to the buried polysilicon layer 29 through the oxide film 26.

The VMOS forms a V-shaped groove, which makes it difficult to miniaturize it. The DMOS, if miniaturized, increases the resistance between wells, making it difficult to reduce the on-resistance.

TDMO for miniaturization and low on-resistance
S is being used.

[0009]

SUMMARY OF THE INVENTION TDM having a trench structure
OS is advantageous for miniaturization and low on-resistance, but since the trench cannot be formed deeply, the P-type diffusion layer 2
It is necessary to reduce the well diffusion of No. 3 and it is difficult to increase the breakdown voltage, and the process is complicated.

An object of the present invention is to reduce the on-resistance of a MOS transistor having a trench structure, increase the withstand voltage, and further simplify the process.

[0011]

In the vertical MOS transistor of the present invention, a deep diffusion layer immediately below the source portion and a guard ring at the periphery of the chip are formed at the same time to achieve a high withstand voltage, and to perform well diffusion and source diffusion. Is performed over the entire main surface of the semiconductor substrate by ion implantation and thermal oxidation, and then unnecessary well diffusion and source diffusion around the chip are removed when forming a gate trench. Further, the contact hole of the source and the contact hole of the gate are simultaneously formed by etching, thereby simplifying the process.

[0012]

The curvature of the well is increased by deepening the diffusion of the second conductivity type diffusion layer below the well diffusion layer stacked with the source diffusion layer, and a guard ring is arranged around the chip. This promotes the extension of the depletion layer near the semiconductor surface, alleviates the electric field, and increases the breakdown voltage. Moreover, since the well diffusion and the source diffusion are performed on the entire main surface, photoetching in this step becomes unnecessary,
Furthermore, by forming the gate contact hole at the same time as the formation of the source contact hole, the number of steps can be significantly reduced compared to the conventional MOS transistor having a trench structure.

[0013]

FIG. 1A is a plan view of an embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA 'of FIG. 1A.
In FIG. 1A, the electrode wiring on the surface of FIG. 1B is omitted for easy understanding of the etching shape and the diffusion shape of the semiconductor substrate.

[0014] In FIG. 1 (a) and 1 (b), on the surface of the N ⁺ -type semiconductor substrate 1, N ^- -type epitaxial layer 2 is formed, further, on the surface thereof was laminated in a network form , And N-type source diffusion layers 6, 6,... Under the well diffusion layer 5 and the guard ring portion, P-type diffusion layers 14, 14, which are deep diffusion layers, are formed in advance. However, the upper part of the P-type diffusion layer 14 in the guard ring portion is cut off. The trench formed between the P-type diffusion layers 14 is provided with a polysilicon layer 4 serving as a gate buried in an insulating layer made of an oxide film 17.

A sidewall 7 made of polysilicon is formed at the boundary between the guard ring portion and the source portion.

The surface is covered with an oxide film 17 and a PSG film 8,
Holes are made in necessary places, metal films 18 and 19 are deposited to form gate electrodes and source electrodes, and gate terminals G and source terminals S are provided. The source electrode reaches the well diffusion layer 5, and the gate electrode reaches the polysilicon layer 4.

A drain terminal D is formed by depositing a metal film 20 on the back surface to form a drain electrode.

FIGS. 2 to 7 are schematic cross-sectional views showing the steps of manufacturing the MOS transistor having the structure shown in FIGS. 1 (a) and 1 (b).

As shown in FIG. 2, for example, antimony (Sb), which is an N-type impurity, is added to about 7 × 10 ¹⁸ atoms / cm ^3.
After growing an epitaxial layer 2 containing phosphorus (P), which is also an N-type impurity, at a concentration of about 3 × 10 ¹⁴ atoms / cm ³ on the N-type silicon substrate 1 having a concentration of about 45 μm, Boron (B), which is a P-type impurity, is diffused to a diffusion depth of 5 to 6 μm in a guard ring portion around the chip to form P-type diffusion layers 14. The entire surface is covered with oxide film 13.

Next, as shown in FIG.
Is once stripped, an oxide film 15 of about 150 to 300 ° is uniformly formed on the wafer surface, and then boron (B) is doped with, for example, an acceleration voltage of 50 keV and a dose of 5 × 10 ¹³ ions / cm ^3.
Then, arsenic (As) is continuously implanted at an acceleration voltage of 80 keV and a dose of 5 × 10 ¹⁵ ions / cm ³ , for example.

Next, as shown in FIG. 4, when driving is performed by thermal diffusion so that the diffusion depth of boron becomes 1.5 to 1.8 μm and the diffusion depth of arsenic becomes 0.3 to 0.5 μm,
A well diffusion layer 5 and a source diffusion layer 6 are formed over the entire surface. Thereafter, a nitride film 3 is deposited on the entire surface, and a well-known photolithography technique is used.
As shown in (a), openings are formed in a mesh shape, and after the nitride film 3 is etched, reactive ion etching is performed using a mixed gas of carbon tetrachloride (CCl ₄ ) and oxygen (O ₂ ) to form a source portion and Are formed in the epitaxial layer 2 between the P-type diffusion layers 14, 14... Of the gate wiring portion. At this time, a part of the epitaxial layer 2 and a part of the P-type diffusion layer 14 above the guard ring part, and also unnecessary parts of the well diffusion layer 5 and the source diffusion layer that are extended are removed. An oxide film 17 is formed on the entire surface including the periphery of the groove 16 so as to have a thickness of about 600 °. Then, a doped polysilicon layer 4 is formed on the entire surface to a thickness of about 2.5 μm. This also penetrates into the grooves 16, 16.

Next, as shown in FIG. 5, carbon tetrachloride (CC
Reactive ion etching is performed using a mixed gas of l ₄ ) and sulfur hexafluoride (SF ₆ ), and the polysilicon layer 4 is etched until the nitride film 3 appears. At this time, if the depth of the groove 16 is set to an appropriate value, the polysilicon layer 4 in the portion of the groove 16 is thick, so that the polysilicon layer in the portion of the groove 16, 16... Similarly, polysilicon sidewalls 7 are formed at the boundary between the portion where the epitaxial layer around the chip is etched and the portion where the epitaxial layer in the source portion is not removed. This side wall 7 prevents disconnection of the resist, electrodes and the like in the subsequent steps. Thereafter, local oxidation is performed, and the nitride film 3 is peeled off. The surface is again covered with oxide film 17.

Next, as shown in FIG. 6, a PSG film 8 is formed on the entire surface by deposition, and a dicing line portion 9, a guard ring portion contact hole 10, a source portion contact hole 11, a gate portion contact hole 12, and the like are formed. At the same time, it is formed by reactive ion etching. At this time, the source portion contact hole 11 needs to be etched so that the thickness of the N ⁺ portion of the source diffusion layer 6 exceeds 0.3 to 0.5 μm. As shown in FIG. 5, since the thickness of the local portion is smaller than that of the other portions by the thickness of the local oxidation, by appropriately selecting the type, flow rate, and temperature of the gas, the source portion contact hole is deep and the other portions are shallow. Can be etched.

Finally, as shown in FIG. 7, metal films 18 and 19 such as an Al-Si film are formed on the front surface by vapor deposition to form a gate electrode and a source electrode, and on the back surface, for example, Al-Mo-Ni. A metal film 20 such as a film is formed by vapor deposition to form a gate electrode, and a gate terminal G, a source terminal S, and a drain terminal D are provided as shown in FIG.

In the examples shown in FIGS. 2 to 7, the number of well diffusion layers 5 is different from those in FIGS. 1A and 1B.

[0026]

According to the present invention, although the trench structure has a well diffusion layer as shallow as 1.5 to 1.8 μm, the source diffusion layer
Since there is a deep P-type diffusion layer 14 of 5 to 6 μm below the center of the semiconductor device, when a voltage is applied between the drain and the source, a depletion layer extends from the deep P-type diffusion layer 14 so as to cover the trench portion. Since the curvature of the depletion layer is determined by the deep diffusion layer and the guard ring is arranged at the periphery of the chip, the extension of the depletion layer near the chip surface is promoted, so that a high breakdown voltage can be achieved.

Further, since the well diffusion layer and the source diffusion layer are formed by ion implantation and thermal diffusion, it is not necessary to use photoetching, and the formation of the contact holes in the source section is made by forming the contact holes in the guard ring section and the gate wiring section. Further, since the process can be performed at the same time as the formation of the dicing portion, the process can be greatly reduced, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1A is a plan view of one embodiment of the present invention,
(B) is an AA 'sectional view thereof.

FIG. 2 is a schematic sectional view showing one step of an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of one step of an embodiment of the present invention.

FIG. 4 is a schematic sectional view of one step of an embodiment of the present invention.

FIG. 5 is a schematic sectional view of one step of an embodiment of the present invention.

FIG. 6 is a schematic sectional view showing one step of an embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of one step of an embodiment of the present invention.

FIG. 8 is a schematic sectional view of a conventional VMOS transistor.

FIG. 9 is a schematic sectional view of a conventional DMOS transistor.

FIG. 10 is a schematic sectional view of a conventional TDMOS.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Epitaxial layer 3 Nitride film 4 Polysilicon layer 5 Well diffusion layer 6 Source diffusion layer 7 Side wall 8 PSG film 10 Guard ring part contact hole 11 Source part contact hole 12 Gate wiring part contact hole 13, 15, 17 Oxidation Film 14 P-type diffusion layer 16 groove

Claims (2)

(57) [Claims] And 1. A process of forming a first conductivity type deep diffusion layer of the plurality of second conductivity type source region and the guard ring portion of the semiconductor substrate surface, and the impurity of the first conductivity type on the surface A step of forming a well diffusion layer and a source diffusion layer by ion implantation of impurities of a second conductivity type and thermal diffusion; and forming a trench in a gate portion by etching, and at the same time, unnecessary well diffusion layers and source diffusion layers in a chip peripheral portion. method for manufacturing the vertical type MOS transistor you <br/>; and a step of leaving removing the guard-ring portion and. 2. A trench which is deeper than a diffusion depth of a source diffusion layer and is shallower than a diffusion depth of a well diffusion layer as a source part contact hole and a trench which penetrates an insulating film and reaches a gate as a gate part contact hole are simultaneously etched. 2. The method for manufacturing a vertical MOS transistor according to claim 1, further comprising a step of forming the MOS transistor.