JP2913184B2 - Automatic exposure equipment for digital copiers - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an automatic exposure apparatus for a digital copying machine.

[Conventional technology]

2. Description of the Related Art In a digital copying machine, an output of an image signal for forming a copy image is required to have an appropriate output value corresponding to the density of the background of the image.

For this reason, digital copiers are equipped with automatic exposure equipment (hereinafter AE).
Automatic exposure processing (so-called device) for detecting a peak value (white level) of a background detection area provided in a copy image area and setting an output of an image signal to an appropriate output value based on the peak value. Background removal (hereinafter referred to as AE processing) is performed.

FIG. 11 shows an AE circuit used for conventional AE processing,
The image signal of the background detection area is input to the non-inverting input terminal of the operational amplifier 1, and the image signal is charged to the capacitor 2 connected between the output terminal and the ground of the operational amplifier 1. Since the output terminal of the operational amplifier 1 is connected to the inverting input terminal, only a signal larger than the image signal charged to the capacitor 2 is output from the output terminal of the operational amplifier 1 and charged to the capacitor 2.

Accordingly, the peak value signal is taken out as a reference signal ( _Vref ) from the output terminal of the operational amplifier 3 whose non-inverting input terminal is connected to the output terminal of the operational amplifier 1, and the output value of the image signal is obtained based on this reference signal. AE processing is performed after setting.

[Problems to be solved by the invention]

Since a digital copying machine can set a copy magnification as large as, for example, 4 to 8 times, it is often the case that only one copy of a document is copied.

In a conventional AE device, a background detection area is provided within the size of a document, and AE processing is performed based on the image signal of the background detection area. A desired copied image may not be obtained due to different processing standards.

An object of the present invention is to set a background detection area based on a document size, a transfer paper size, and a copy magnification, and to perform an optimum background processing so as to obtain a high-quality copy image by using the background detection area. [MEANS FOR SOLVING THE PROBLEMS] In order to achieve the above object, the present invention provides at least a preset background detection area in an image signal from a document. A reference signal is calculated on the basis of the image signal from the digital camera, and the image signal is A / D-converted to a predetermined output in accordance with the reference signal. The apparatus has a background detection area setting means for setting the background detection area based on the size, transfer paper size, and copy magnification.

[Action]

In the present invention, the optimal background detection area is set by the background detection area setting means based on the document size, the transfer paper size, and the copy magnification. Then, appropriate background processing is performed using the background detection area so as to obtain a high-quality image.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

 First, the overall configuration and operation of the embodiment will be described.

FIG. 1 is a block diagram showing the overall configuration of an embodiment, in which 5 is an AD converter, 6 is a gate region selection circuit, 7a and 7b are peak hold circuits, 8 is a ROM1, and 9 is an average data generation circuit. , 10 is a selector, 11 is a latch, 12 is
ROMs 2, 13, and 14 are selectors, 15 is a ROM 3, 16 is a latch, 17 is an adder, 18 is a selector, 19 is a DA converter, and 20 is a buffer.

As shown in FIG. 1, an image signal from a document is input to an AD converter 5, which has a buffer.
Reference signal _Vref is input from 20. Therefore, the image signal is AD-converted to a predetermined output by the AD converter 5 based on the reference signal _Vref .

The AD converter 5 is connected to a peak hold circuit 7a and a gate area selection circuit 6 for selecting a background detection area. The output terminals of the gate area selection circuit 6 have a peak hold circuit 7b and an average data generation circuit. 9 is connected. For this reason, the peak value in one line is detected by the peak hold circuit 7a from the image signal AD-converted by the AD converter, and the peak value corresponds to the background detection area set in advance by the gate area selection circuit 6. Is selected, and a peak value from the background detection area is detected from the output by the peak hold circuit 7b.

The peak values are respectively input from the peak hold circuits 7a and 7b to the ROM 18, and the ROM 18 calculates the gain A used for the calculation of the reference signal _Vref based on the peak values.

The average data generating circuit 9 is controlled by the selector 14 and calculates the average value of the image signal from the background detection area in a different manner according to the character image or the photographic image. A selector 10 is connected to the average data generating circuit 9, and either the character image average data or the photograph image average data is selected by the selector 10, and the selected data is sent to the latch 11 connected to the selector 10. Is entered.

A ROM 212 is connected to the latch 11, and a ROM 3 is connected to the ROM 212.
15 output signals are input, and the ROM 212
The increase or decrease at t is calculated. Selector 13 in ROM 212
The output of the ROM 212 is selected by the selector 13 between an output corresponding to a character image and an output corresponding to a photographic image, and the selected output is sent to an adder 17 connected to the selector 13. After being input and further subjected to addition processing via a latch 16 connected to the adder 17, the input is input to a ROM 315 connected to the latch 16.

The gain A calculated by the ROM 18 is input to the ROM 315, and the reference signal data E _ref is calculated based on the output of the adder 17 and the gain A input via the latch 16 in the ROM 315. _{The ref} is input to the selector 18 and the ROM 212.

A fixed value is input to the selector 18, and the selector 18 selects the reference signal data _Eref and inputs it to the DA converter 19 in the automatic exposure mode (AE mode). A buffer 20 is connected to the DA converter 19, and the buffer 20
Is connected to the AD converter 5, and the DA converter 19
The reference signal data E _ref obtained by DA conversion at step (1) is input to the AD converter 5 via the buffer 20 as the reference signal V _ref .

FIG. 2 is an explanatory diagram of a copying machine to which the present invention is applied. In FIG. 2, reference numeral 21 denotes a document, reference numeral 22 denotes a contact glass, light sources 24 and 25 are mirrors, reference numeral 27 is a lens, reference numeral 28 is a CCD, reference numeral 29 is an amplifier, 5 is an AD converter, 19 is a DA converter, 20 is a buffer, 30 is an image processing unit, 33 is an optical control unit, 38 is an image reading unit, and S is a document reference line.

As shown in FIG. 2, a contact glass 22 is arranged on a document table 36, a document 21 to be copied is placed on the contact lens 22, and a reference white plate 23 is placed on an end of the contact glass 22. Installed.

A light source 24 is disposed so as to be able to scan on the document 21 in close proximity to the contact glass 22, and the light 21 from the light source 24 is
Is reflected by the mirror 25, focused by the lens 27, and input to the CCD.

An image signal corresponding to the image of the original 21 is obtained by the CCD 28, and this image signal is input to the AD converter 5 and AD-converted, and is input to the image processing unit 30 having the original size detection unit 30a, and the image processing unit The output signal from 30 is input to the plotter, and a copied image is formed by the plotter.

The operation of generating the reference signal in the loop of the AD converter 5, the image processing unit 30, the DA converter 19, and the buffer 20 is as described with reference to FIG.

The optical controller 33 including the CPU 33a includes a lamp driver 31
The lighting control of the light source 24 is performed by the lamp driver 31, and the filter 26 can be inserted into the optical path between the mirror 25 and the lens 27 by the solenoid 32 connected to the optical control unit 33. ing.

Also, a drive motor 35 is connected to the optical control unit 33, and the optical control unit 33 and the sensor 34, the image processing unit 30, the operation unit 37, and the plotter are configured to be able to exchange signals with each other.

Next, the gate area selection by the background detection area setting means in the embodiment will be described in detail.

FIG. 3 is an explanatory view of selecting a gate region in the embodiment. In FIG. 3, reference numeral 22 denotes a contact glass, and reference numeral 40 denotes a background detection region serving as a gate region.

In the embodiment, the gate width in the main scanning direction is D ₀ for the document width, T for the copy magnification, D _{1 for} the transfer paper width, and X for the margin.
_OS and the fixed gate width are set as X _IN −X _ON as follows.

(A) When the document size is clear (1) If D ₀ × T> D ₁ , the value obtained by subtracting X _OS from the transferred space D ₁ / T in the document is set as the gate width.

(2) When it is D ₀ × T ≦ D _1, and the gate width D ₀ -X _OS.

(B) When the document size is unknown (1) If T <1, fixed gate width X _IN regardless of magnification
−X _ON is the gate width.

(2) If T> 1, a value obtained by shortening the fixed gate width X _IN −X _ON according to T is set as the gate width.

(3) The gate width (X ₁ −X ₀ ) shown in FIG.
If the width (X ₀ + X ₁ ) obtained by adding X ₀ is larger than the transfer paper width D ₁ , the gate width is set as in (A) (1).

FIG. 4 is a block diagram showing a configuration of a circuit for generating a gate signal applied to the gate area selecting circuit of the embodiment.
In the figure, reference numeral 30a denotes a document size detection unit, 37 denotes an operation unit, 41
Is a plotter, 33a is a CPU, 42 is a selector, 43a and 43b are latches, 44a and 44b are digital comparators, and 45 is an AND circuit.

As shown in FIG. 4, the CPU 33a includes an original size detecting unit 30.
a, it is connected to the operation unit 37 and Purotsuta 41, respectively, the CPU33a from these, the document width D _0, magnification data T, the transfer paper width data D ₁ are input, respectively.

Based on these data, the CPU 33a creates address data X ₀ , X _{1 of the} background detection area, and these address data are input to the select 42 connected to the CPU 33a. The selector 42, latch 43a, 43b are connected, Yotsute address data X ₁ to the selector 42 latches 43a
Is input to the address data X ₀ is input to the latch 43b.

The output terminal of the latch 43a is connected to the P terminal of the digital comparator 44a, the output terminal of the latch 43b is connected to the Q terminal of the digital comparator 44b, and connected to the Q terminal of the digital comparator 44a and the P terminal of the digital comparator 44b. Is input with pixel counter data.

In the digital comparators 44a and 44b, the input of the P terminal is Q
The logic value of the output signal is “1” when it is larger than the input of the terminal.
Therefore, the AND circuit 45 connected to the digital comparators 44a and 44b outputs a gate signal indicating an address in the background detection area. This gate signal is
As shown in the figure, the data is input to the gate region selection circuit 6.

FIG. 5 is a flow chart of the operational behavior of the address data of the background detection region in Example, copy magnification T is input in step S1, the process proceeds to step S3 transfer sheet width data D ₁ is excisional at step S2. In step S3, or determined whether the document size can be detected is made, the determination in step S3 is YES the detection of document size (width) is performed in step S4, the document width D ₀ proceeds to step S5 Set.

Proceeding from step S5 to step S6, it is determined whether D ₀ × T> D ₁ is satisfied among the document width D ₀ , the magnification T, and the transfer paper width D ₁ . If the determination in step S6 is YES,
Proceeding to step S7, the address data is calculated by the following operation.
x ₀ and x ₁ are calculated. In the equation, Δx is a preset fixed margin regardless of the magnification, and generally a value of 0 to 5 mm is used.

When the judgment at step S6 is is NO, the process proceeds to step S8, Yotsute address data x ₀ to the next operation, x ₁ is calculated.

If the determination in step S3 is NO, the process proceeds to step S9, where a determination of T> 1 is performed. If the determination is YES, the process proceeds to step S10, and the address data x is calculated by the following calculation.
_0, x ₁ is calculated.

If the determination in step S9 is NO, the process proceeds to step S11, where x ₀ = x _0N , x ₁ = x _1N and fixed values are set in the address data. Step S10 or Step S11 to Step S12
The process proceeds, a determination is made of the step S12, _{D 1> x 0 + x 1} ,
Proceed to step S7 if the determination is ON, the calculation of the address data x _0, x ₁ as described above is performed.

In the embodiment, as described above, the average value calculation of the image signals from the background detection area is performed by changing the number of image signals to be averaged in the case of a character image and a photographic image.

 This average value calculation will be described in detail.

FIG. 6 shows a circuit for calculating the average value of the image signal of the background detection area in the embodiment. In FIG.
46bm-1 is an adder, 47 is a latch, 10 is a selector, and 11 is a latch.

The image signals (8 bits) output from the gate area selection circuit 6 are input to the adders 46bo to 46bm-1.
bm-1 is connected to a latch 47, a selector 10 is connected to the latch 47, and a latch 11 for calculating an average value and extracting an image signal is connected to the selector 10.

The selector 14 selects a timing signal for setting the average number of image signals by switching between a character image mode and a photographic image mode. In this case, the number of image signals to be averaged is set to 2 'and 2 ^{l + k} for simplicity.

The average value calculation data is input to the latch 47, and the character image mode is set to the photographic image mode. The selector 10 selects the bit positions of the adders 46bo to 46bm-1 corresponding to the number of image signals to be averaged, and sets the necessary data. Is input to the latch 11.

Next, in the embodiment, as described above, the image signal whose average value is calculated and the current reference signal V _ref of the AD converter 5 are used.
To calculate a time constant and output a new reference signal.

The calculation of the new reference signal in the embodiment will be described in detail.

FIG. 7 shows a reference signal operation circuit of the embodiment. In FIG. 7, reference numeral 12 denotes a selector for ROM 213, reference numeral 15 denotes a latch for ROM 316, and reference numeral 17
Is an adder, 50 is an inverting gate, and 51 is a selector.

As shown in FIG. 7, the average value data E _in (image signal calculated by the average value) and the reference signal data E _ref calculated by the ROM 315 are input to the ROM 212, and the input voltage from the DA converter 19 is input to the ROM 212. Assuming that the data value of the output voltage V ₀ output at O is E ₀ , the following calculation of the output data E _OUT is performed on the character image.

(1) When E _in > E _ref + E ₀ However, E ₁ is (maximum reference signal> E ₀ of E ₁ ≧ AD converter) fixed value, Delta] t is the time corresponding to 2 ¹ lesser of number average image signal (Delta] t = pixel period × 2 ^l) (2) E _{When in} = E _ref + E ₀ , E _OUT = 0 (8) (3) When E _in <E _ref + E ₀ However, τ ₁ << τ _{2 In} this case, the format of the output data E _OUT is as shown in Table 1.

In this way, in the embodiment, Δ
An excessive increase / decrease value at time t is output.

The output data is calculated in a fixed time Δt, and the average number of image signals is different between a character image and a photographic image.

Output data E ' _OUT for a photographic image is performed as follows, with K as a constant.

(1) For E _in <E _ref + E ₀ (2) When E _in = E _ref + E ₀ E ' _OUT = 0 (3) When E _in <E _ref + E ₀ Assuming that τ ₁ , τ ₂ >> Δt · 2K, equations (10) and (11) are expressed by equations (12) and (13), respectively.

Thus, since E _'OUT is obtained if multiplied by the E _OUT 2 ^k, it may in circuit manner to Kbit shifting E _OUT.

In addition, since the output data takes a positive or negative value, if D ₇ = 0, the data is added as it is based on the value of D ₇ used as a sign bit, and if D ₁ = 1, the two's complement is added. And then add (actually add the reciprocal and 1 LSB).

For this reason, in the embodiment, a selector 13 is connected to the ROM 212, and the selector 13 is switched between a character image and a photographic image to select the _unshifted output data E _OUT and the shifted output data E ′ _OUT. The variation of the time constant due to the difference in the number of image signals to be averaged is eliminated.

An inverting gate 50 is connected to the selector 13, and an exclusive (exclusive) OR circuit is provided in the inverting gate 50 to take data as it is according to D ₇ = 0 and D ₇ = 1, or The reciprocal is performed by a sieve OR circuit.

As described above, the output data E _OUT2 from the inverting gate 50 is an increase / decrease value at Δt or Δt · ^2k time, and has data equal to or less than 1 LSB of the reference signal data.
Therefore, an accurate calculation is performed for the time constant of τ ₁ , τ ₂ >> Δt.

Therefore, the data E _ref0 should have a data Hbit from MSB of the reference signal data E _ref to the LSB of the output data E _ref2. In the case of adding the output data E _OUT2 data E _ref0, since the output data E _OUT2 has to take reciprocal If it is negative, the same output data E _OUT2 and data E _ref0 bit
Must be a number.

For this reason, in the embodiment, the selector 51 is connected to the inversion gate 50, and the difference between the data E _ref0 and the output data E _OUT2 is calculated.
The bit is supplemented by the selector 51, and when the reciprocal is taken, the bit of the difference is output from the selector 51.

The adder 17 is connected to the inversion gate 50 and the selector 51, and the Hbit obtained by the inversion gate 50 and the selector 51 is
And data Delta] E _ref of, and data E _ref0 from latch 16 is added. At the time of this addition, when D ₇ = 1, the data ΔE _ref is the inverse, and the carry INCI of the adder 17 is used.
Is set to “H”, and the subtraction is performed by adding the data ΔE _ref and the data E _ref0 .

RON315 is connected to adder 17 and data is stored in ROM315.
In the upper 8 bits E _ref1 of E _ref0 , the gain A
And new reference signal data E _ref is obtained as in the following equation.

E _ref = A (E ₀ + E _ref1 ) −E ₀ (14) In the AE mode in the AE mode by the selector 18 in FIG.
4) The reference signal data E _{ref of the} equation is selected and the DA converter 1
Entered in 9. Except in the AE mode, a fixed value is selected by the selector 18 and input to the DA converter 19.

FIG. 8 shows a reference signal output circuit in the embodiment, in which 19 is a DA converter, 55 and 56 are operational amplifiers, and the reference signal _Vref obtained at the output terminal of the operational amplifier 56 is given by the following equation.

If R ₄ = R _{5 in} equation (15), the following equation is obtained.

Here, the maximum value of the reference signal of the AD converter is V _ref (A / D
MAX), the following equation must be satisfied.

In the equation (17), B is a margin constant, which is usually about 0.9 to 0.95 times. V ₀ is a fixed value V _ref when not in the AE mode.
The value is about 0.4 to 0.5 times (N).

Capacitor C ₀ in Figure 8, is inserted to prevent ringing of the output is set to satisfy the following equation.

As described above, in the ROM315, but is multiplied by the gain A in the data E _ref1, this is done in order to compensate for the uneven illuminance of the light source.

FIG. 9 is an explanatory diagram showing illuminance unevenness of the light source (fluorescent lamp) of the embodiment, and the illuminance curve I of the light source has uneven illuminance. Accordance connexion, if you set the density detection gate between _1, l _2, is required illumination compensation and thus is adjusted by multiplying a gain A in the data E _ref1 in ROM315.

FIG. 10 is commonly provided in digital scanners
The AGC circuit detects the peak value of the background detection area when the standard white board 23 of FIG. 2 is read, and feeds back the peak value to the impedance 59 connected between the inverting input terminal and the output terminal of the operational amplifier 56. ing.

By doing so, the signal V _IN input from the output terminal of the operational amplifier 56 to the AD converter 57, and V _IN = C · V _ref C as margin (about 0.95), to match the substantially V _ref I have.

However, in this case, the peak value MAX1 of the background detection area and 1
The following equation must be satisfied between the peak values MAX0 in the line.

For this reason, conventionally, when the expression (19) is not satisfied, a fluorescent lamp which is a light source is mounted on the opposite side (a so-called register mark).

The embodiment solves this difficulty, and detects the peak value MAX1 in the background detection area and the peak value MAX0 in one line as described above, and the AGC detects the peak value MAXO in one line.
You are using Then, in the AE mode, using these peak values MAX1 and MAX0, a gain A that satisfies the following equation is calculated as R
Calculated by OM18.

C · MAX0 = A · MAX1 (20) The reference value data E _ref is calculated in the ROM 315 using the gain obtained in this manner, and based on the reference value data E _ref , the image signal is the output value of V _in is set.

In the embodiment, the background detection area is set based on the document size, the transfer paper size, and the copy magnification in this manner,
An optimum reference value signal is created based on the peak value MAX1 of the background detection area and the peak value MAX0 of one line, and a predetermined image signal subjected to background processing (so-called background removal) based on the reference value signal. The output is set and a high quality copy image is formed.

〔The invention's effect〕

As described above in detail, according to the present invention, the background detection area is set based on the document size, the transfer paper size, and the copy magnification, the optimum background processing is performed, and a high-quality copy image is formed.

[Brief description of the drawings]

1 to 9 are diagrams for explaining an embodiment of the present invention. FIG. 1 is a block diagram showing the overall configuration, FIG. 2 is an explanatory diagram of a copying machine to which the present invention is applied, and FIG. FIG. 4 is an explanatory diagram of gate region selection, FIG. 4 is a block diagram showing a gate signal generation circuit,
FIG. 5 is a flow chart of an operation for calculating address data;
FIG. 6 is a block diagram showing a circuit for calculating an average value of an image signal.
FIG. 7 is a block diagram showing a reference signal operation circuit, FIG. 8 is a circuit diagram showing a reference signal output circuit, FIG. 9 is an explanatory diagram showing illuminance unevenness of a light source, and FIGS. 10 and 11 are conventional AEs. FIG. 10 is a block diagram showing an AGC circuit, and FIG.
The figure is a circuit diagram showing an AE circuit. 5 AD converter, 6 Gate area selection circuit, 7a, 7b
Peak hold circuit, 8 ROM1, 9 average data creation circuit, 10, 13, 14, 18 selector, 11, 16 latch, 17 adder, 18 DA converter, 20 buffer, 30 image processing unit , 33 ... optical control unit, 33a ... CPU, 38 ... image reading unit,
40: background detection area, 42: selector, 43a, 43b: latch, 4
4a, 44b: Digital comparator, 46bo to 46bm-1: Adder, 47: Latch, 50: Inverting gate, 51: Selector, 55, 5
6… Op amp.

Claims (1)

(57) [Claims] A reference signal is calculated based on at least an image signal from a predetermined background detection area among image signals from a document, and the image signal is output to a predetermined output in accordance with the reference signal. In an automatic exposure device of a digital copying machine, which is AD-converted and the background processing is performed, the document size,
An automatic exposure apparatus for a digital copying machine, comprising: a background detection area setting means for setting the background detection area based on a transfer paper size and a copy magnification.