JP2914232B2 - Spread spectrum communication system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication system, and more particularly to a spread spectrum communication system for performing high-speed data transmission using a transmission line having a poor transmission environment such as a power line.

[0002]

2. Description of the Related Art In recent years, bus-type networks such as a home bus system (HBS) and a domestic digital bus (D2B) have been proposed with the progress of computerization at home.
However, these networks require a dedicated transmission path such as a coaxial cable or a twisted pair cable, and thus have a problem in laying cables. Therefore, as a means for solving this problem, a communication system in which a power line already laid in a home is used as a transmission path has been considered.

However, an electric light line is originally a line for carrying electric power, and is not suitable for transmitting information due to the influence of noise from various electric devices, abrupt fluctuation of transmission characteristics, jitter, and the like. As a countermeasure, a communication system using spread spectrum communication resistant to noise and fluctuations in transmission characteristics has been proposed.
There is a “spread spectrum communication system and device” disclosed in Japanese Patent No. 252531.

FIG. 8 is a configuration diagram of a transmission section of the conventional spread spectrum communication system. In FIG. 8, the transmission unit is a PN (Pseudo Noise) which is a spreading code.
A code clock generator 70 for generating a code clock (hereinafter referred to as FCK); a PN code generator 71 for generating a PN code; a 15-stage shift register 72;
And 3.

The PN code generator 71 is composed of a five-stage linear feedback shift register, and has an initial value "00000".
Data other than "b" (b indicates a binary number) is set, and an M-sequence code having a code length of 31 chips is generated. This M-sequence code is provided as a spread code (hereinafter referred to as PN0) for transmission data "0", and is supplied to the first input of the selector 73.
This PN0 is an M-sequence code delayed by about half a cycle (15 chips) in the 15-stage shift register 72.
This M-sequence code is used as a spread code (hereinafter referred to as PN1) for the transmission data "1", and is supplied to the second input of the selector 73.

The transmission data has one cycle (31 chips) of the spreading code as one bit, and a selector 7 according to the transmission data.
At step 3, either PN0 or PN1 is selected and output as a spread spectrum signal (hereinafter referred to as an SS signal) to a power line as a transmission path.

Next, FIG. 9 shows a configuration of a receiving section for receiving the SS signal. In FIG. 9, a code clock generator 80 for generating a PN code, a PN code generator 81 for generating the same PN0 as the transmitting unit, and a 15-stage shift register 8
2, correlation integrators 83-0 and 83-1 and comparator 84
, A selector 85, a peak detector 86, and a synchronization control unit 87.

As in the transmission section, PN0 is generated from a PN code generator 81, and PN1 is generated from a shift register 82, respectively. The SS signal is input to correlation integrators 83-0 and 83-1 to calculate the correlation integral between PN0 and PN1, respectively. These correlation integrated values are referred to as CORR0 and CORR1, respectively.
Call.

Then, CORR0 and CORR1 are compared by a comparator 84, and a data value corresponding to the larger PN code is output as demodulated data. That is, CORR0
Is larger, the data "0" is demodulated data, and if the CORR1 is larger, data "1" is demodulated data.

Further, the selector having the larger correlation integration value is selected by the selector 8.
5 to a peak detector 86, which detects the peak value and the peak position.
Control the code clock generator 80 so that the PN code is not out of synchronization.

[0011]

However, in the conventional spread spectrum system, when trying to increase the data rate, the frequency of the spread code increases in proportion to it,
There is a disadvantage that the spreading bandwidth is increased. For example, at a data rate of 9600 bps, the spread code chip 3
In the case of spreading with the M-sequence code of 1, the code clock is 297.6 kHz, which is 31 times that, and the spreading bandwidth is about 600 kHz, which is twice that. If the data transfer rate is doubled under these conditions, the spread bandwidth becomes 1200 kHz, which is 450 kHz, which is the band limit in the case of power line transportation.
Hz.

It is an object of the present invention to provide a spread spectrum communication system in which the data transfer speed is increased by increasing the data transfer amount without changing the code length and spread bandwidth of the spread code. .

[0013]

Spread spectrum communication system according to the present invention SUMMARY OF THE INVENTION A parallel N bit (N is an integer of 2 or more) each corresponding to a combination pattern of 2 ^N as in the 2 ^N spread transmission data of A first spreading code generating means for generating a code, a selecting means for selecting a corresponding spreading code corresponding to each combination pattern of the transmission data and setting a transmission output, and generating a first synchronization spreading code. a first synchronizing <br/> spread code generating means for the first to the selection output of the selection means
A transmitting unit having an adding means for adding and transmitting one synchronization spreading code , a second spreading code generating means for generating 2 ^N spreading codes, and 2 ^{N combinations} patterns of the transmission data 2 ^N correlation integration means for receiving 2 ^N transmission spreading codes respectively corresponding to the above and calculating the correlation integration with the 2 ^N spreading codes of the second spreading code generation means; Means for detecting the largest integrated value of the means, and second synchronization for generating a second synchronization spreading code.
Receiving means for receiving the first spreading code for synchronization,
To calculate a correlation integral with the second synchronization spreading code.
A correlation integration means for synchronization, a means for detecting a phase state of the received spreading code with respect to the second synchronization spreading code based on the integration value for synchronization , Is a pattern corresponding to the maximum value as demodulated data,
In the case of non-coincidence, a judging means for determining demodulated data according to the magnitude of a difference between an integral value corresponding to a pattern shifted by two chips from the pattern corresponding to the maximum value and the maximum value and a predetermined threshold value. And a receiving unit having:

[0014]

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention is as follows.
That, PN of the transmitting side, husband the 2 ^N each combination pattern of the N-bit data s correspondingly are prepared to the 2 ^N PN code, corresponding according to the data pattern of N bits to be transmitted Codes are sent alternatively.

On the receiving side, the correlation integral between the received signal and 2 ^N PN codes is calculated, and the maximum value P
An N-bit pattern corresponding to the N code is used as demodulated data.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a transmitting section of a spread spectrum communication system according to the present invention. In FIG. 1, the transmitting unit includes:
The apparatus includes a code clock generator 1 for generating a spread code clock (hereinafter referred to as FCK), a PN code generator 2 for generating a PN code, a 28-stage shift register 3, and a selector 4.

The output of the code clock generator 1 is connected to the input of the PN code generator 2 and the clock input of the shift register 3, and the output PN0 of the PN code generator 2 is connected to the data input of the shift register 3 and the selector 4 Connected to data input. From the fourth stage of the shift register 3 to 2 every 4th stage
The seven outputs PN1 to PN7 up to the eighth stage are connected to the data input of the selector 4, and the control input of the selector 4 is connected to 3-bit transmission data.

The PN code generator 2 includes a five-stage shift register 5 and an EXOR 6, and the shift register 5
The outputs of the fifth stage and the second stage are input to the first stage of the shift register 5 through the EXOR 6, and constitute a linear feedback shift register. The linear feedback shift register outputs an M-sequence code having a code length of 31 chips.

Next, the operation of the transmitting section of the present invention will be described. First, an M-sequence code is generated from the PN code generator 2 on the basis of FCK, and the M-sequence code is converted to 3-bit transmission data "00
0b "is output to the selector 4 as a spreading code (hereinafter referred to as PN0). Further, through the shift register 3, seven signals every four clocks from PN0 to 4 clocks of FCK to 28 clocks are spread codes corresponding to 3-bit transmission data “001b” to “111b” (hereinafter referred to as “spread codes”). PN1 to PN7) are output to the selector 4.

The eight PN codes PN0 to PN7 are the same M-sequence code, and have a relationship delayed by FCK. From the autocorrelation characteristics of the M-sequence code, since these codes have low cross-correlation characteristics, a data value corresponding to each PN code can be detected by a receiving unit described later.

In the selector 4, PN0 to PN7 are alternatively derived based on the 3-bit transmission data and sent out to the transmission line as a spread spectrum signal (SS signal). In this way, transmission data can be transmitted with a plurality of bits (3 bits in this embodiment) spread at a time.

Next, FIG. 2 shows a configuration of a receiving section for receiving the SS signal from the transmitting section in FIG. In FIG. 2, a receiving unit includes a code clock generator 10 and a PN generator PN0.
A code generation unit 11; a 28-stage shift register 12;
Correlation integrators 13-0 to 13-7, a comparator 14,
Selector 15, peak detector 16, synchronization control unit 17
And

FCK which is the output of the code clock generator 1
Is connected to the input of the PN code generator 11 and the clock input of the shift register 12, and the output (P
N0) is connected to the second input of the correlation integrator 13-0 and the data input of the shift register 12.

Seven outputs (PN1 to PN7) at every fourth stage from the fourth stage to the 28th stage of the shift register 12 are connected to second inputs of the correlation integrators 13-1 to 13-7. The SS signal is connected to first inputs of the correlation integrators 13-0 to 13-7. Correlation integrators 13-0 to 13-7
(Hereinafter referred to as CORR0 to CORR7) are connected to the input of the comparator 14 and the data input of the selector 15.

The output of the selector 15 is connected to the input of the peak detector 16, and the output of the peak detector 16 is connected to the input of the synchronization controller 17. The first output of the synchronization control unit 17 is connected to the input of the code clock
Is connected to the first control input of the selector 15. The output of the comparator 14 is connected to the second control input of the selector 15.

Next, the operation of the receiving section will be described. First, the code clock generator 10
Generates an FCK, and based on the generated FCK, the same eight spreading codes PN0 to PN7 as those of the transmitting unit are generated via the PN code generating unit 11 and the shift register 12.

These spread codes are correlation-integrated with the SS signal by correlation integrators 13-0 to 13-7. The correlation integral is a value obtained by integrating one period of the SS signal and the spread code as shown in Expression 1.

Correlation integral value = (1 / T) ∫ (SS signal) * (spread signal) dt (Equation 1) Here, T is a period of a spread code, and ∫ indicates an integration of 0 to T. Shall be.

FIG. 3 shows the correlation integral output (C) of the correlation integrators 13-0, 13-1,..., 13-7 for the transmission data.
ORR0, CORR1,..., CORR7). In FIG. 3, the correlation integral value corresponding to the transmission data becomes the maximum, and the other integral values become the minimum values. Therefore,
The maximum of CORR0 to CORR7 is detected by the comparator 14, and a 3-bit data pattern corresponding to the maximum PN code can be demodulated as received data. Thus, 3-bit data from "000b" to "111b" can be demodulated.

In order to perform the demodulation correctly in this way, it is premised that the spreading codes of the transmitting unit and the receiving unit are synchronized. Synchronization is divided into two steps: synchronization capture for roughly synchronizing synchronization, and synchronization tracking for preventing synchronization after synchronization capture. For synchronous capture, for example, a sliding search method having a simpler configuration than the conventional one is used.

Before sending transmission data from the transmission unit,
Specific data, for example, “000b” is transmitted for synchronous capture. At this time, the receiver controls the code clock generator 10 via the synchronization control 17 to gradually delay FCK. Then, the selector 15 is controlled, and C of the correlation integrator 13-0 is controlled.
By detecting the peak position of ORR0 with the peak detector 16, synchronization is captured.

Further, regarding the synchronization tracking after the synchronization capture,
The comparator 14 detects the peak position of the correlation integration value that shows the maximum, and the peak detector 16 detects the peak position.
It is possible to determine whether the signal is delayed or advanced with respect to K, and control the code clock of the code clock generator 10 in accordance with the result of the determination to track the synchronization.

As described above, in the spread spectrum communication system according to the present invention, the amount of information can be increased and data can be transmitted at high speed despite the fact that the band of the SS signal does not change from that of the related art.

In order to speed up data, it is necessary to prepare a large number of spread codes corresponding to each data value.
Thus, if the spread code length is the same, the delay amount of the spread code may be reduced as much as possible. As shown in FIG.
In the case of the M-sequence code, the peak width of the correlation integral becomes ± 1 chip. In principle, in order to distinguish the M-sequence code from the delayed M-sequence code, the delay amount may be one chip.

However, in practice, since the peak of the correlation integral value shifts due to the characteristic fluctuation jitter of the transmission line, there is a possibility that the correlation integral value of the spread code having a close delay amount becomes larger. Just judging the magnitude of the value may erroneously demodulate the data. Therefore, a spread spectrum communication system considering such errors will be described.

FIG. 4 shows the configuration of the transmitting section of the spread spectrum communication system. Compared with the transmission unit of FIG. 1, a PN code generator 21 for generating a spread code (called PNS) for synchronization, and an adder for adding a PNS to an SS signal selected by a selector 24 based on a transmission data value. 25 have been added.

Further, the transmission data is expanded from 3 bits to 4 bits, and accordingly, the shift register 23 for delaying PN0 becomes 30 stages, and the PN1 to PN are shifted every two stages.
Including the 15 spreading codes up to 15, and PN0, 16 spreading codes corresponding to the transmission data "0000b" and "1111b" on a one-to-one basis are generated.

If a large amount of PN codes are generated with a small delay amount with respect to PN0, the demodulated data may be erroneous in the state described above. Attempting to do so may result in incorrect synchronization. Therefore, a spreading code PNS for newly establishing synchronization is added. PNS is PN0
Since it is desired that the cross-correlation with PN15 is small, this embodiment uses an M-sequence code composed of a linear feedback shift register that inputs the EXOR results of the outputs of the fifth and third stages.

FIG. 5 shows a configuration of a receiving section corresponding to the transmitting section of FIG. Compared with the receiving unit of FIG.
A code generator 31, a correlation integrator 35, a data determination unit 40, and a threshold setting unit 39 serving as a data determination condition are added.

The synchronization of the code clock is performed by controlling the code clock generator 30 via the peak detector 36 and the synchronization control unit 37 based on the correlation integral value (CORRS) of the PNS.

The demodulation of the data is performed by the correlation integrator 34-.
Correlation integrated values CORR0 to CORR15 of 0 to 34-15
Are compared by the comparator 38 to detect a maximum value, a 4-bit pattern corresponding to the PN code of the maximum value is generated, and the 4-bit pattern is correlated with the correlation integral values CORR0 to CORR1.
5 is performed by the data determination unit 40.

Referring to FIG. 6, the data m (0 ≦ m ≦
(15, m is an integer) shows a processing flow of the data determination unit 40 when the correlation integration value CORRm becomes the maximum.
The data determination unit 40 checks the phase information of the PNS SS signal from the synchronization control unit 37 (routine 5).
1). At this time, if the phases match, the data m is output as demodulated data (routine 54).

If the time is late, CORRm
And the difference between the correlation integral CORR (m + 1) of PN (m + 1) two chips behind PNm is compared with the threshold value of the threshold value setting unit 39 (routine 52). If smaller, the demodulated data is set to m + 1 (routine 55). If not, the demodulated data is set to m (routine 54).

Similarly, when the routine proceeds to the routine 51, the difference between CORRm and CORR (m-1) is compared with a threshold value (routine 53). If it is smaller, the demodulated data is set to m-1 (routine 56), and if not smaller, it is set to m (routine 54).

FIGS. 7A and 7B are diagrams showing the state of the phase of the SS signal with respect to the PNS. FIG. 7A shows a state in which both phases match, FIG. 7B shows a state in which the phase of the SS signal is advanced,
(C) shows the state where the phase of the SS signal is delayed.

As described above, the data judgment unit 40 judges the demodulated data based on the correlation integration value indicating the maximum in the comparator 38, the threshold value, and the phase information of the synchronization control unit 37. Accordingly, even if the delay amount of the M-sequence code, which is a spread code, is reduced, demodulation can be performed correctly, and the speed of data transfer can be further increased.

[0049]

As described above, according to the spread spectrum communication system of the present invention, 2 ^N pieces of spreading codes having a small cross-correlation are allocated and spread to N-bit data, and the spread signal and 2 ^N data are spread. By making the data corresponding to the largest spreading code among the correlation integral values with the spreading codes the demodulated data, the data transfer amount can be increased with the same spreading code length and spreading band, and the data There is an effect that data can be transferred at high speed.

Therefore, for example, in the conventional power line carrier,
When spreading is performed using an M-sequence code of 31 chips, the data transfer rate is limited to 9600 bps due to the limitation of the transmission band. Alternatively, the data transfer speed can be increased up to four times.

[Brief description of the drawings]

FIG. 1 is a block diagram of a transmission unit according to one embodiment of the present invention.

FIG. 2 is a block diagram of a receiving unit according to one embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a correlation integral value in a receiving unit according to an embodiment of the present invention.

FIG. 4 is a block diagram of a transmission unit according to another embodiment of the present invention.

FIG. 5 is a block diagram of a receiving unit according to another embodiment of the present invention.

FIG. 6 is an operation flowchart of the data determination unit 40 of FIG. 5;

FIG. 7 is a diagram showing a phase state of an SS signal in a PNS.

FIG. 8 is a block diagram of a transmitter of a conventional spread spectrum communication system.

FIG. 9 is a block diagram of a receiving section of a conventional spread spectrum communication system.

[Explanation of symbols]

1, 10, 30 Code clock generator 2, 11, 32 PN code generator 3, 12, 23, 33 Shift register 4, 15, 24 Selector 13-0 to 13-7, 34-0 to 34-15, 35 Correlation integrator 14,38 Comparator 16,36 Peak detector 17,37 Synchronization control unit 21,31 Synchronization PN code generator 39 Threshold setting unit 40 Data judgment unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) H04B 1/707 H04B 3/54 H04L 7/00

Claims (2)

(57) [Claims] 1. A first spreading code generating means for generating 2 ^N spreading codes respectively corresponding to 2 ^{N combinations} of transmission data of parallel N bits (N is an integer of 2 or more), Selection means for selecting a corresponding spreading code corresponding to each combination pattern of the transmission data and setting the transmission output,
A first synchronizing spread code generating means for generating a first synchronizing spread code, the first synchronization with the selection output of the selection means
A transmitting unit having an adding means for adding and transmitting a spreading code for use , a second spreading code generating means for generating 2 ^N spreading codes, and 2 ^{N combinations} patterns of the transmission data, respectively. Receiving the 2 ^N transmission spreading codes thus obtained,
2 and ^N correlation integral means for calculating the correlation integral between the 2 ^N spread codes of the spreading code generating means, and a maximum value detecting means for detecting that maximum integrated value of this such correlation integral unit, the
A second synchronization spreading code generating a second synchronization spreading code.
Generating means for receiving the first synchronization spreading code,
Synchronization correlation for calculating correlation integral with 2 synchronization spreading codes
Integrating means, means for detecting a phase state of the received spreading code with respect to the second synchronization spreading code based on the synchronization correlation integration value, and a pattern corresponding to the maximum value when the phase state indicates a match. Is the demodulated data, and in the case of a mismatch, the demodulated data is calculated according to the magnitude of the difference between the integral value corresponding to the pattern shifted by two chips from the pattern corresponding to the maximum value and the maximum value and the predetermined threshold value. And a receiving unit having a determination unit for determining the following. 2. The first and second spreading code generating means.
Are linear feedback shift register circuits and this linear feedback
The output of the red shift register circuit is sequentially delayed to 2 ^N -1
And a delay shift register circuit for deriving the delayed output of
And the output of the linear feedback shift register circuit and the delay
Wherein the 2 ^N -1 single output of the shift register circuit 2 ^N pieces
The spread spectrum communication system according to claim 1 , wherein the spread code is used .