JP2918906B2 - Image processing method and apparatus - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and apparatus for use in a facsimile, printer, image scanner, etc. having an image enlargement function, and more particularly, to a pixel forming an image. Alternatively, the present invention relates to an image processing method and an image processing method for enlarging an image by repeating a pixel line (hereinafter collectively referred to as pixel data) at appropriate intervals or by appropriately selecting one of a plurality of read clocks.

[Prior art] Conventionally, in a facsimile or an image scanner, image data read by an image sensor may be enlarged to a predetermined size and transmitted to the other receiver. In some cases, the image data expanded in the memory is enlarged to a predetermined size and output to the print engine side. As a method of enlarging such image data to a predetermined size, for example, image data in the main scanning line direction is converted to a predetermined pixel clock. In an apparatus that performs image processing while alternately writing and reading data to and from a plurality of line buffers based on a frequency, it is necessary to repeatedly read out pixel data located at intervals corresponding to a predetermined enlargement ratio during the reading. Effectively increases the number of pixels and expands image data. There is a system that makes a big difference. (Problems to be Solved by the Invention) However, in the first prior art, the repetition interval and position can be arbitrarily set using a counter or a registration means. Since the setting can be performed, an accurate enlargement ratio can be obtained. However, the iterative processing means thins out the read clock of the corresponding pixel data based on the repeat instruction signal, stops reading one pixel, and repeats the process. Since the output time of the repeated pixel data is twice as long as the output time of the other adjacent pixel data, only the repeated pixel data is output in a delayed state. Image distortion increases, and problems such as image reproducibility and readability tend to occur.

In order to solve such a drawback and realize accurate image reproducibility without causing image distortion, the frequency of the original oscillation clock is changed in accordance with the enlargement ratio so that the clock for writing to the storage means and the read for the memory can be read. There is also a technique for changing the frequency ratio of the clock, in other words, for uniformly increasing the pixel pattern density (hereinafter referred to as a second conventional technique), but in order to obtain a fine enlargement rate, the oscillation clock must be accelerated accordingly. In particular, the enlarged size of the image is, for example, 115% (B
With a single digit division ratio such as 5 → A4) 122% (A4 → B4) 141% (A4 → A3), it is not possible to obtain a common greatest divisor, and to obtain a highly accurate enlargement factor It is necessary to prepare a frequency divider having a predetermined frequency division ratio for each enlarged size, and as a result, there arises a problem that the device configuration becomes complicated.

In view of the drawbacks of the prior art, the present invention provides an image processing method capable of obtaining a preferable enlarged image in terms of image reproducibility and readability without complicating the device configuration and without noticeable image distortion, and The purpose is to provide a device.

"Means for Solving the Problems" The progress of the present invention will be described.

First, in the method of enlarging only one pixel located at the pixel interval corresponding to the enlarging ratio as in the first related art, since only the output time of the pixel in that part is doubled,
Image distortion cannot be avoided.

Also, as shown in the second prior art, it is difficult to obtain a frequency-divided clock corresponding to the enlargement ratio in a system in which all pixel pattern densities on one image line are uniformly enlarged, and there is a problem in enlargement accuracy. .

Therefore, in the first invention described in claim 1), the enlargement processing of the corresponding pixel is performed at every pixel interval set based on the target enlargement ratio, but only one pixel is subjected to the enlargement processing. Without being limited to the above, the enlargement processing is performed together with the pixel data (the number of pixels: n ₂ ) adjacent to one piece of pixel data located at the pixel interval, whereby the number of processed pixels n (n ₂ +1)
The output time of the pixel group is made closer to the output time (T1) of the normal pixel in correspondence with
By outputting using a second read clock different from other pixel data so as to substantially match T1 × [(1 + n) / n], as a result, the occurrence of image distortion due to the difference in the output time is reduced. The goal is to reduce as much as possible.

For example, when pixel data and the next pixel data are read out at each corresponding pixel interval, 2 can be substituted for n in the above equation.
In this case, an inverted clock having the same cycle as the normal read clock and having a different phase from the normal read clock is used as the second clock, as shown in a later-described embodiment. I just need.

Therefore, according to the first aspect of the present invention, the target enlargement ratio is set based on the pixel interval in the same manner as in the first related art. Is simply output using the second read clock. In other words, instead of preparing a large number of read clocks having different frequencies corresponding to the target enlargement ratio as in the second related art, the normal read operation is simply performed. It is only necessary to prepare a first read clock for reading the data and a second read clock for obtaining the output time, and the configuration of the device is not complicated.

In the case where the same pixel group is continuous as shown in FIG. 3 in the pixel group, in other words, in the case where black dots and white dots are continuous, even if the enlargement process is performed based on the first invention, Even if the enlargement process is performed on the first related art, the output data states of the corresponding pixel groups are the same, and there is no point in adopting the first invention in particular.

Therefore, the invention described in claim 3) includes a first enlargement processing unit that performs repetitive processing of corresponding pixel data based on a designation signal output at an arbitrary pixel interval according to an arrangement state of a corresponding pixel data group. The second enlargement processing means for switching to a second clock different from the first read clock based on the designation signal and reading out one or a plurality of corresponding pixel data is selectively switchable. It is characterized by the following.

Further, such an invention includes a temporary storage means for storing at least a plurality of pixel data before and after the output while sequentially shifting based on the first read clock, and a temporary storage means for each shift or each output of the designation signal. A determination circuit for loading a plurality of pixel data stored in the storage means in parallel and determining whether at least the pixel data and the next pixel data are the same pixel data, and a determination output from the determination circuit; The two enlargement means may be configured to be selectively switchable based on the above.

Hereinafter, preferred embodiments of the present invention will be illustratively described in detail with reference to the drawings. However, unless otherwise specified, the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention thereto, but are merely illustrative examples. It's just

FIG. 1 is an overall block diagram showing an image processing apparatus according to an embodiment of the present invention used in a laser printer. In order to briefly explain the configuration of the apparatus, reference numeral 1 denotes a video memory, Using the image input clock, image data for one page is expanded and stored in a dot shape while being enlarged in the sub-scanning direction and stored.

Reference numeral 21 denotes a shift register which reads out the image data stored in the video memory 1 in one main scanning line or n bits at a time in parallel and stores it as line-shaped image data. The shift register 21 is selectively output from the clock switching circuit 23. Video data can be serially output while sequentially shifting stored image data based on a shift (read) clock.

Reference numeral 22 denotes a determination circuit, which reads 2 to n-bit data D1 to Dn in parallel each time the shift clock is output to the shift register 21 side, and outputs black data (1) or white data in which output data and subsequent data are continuous. If it is a dot (0), the judgment output of "0" is outputted from the judgment circuit 22 to the clock switching circuit.
It can be sent to the 23 side.

Reference numeral 24 denotes a clock oscillator, and a first read clock synchronized with an image input clock and the first read clock generated by an inverter 25.
The read clock I is inverted, and an inverted clock having the same cycle and a different phase as the normal read clock is input to the clock switching circuit 23 as the second read clock II.

Each time the designation signal is output from the repetition designation circuit 30 at a pixel interval corresponding to the enlargement ratio, the clock switching circuit 23 generates a clock signal based on the "0" or "1" decision output sent from the decision circuit 22. The read clock 24 or any of the clocks inverted by the inverter 25 is selectively switched so that the corresponding read clocks I and II can be transmitted to the shift register 21 side.

As shown in FIG. 5, the repetition designating circuit 30 includes a latch register 301 for storing a bit pattern corresponding to the enlargement ratio,
At each start of main scanning or at appropriate intervals, the latch register 30
A cyclic shift register 302 into which a bit pattern is loaded from 1 and M corresponding to the bit length of the bit pattern.
A selector circuit 303 for selecting a feedback bit position of the cyclic shift register 302 according to a control signal from a PU, and the shift clock SC is supplied to the cyclic shift register 302.
, The repetition designation signal corresponding to the bit pattern can be generated from the output terminal 302a of the cyclic shift register 302.

For example, by setting the bit pattern to “1 ₀₀₀₀₀₀ 1 ₀₀₀₀₀₀ ”, about 115% (B5 → A
4) If the repetition designation signal having the magnification is " _{1001 0} 1 ₀₀ 1 ₀ "
Approximately 141 at intervals of 2 to 3 bits by setting
% (A4 → A3) can be obtained.

 Next, an embodiment of the present invention will be described with reference to FIG.

First, image data stored in the video memory 1 is read out in parallel for each main scanning line,
After that, serial video is performed while being sequentially shifted based on a shift clock selectively output from the clock switching circuit 23.

Then, every time the output bit data and the next bit data are output to the determination circuit 22 side for each shift, the output bit data and the next bit data are loaded in parallel. If both data are continuous black dots (1) or white dots (0), The determination output of “0” is sent from the determination circuit 22 to the clock switching circuit 23 side.

As a result, the shift clock synchronized with the image input clock is sent to the shift register 21 as it is without clock switching in the clock switching circuit 23, and the repetition designation signal is provided at every bit interval corresponding to the target magnification. Is transmitted, for example, when a repetition designation signal is transmitted between D2 and D3, the output of the shift clock is stopped for one clock based on the designation signal, and the corresponding pixel data becomes the output data. Repeat D3.

As a result, as shown in FIG. 4 (a), the output time T is doubled as in the case of the pixel data D3, but the pixel data D3 is the next-order pixel data which is not subjected to the repetitive processing.
Since it is the same type as D4, the combination of the two-bit data of D3 and D4 agrees that the output time is suppressed to 1.5 times the normal pixel data readout cycle, and the image distortion does not become noticeable.

On the other hand, if the pixel data D3 and the next-order data D4 are a combination of black dots and white dots (10 or 01), a determination output of "1" is sent from the determination circuit 22 to the clock switching circuit 23, and The clock is switched by the switching circuit 23, the second read clock II is sent to the read control circuit side, and the corresponding pixel data is output based on the clock.
D3 and the next pixel data D4 before output are read. As a result, as shown in FIG. 4 (b), the output time T of both pixel data can be suppressed to 1.5 times the normal pixel data read cycle in which no repetitive processing is performed.

After reading the 2-bit data of D3 and D4, switching to the first read clock I is performed based on the signal from the repetition designating circuit 30, and the same operation is repeated thereafter.

FIG. 2 shows that once the image data for one main scanning line stored in the shift register 21 is temporarily stored in the temporary storage means 4, the enlargement processing is performed when the image data stored in the temporary storage means 4 is read out. An image processing apparatus to be performed will be described, and the description will focus on differences from the above embodiment.

The temporary storage means 4 is composed of two sets of line buffers 41 and 42 for performing a toggle operation and a pair of selectors 43 and 44. The temporary storage means 4 is connected to the line buffers 41 and 42 based on switching signals from the write and read control circuits 6 and 7. Is configured to perform writing and reading in parallel.

The image data read from the line buffers 41 and 42 is configured to be video output via the clock control circuit 5.

The clock control circuit 5 is a 4-bit register 50 for sequentially outputting image data while sequentially shifting image data based on the shift clock from the clock switching circuit 51, and a pixel data group stored in the 4-bit register 50 for each data shift. , And outputs a determination output of “0” or “1” in accordance with the table shown in FIG.
A clock switching circuit 51 for switching the read clock based on the determination output sent from the determination circuit 52 is provided.

The clock oscillator 24 'sends the first clock I synchronized with the image input clock to the shift register 21 and the write control circuit 6, respectively, and controls the writing to the line buffers 41 and 42 based on the clock. , The first
And the second clock II inverted by the inverter 25 are sent to the clock switching circuit 51 side.

The repetition specifying circuit 30 is configured to transmit a repetition specifying signal having a target enlargement ratio based on a signal from the MPU as in the above-described embodiment.

 Next, examples of the present invention will be described.

First, the pixel data D1 after output is sequentially shifted into the 4-bit register 50 via the selectors 43 and 44 based on the shift clock I synchronized with the write clock.
The next pixel data D3 before the output of the pixel data D2 and the next data D4 are stored.
When the bit pixel data D1 to D4 are loaded in parallel to the determination circuit 52 side and the determination output of "0" is sent from the determination circuit 52 to the clock switching circuit 51 as shown in FIG. The first clock I is sent as it is to the 4-bit register 50 and the read control circuit 7 without clock switching in the 51, and a repetition designation signal is sent at every bit interval corresponding to the target magnification. Then, iterative processing of the pixel data D3 can be performed based on the designation signal.

As a result, as shown in FIG. 4 (a), the output time T of the pixel data D3 from the 4-bit register 50 is doubled and output to the print engine side in the same manner as in the previous embodiment.

On the other hand, when a decision output of "1" is sent from the decision circuit 52 to the clock switching circuit 51, the clock is switched to the second clock II by the clock switching circuit 51, and the clocks are read out by the read control circuits 7 and 4 respectively. By being sent to the bit register 50, the corresponding pixel data D3 and the next pixel data D4 before output are read out based on the clock II as in the previous embodiment. As a result, as shown in FIG. 4 (b), the output time T of both pixel data can be suppressed to 1.5 times the normal pixel data read cycle in which no repetitive processing is performed.

After reading the 2-bit data of D3 and D4, switching to the first clock I is performed based on the signal from the repetition designating circuit 30, and the same operation is repeated thereafter.

Therefore, in any of the above embodiments, regardless of whether the judgment output from the judgment circuit 52 is “0” or “1”, when the pixel data D2 is substantially combined with the next pixel data D3 before output, The output time can be substantially suppressed to 1.5 times the normal pixel data read cycle, and the image distortion does not become noticeable. Further, according to the second embodiment, the pixel data to be determined can be increased by 4 bits, and more accurate image control can be performed.

[Effects of the Invention] As described above, according to the present invention, it is possible to obtain an enlarged or enlarged image with high accuracy corresponding to any enlarged size without complicating the device configuration, and only a part of the pixel clock is used. It is possible to obtain an enlarged or enlarged image with high reproducibility extremely close to the original image without making the image redundant. And so on.

[Brief description of the drawings]

1 and 2 are an overall block diagram showing an image processing apparatus according to each embodiment of the present invention, FIG. 5 is a block diagram showing a repetition designating circuit used in the apparatus, and FIG. Time chart diagram showing the output time of pixel data corresponding to the read clock output from the clock switching circuit,
FIG. 3 is a table showing the arrangement of pixel data stored in a 4-bit register in the device.

Claims (4)

(57) [Claims] An image processing method for performing an enlargement process while serially reading image data in a predetermined scanning line direction using a first read clock (output time T1), wherein one pixel data located at a corresponding pixel interval is provided. And one or more pixel data adjacent to the pixel data are output using a second read clock different from the other pixel data, so that the output time T of the pixel data substantially matches the following equation. An image processing method characterized by being set. T = T1 × [(1 + n) / n] (n: the total number of pixels of the one pixel data and one or more pixel data adjacent to the pixel data) 2. An inverted clock having the same cycle as that of a normal read clock and having a different phase is prepared as the second read clock, and pixel data and next-order pixel data are used for each corresponding pixel interval by using the clock. The image processing method according to claim 1, wherein the image is output. 3. An image processing apparatus for performing image enlargement processing of pixel data based on a designated signal output at an arbitrary pixel interval, comprising the steps of: A first enlargement processing unit that performs repetitive processing of the above, and a second enlargement that switches to a second clock different from the first read clock based on the designation signal and reads one or a plurality of corresponding pixel data. An image processing apparatus comprising: a processing unit; and the two enlargement processing units are selectively switchable according to an arrangement state of a corresponding pixel data group. 4. A temporary storage means for storing at least a plurality of pixel data before and after output while sequentially shifting based on the first read clock, and a temporary storage means for each shift or each output of the designation signal. A plurality of pixel data stored in the memory in parallel, and a determination circuit for determining whether at least the pixel data and the next pixel data are the same pixel data, based on a determination output from the determination circuit 4. An image processing apparatus according to claim 3, wherein said enlargement means is selectively switchable.