JP2919406B2 - Performance evaluation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer performance evaluation method.

[0002]

2. Description of the Related Art With the recent development of semiconductor technology, computers of various architectures have been devised and put into practical use. Early calculators were relatively simple in construction,
Although its processing ability largely depends on a central processing unit (CPU), the architecture is becoming more complicated with a hierarchical memory structure, multiple buses, write buffers and the like for further improving the processing ability. As a result, the performance of the computer system strongly depends not only on the processing capability of the CPU itself but also on the architecture of the entire computer such as the memory, I / O, and bus. For this reason, in order to develop a computer or to operate an application program at a high speed on a specific computer system, it is necessary to optimize hardware according to the architecture.

Under the above-mentioned background, a technique of a performance evaluation method is attracting attention as a technique for optimizing the operation of a hardware architecture in advance by simulating the operation of the hardware architecture.

As a conventional performance evaluation method, for example, there is a data processing apparatus as disclosed in Japanese Patent Laid-Open No. 5-324412. FIG. 3 is a diagram showing the prior art of the above publication, and the operation will be described below with reference to FIG.

In the conventional performance evaluation method, a multiprocessor configuration is adopted for the database processing unit 16, and the processing of data input / output with the disk unit 17 is performed by an engine interface processor (EIP) 161 by a parallel sorting module (PSOM). ) 165 and the sort processing using the hardware operation circuit of the parallel relation algebra operation module (PRAM) 166 are distributed to the HW sorter control processor (ECAM) 164, and the whole control is distributed to the engine control processor (ECP) 162. ing. And an engine control processor (ECP)
162 is an engine interface processor (EI)
P) 161, HW sorter control processor (ECAM) 1
The operation contents of the CPU 64 and the engine control processor (ECP) 162 and the execution time of the operation are collected as statistical data, and the host device analyzes the operation state and performance in the database processing unit.

[0006]

The above-described conventional performance evaluation method requires dedicated hardware such as a database processing unit for analyzing execution instructions, and executes execution instructions and the like in the engine control processor. A large-capacity memory for storing is required. For this reason, control becomes complicated by requiring synchronous processing between the instruction execution of the computer to be evaluated and the engine control processor.
There is a problem in that data to be simulated may include interrupt processing that is not originally executed.

[0007] In addition, although there is a conventional example in which performance evaluation is performed by software, there is a problem that the performance evaluation target does not include a BIOS instruction section, and accurate performance evaluation cannot be performed.

An object of the present invention is to provide an accurate performance evaluation method that does not require dedicated hardware or a large-capacity memory and includes a BIOS instruction.

[0009]

A first performance evaluation method of the present invention is a performance evaluation method for simulating the operation of a computer having a virtual architecture based on execution instruction information of the computer and analyzing the performance information. A first step of converting a simulation target program into a machine language instruction unique to a computer, a second step of extracting a BIOS instruction included in the simulation target program converted into a machine language instruction, and the BIOS instruction A third step of inserting a BIOS source code recording an instruction sequence for each type into the simulation target program converted into machine language instructions, and a memory access for each instruction of the simulation target program into which the BIOS source code is inserted A fourth step of checking for the presence or absence of A fifth step of inserting an instruction code for calling a program, and temporarily storing read / write type and reference address information for each memory access instruction when each instruction is a memory access instruction; A sixth step of linking the simulation target program and the evaluation subprogram that have undergone the processing of the fifth step to convert them into an execution module, and a step of calling the evaluation subprogram each time one instruction is executed. Step 7, the required number of clocks for each of the instructions is read from the instruction execution time database, and an eighth step of calculating the total number thereof. In the case of the memory access instruction, from the read, write type and reference address information, A ninth step of calculating performance information.

According to a second performance evaluation method of the present invention, in the first performance evaluation method of the present invention, the performance information is the number of execution clocks, the number of memory accesses, a cache hit ratio or a page hit ratio. And

[0011]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a processing flow of the performance evaluation method of the present invention. 1 is a simulation target program, 2 is a BIOS source code, 3 is a program analysis means, 4 is an instruction / memory evaluation subprogram, 5 is a compile / link, 6 is an execution module, 7 is a program execution, 8 is an instruction execution time database, 9 is a simulation result.

FIG. 2 is a diagram showing a processing flow of the program analysis means 3 of FIG.

The simulation target program 1 is converted by an assembling process 31 into machine language instructions unique to the computer to be simulated. Further, by analyzing the bit string of the machine language instruction, a BIOS instruction is extracted, and a process 32 of inserting the BIOS source code 2 corresponding to each BIOS instruction type into the simulation target program 1 is performed.

The simulation target program 1 into which the BIOS source code 2 is inserted is further checked 33 for the presence or absence of memory access for each machine language instruction. This can be easily determined by analyzing the bit string of the machine language instruction. In the case of a memory access instruction, a process 34 of storing the read / write type and reference address information in a specific register or main memory is performed. Then, a process 35 of inserting an instruction for calling the instruction / memory evaluation subprogram 4 for each instruction of the simulation target program 1 is performed.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS.

First, the simulation target program 1
Are converted by the program analysis means 3 into machine language instructions unique to the computer. And the program analysis means 3
A bit string of the converted machine language instruction is searched, a BIOS call part included in the instruction string is detected, a corresponding program routine is read from the BIOS source code 2, and inserted into the machine language instruction string. Further, the program analysis means 3
An instruction for subroutine-calling the instruction / memory evaluation subprogram 4 is inserted for each instruction in the machine language instruction sequence. At this time, if the machine language instruction includes a memory access, the read / write type and reference address information are temporarily stored in a specific register or main memory (step S101).

The simulation target program 1 into which machine language instructions are expanded, a BIOS source code 2 is inserted for each BIOS call, and an instruction for calling the instruction / memory evaluation subprogram 4 is inserted for each instruction, is compiled and compiled. By the link processing 5, the reference address relationship with the instruction / memory evaluation subprogram 4 is determined, and linked to be converted into the execution module 6 (step S10).
2).

The flow of processing when executing the execution module 6 will be described in detail. When the execution module 6 executes the program 7, the simulation target program 1
Makes a subroutine call to the instruction / memory evaluation subprogram 4 every time one machine language instruction is executed. The instruction / memory evaluation subprogram 4 reads the number of clocks required to execute each machine language instruction from the instruction execution time database 8, and obtains the total (step S103). If the machine language instruction to be simulated includes a memory access, the instruction / memory evaluation subprogram 4 executes (step S101) the cache hit / miss, the cache hit / miss from the reference address information stored in the register or the main memory.
The page hit / miss is determined, and the total of the number of memory accesses, the number of cache hits, and the number of page hits is calculated. The determination of cache hit / miss and page hit / miss differs depending on the cache structure (bit width, control method) and memory structure (page size, paging method) of the computer to be simulated, but a specific bit string pattern of reference address information. Is realized by evaluating

The above processing for each machine language instruction is continued until the end of the program, and the number of execution clocks, the number of memory accesses, the cache hit ratio, and the page hit ratio are calculated as simulation results 9 (step S104).

[0021]

As described above, according to the present invention, no special hardware or large-capacity memory is required, and B
There is an effect that an accurate performance evaluation method including an IOS instruction can be constructed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a processing flow of a performance evaluation method of the present invention.

FIG. 2 is a diagram showing a processing flow of a program analysis means 3 of FIG.

FIG. 3 is a diagram showing a conventional technique.

[Explanation of symbols]

 Reference Signs List 1 simulation target program 2 BIOS source code 3 program analysis means 4 instruction / memory evaluation subprogram 5 compile / link processing 6 execution module 7 program execution 8 instruction execution time database 9 simulation result

Claims (2)

(57) [Claims] 1. A performance evaluation method for simulating the operation of a computer having a virtual architecture based on execution instruction information of a computer and analyzing the performance information, wherein a program to be simulated is converted into a machine language instruction unique to the computer. A first step of extracting a BIOS instruction included in the simulation target program converted into a machine language instruction, and a BIOS source code in which an instruction sequence for each BIOS instruction type is recorded. A third step of inserting the BIOS source code into the simulation target program, a fourth step of checking the presence or absence of memory access for each instruction of the simulation target program inserted, Insert the instruction code that calls the evaluation subprogram into A fifth step of temporarily storing a read / write type and reference address information for each memory access instruction when each instruction is a memory access instruction; and the simulation in which the processing of the fifth step is performed. A sixth step of linking the target program with the evaluation subprogram and converting it into an execution module; a seventh step of calling the evaluation subprogram each time one instruction is executed; An eighth step of reading the number of clocks from the instruction execution time database and calculating the sum thereof, and in the case of the memory access instruction, a ninth step of calculating performance information from the read / write type and reference address information; A performance evaluation method comprising: 2. The performance evaluation method according to claim 1, wherein said performance information is a number of execution clocks, a number of memory accesses, a cache hit ratio or a page hit ratio.