JP2919566B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device such as a semiconductor integrated circuit (hereinafter, referred to as IC) chip, and more particularly to this electrostatic discharge protection structure.

(Prior art) Conventionally, IC chips and the like are packaged with the input terminals and output terminals exposed to the outside, and static electricity invades the inside of the IC chip when a human body contacts the terminals. In some cases, electrostatic breakdown may occur. In particular, input terminals and output terminals of IC chips and the like are often directly connected to main circuits inside the IC chip.
Highly affected by electrostatic breakdown. ICs such as MOS LSI
In a chip, the input terminal is usually connected to the gate electrode of a MOS transistor, but the gate electrode is insulated by an oxide insulating film, so it has good electrical insulation, such as in clothes and plastic containers, and when handling LSI. High voltage is easily applied by the generated static electricity.

As a countermeasure against such an electrostatic breakdown, conventionally, an electrostatic breakdown protection circuit connected between an input terminal or an output terminal and an internal circuit is incorporated in an IC chip.

As such an electrostatic discharge protection circuit, for example, there is a technique described in the document “Nikkei Microdevice” (November 1986), pp. 131-137. The configuration is shown in FIG.

FIG. 2 shows a conventional IC having a first electrostatic discharge protection circuit.
It is a block diagram of a chip.

This IC chip 10 has a power supply pad 11, a power supply pad for grounding (hereinafter referred to as a grounding pad) 12 and an input pad 13, and a power supply line 14 is connected to the power supply pad 11 as a power supply wiring. A ground line 15 is connected to the pad 12 as a power supply line. Between the power supply line 14 and the ground line 15, an internal circuit 16 and an electrostatic suppression circuit 17, which is an electrostatic protection circuit, are connected in parallel.

The internal circuit 16 includes, for example, MOS transistors 16a and 16b constituting an inverter, and is connected to the static electricity suppressing circuit 17.

The static electricity suppressing circuit 17 is a circuit that performs a shunt or the like for suppressing static electricity from the input pad 13 and discharging the static electricity to the outside.
It is composed of clamping diodes 17a and 17b and a discharge current limiting resistor 17c.

 Next, the operation will be described.

Normally, when positive or negative static electricity is applied to the input pad 13, the static electricity restricts the discharge current by the resistor 17c and slows the rise of discharge, and the positive static electricity flows to the power supply side through the diode 17a, and the negative static electricity flows. Flows to the ground side via the diode 17b. At this time, for example, if the power supply pad 11 is open and the ground pad 12 is grounded, positive static electricity tends to flow through the diode 17b via the resistor 17c. In the opposite direction, the sensitivity is generally poor.
As shown by A1, it flows to the power supply side through the diode 17a,
Further, the current flows to the ground pad 12 through the MOS transistors 16a and 16b of the internal circuit 16. Further, the negative static electricity flows to the ground pad 12 through the diode 17b as shown by an arrow A2 in FIG.

FIG. 3 shows another example of the configuration of another conventional electrostatic breakdown protection circuit.

FIG. 3 shows a conventional IC having a second electrostatic discharge protection circuit.
It is a block diagram of a chip.

This IC chip 20 has almost the same configuration as the IC chip 10, except that in addition to the static electricity suppressing circuit 17, a protection transistor 21 having electrostatic withstand voltage, which is a discharge element, is added. It was done.

The protection transistor 21 includes a power line 14 and a ground line.
15, and the gate electrode is connected to the ground line 15. In addition, the protection transistor 21 is provided so that static electricity is dispersed and flows in order to have electrostatic withstand voltage.
For example, it is configured to have a large dimension in a gate width or the like.

In the IC chip 20, for example, similarly to the case of the IC chip 10, positive static electricity applied to the input pad 13 when the power supply pad 11 is in the open state flows through the diode 17a as shown by an arrow A3 in FIG. Flows to the ground pad 12 via the protection transistor 21.

(Problems to be solved by the invention) However, the electrostatic breakdown protection circuit having the above configuration has the following problems.

(A) In the IC chip 10, for example, when positive static electricity is applied to the input pad 13 when the power supply pad 11 is open, the static electricity flows through the MOS transistors 16a and 16b of the internal circuit 16, so that each of the MOS transistors 16a and 16b The pn junction between the source or drain electrode and the substrate may be destroyed. In this case, for example, the MOS transistor 16
It is conceivable to solve this problem by increasing the junction area of the pn junctions a and 16b. However, in this case, there is a problem that the chip area increases.

(B) In the IC chip 20, for example, even when the power supply pad 11 is in an open state, the static electricity entering from the input pad 113 and flowing to the power supply side passes through the diode 17a and is protected from sneaking into the internal circuit 16. It flows through transistor 21 to ground pad 12. However, since the protection transistor 21 conducts static electricity, the protection transistor 21 has a dimension larger than that of a normal MOS transistor or the like in order to obtain an electrostatic withstand voltage, so that the chip area of the IC chip 20 increases.

The present invention solves the problems of the prior art,
An object of the present invention is to provide a semiconductor device having an electrostatic discharge protection structure capable of reliably protecting an internal circuit from static electricity without increasing a chip area.

(Means for Solving the Problems) In order to solve the above problems, according to a first aspect of the present invention, a first power supply pad to which a first power supply potential is supplied, and a first power supply potential are provided. And a second power supply pad to which a different second power supply potential is supplied. The second power supply pad is electrically connected to the first power supply pad via a first wiring, and a second power supply pad is connected to the second power supply pad. And an electrostatic circuit electrically connected to an input pad or an output pad and electrically connected to the first power supply pad and the second power supply pad. And a discharge element electrically connected to the first power supply pad using a third wiring and electrically connected to the second power supply pad. An electrostatic protection circuit and the first power supply pad or the second power supply pad; The wiring connecting to the power supply pad is different from the first wiring and the second wiring, and the impedance of the third wiring is smaller than the impedance of the first wiring or the second wiring.

In a second aspect, in the semiconductor device according to the first aspect,
The first power supply pad and the second power supply pad are electrically connected to a plurality of internal circuits.

In a third aspect, in the semiconductor device according to the first or second aspect, the width of the third wiring is wider than the width of the first wiring or the second wiring.

In a fourth aspect, in the semiconductor device according to any one of the first to third aspects, the electrostatic protection circuit electrically connected to the output pad has an input side connected to an output of the internal circuit, CMOS whose output side is connected to the output pad
It is an inverter.

In a fifth aspect, in the semiconductor device according to any one of the first to fourth aspects, the discharge element is disposed between adjacent pads.

(Operation) According to the present invention, since the semiconductor device is configured as described above, for example, when a high voltage due to static electricity is applied to the input pad or the output pad, the high voltage causes the internal circuit to be connected. With wiring different from the first and second wirings,
The power is transmitted to the first or second power supply pad. Also, the first
The high voltage transmitted to one of the power supply pads and the second power supply pad is transmitted to the other power supply pad by the power distribution element. At this time, the high voltage transmitted to one of the power supply pads is not transmitted to the internal circuit through the first wiring or the second wiring having a large impedance, but is connected to the third wiring having a small impedance. Is discharged through.

FIG. 1 is a schematic configuration diagram of an IC chip having an electrostatic discharge protection circuit according to a first embodiment of the present invention. In the figure, the third
Elements common to the drawings are denoted by common reference numerals. 4th
FIG. 2 is a layout diagram showing one configuration example of an IC chip according to the electrostatic discharge protection circuit of FIG. 4, the same elements as those in FIG. 1 are denoted by the same reference numerals.

The IC chip 30 has a chip plate 31, on which a power supply pad 32 as a first power supply pad,
A ground pad 33, which is a second power pad provided adjacent to the power pad 32, and input pads 34, 34-1 to 34-
n, a power supply line 35 and a ground line 36 as power supply lines for an electrostatic protection circuit, and a power supply line 37 as a first wiring and a ground line as a second wiring as power supply lines for an internal circuit. 38 are formed.

The power supply line 35 is connected to the power supply pad 32. The power line 37 is connected to the power pad
32 and a power supply line to obtain pressure resistance
The line width is set narrower than 37.

The ground line 36 is connected to the ground pad 33. The ground line 38 has a different path from the ground line 36 to the ground pad.
Connected to 33 and ground line to obtain pressure resistance
The line width is set smaller than 36.

Between the power supply line 35 and the ground line 36, for example, an electrostatic suppression circuit 17, which is an electrostatic protection circuit having the same configuration as that of the IC chip 10, is connected, and its resistance 17c is connected to the input pad 3
Connected to 4.

Between the power supply line 37 and the ground line 38, for example, an internal circuit 16 having the same configuration as that of the IC chip 10 is connected.
The input side of the internal circuit 16 is connected to the input pad 34 via the static electricity suppressing circuit 17.

Further, between the power supply pad 32 and the ground pad 33 provided adjacent to each other, for example, a protection transistor 21 which is a discharge element having the same configuration as that of the IC chip 10 is formed.

The protection transistor 21 functions so as to be turned on only for static electricity and to flow a current, and to be turned off for a normal power supply voltage.
It is composed of transistors. This protection transistor
In 21, a drain electrode is connected to a power supply pad 32 via a power supply line 39 which is a third wiring, and a gate electrode and a source electrode are connected to a ground pad 33.

In the IC chip configured as above, the power supply line 35
A wiring portion A11 which is a second wiring between the power supply pad 32 and the static electricity suppressing circuit 17 in FIG. 4 and a wiring portion which is a first wiring between the power supply pad 32 and the internal circuit 16 in the power supply line 37
The following relationship has been established with A12. That is, with respect to static electricity assumed to be input to the input pad 34, the impedance of the power supply line 39 to which the protection transistor 21 is connected is smaller than the impedance of the wiring portion A12 so that static electricity flows toward the power supply line 39. In the IC chip 30, the impedance of the power supply line 39 is set to be smaller than the impedance of the wiring portion A11. This is realized by, for example, increasing the line width of the power supply line 39.

 Next, the operation will be described.

For example, if positive static electricity is applied to the input pad 34 while the power pad 32 is open and the ground pad 34 is grounded, the positive static electricity causes the rising of discharge to be delayed by the resistor 17c and the discharge current to rise. Flows through the wiring portion A11 through the diode 17a. This positive static electricity enters the power supply pad 32, but flows to the power supply line 39 because the impedance of the wiring portion A12 is set to be larger than the impedance of the power supply line 39, and passes through the protection transistor 21 to the ground pad. It flows to 33 and is discharged.

When a negative static electricity is applied to the input pad 34, the static electricity flows through the diode 17b, the ground line 36, and the ground pad 33.

 This embodiment has the following advantages.

(A) The protection transistor 21 is formed in an empty area between the power supply pad 32 and the ground pad 33 adjacent to each other. Therefore, it is not necessary to provide a region for forming the protection transistor 21 in the IC chip 30. Therefore, even if the protection transistor 21 has a large dimension, an electrostatic breakdown protection circuit that can reduce the chip area of the IC chip 30 can be realized.

(B) In this embodiment, since the impedance of the wiring portion A12 is set to be higher than the impedance of the power supply line 39, the positive static electricity input to the input pad 34 reaches the power supply pad 32 when Line 39
Then, the current flows from the ground pad 33 through the protection transistor 21 to be discharged. Therefore, in the IC chip 30, the internal circuit 16
Electrostatic breakdown can be prevented.

FIG. 5 is a schematic configuration diagram of an IC chip having an electrostatic discharge protection circuit according to a second embodiment of the present invention, and FIG. 6 is an IC chip corresponding to the electrostatic discharge protection circuit of FIG. FIG. 3 is a layout diagram illustrating a configuration example. In the figure, elements common to FIG. 1 include:
Common symbols are assigned.

This IC chip 40 has a power supply pad 32, a ground pad 33, a protection transistor 21,
It has power supply lines 35 and 37, and ground lines 36 and 38, and has an input pad row 41, a static electricity suppression circuit row 42, and an internal circuit row 43.

The input pad row 41 includes, for example, a plurality of input pads 34-1 to 34-1.
34-n, each of which is a static suppression circuit row
Connected to 42.

The static electricity suppression circuit row 42 has input pads 34-1 to 34-1 respectively.
34-n, each of which is connected to a diode 17a-
1, 17b-1, resistor 17c-1, diode 17a-2, 17b-
2, resistor 17c-2, diode 17a-3, 17b-3, resistor 1
7c-3, diodes 17a-4, 17b-4, resistor 17c-4
, Diodes 17a-5 and 17b-5, a resistor 17c-5, and diodes 17a-n and 17b-n, a resistor 17c-n, and the like. The static electricity suppression circuit row 42 is connected to the power supply pad 32 by a wiring portion A11 in the power supply line 35, and is also connected to the internal circuit row 43.

The internal circuit array 43 includes, for example, MOS transistors 16a-1 and 16b-1 forming an inverter and a MOS transistor
16a-2, 16b-2 and MOS transistors 16a-3, 16b-3
, MOS transistors 16a-4, 16b-4, MOS transistors 16a-5, 16b-5, and MOS transistors 16a-6, 16b-6.
Etc. The internal circuit row 42 is connected to the power supply pad 32 by a wiring portion A12 in the power supply line 37.

In the second embodiment, for example, when the power pad 32 is open and the ground pad 33 is grounded, if positive static electricity is applied to any of the input pads 34-1 to 34-6, The positive static electricity is generated by the diodes 17a-1 to 17a-
power pad 3 through wiring portion A11 through any of n
2, and further flows toward the power supply line 39 whose impedance is set smaller than that of the wiring portion A12, and flows to the ground pad 33 via the protection transistor 21. Similarly, when negative static electricity is applied to any of the input pads 34-1 to 34-n, the negative static electricity is applied to the diodes 17b-1 to 17b.
-N through any one of -n to ground pad 33.

The second embodiment has the following advantages in addition to the advantages (a) and (b) similar to those of the first embodiment.
That is, the power supply line 35 of the static electricity suppression circuit row 42 and the internal circuit row
The power supply line 37 of 43 is separately wired, and the static electricity suppression circuit row 42
And the ground line 36 of the internal circuit array 43 were separately wired, and power supply lines 35 and 37 were formed in the same manner as in the first embodiment. Therefore, the static electricity applied to the input pad row 41 can be discharged to the ground pad 33, but at this time, only one protection transistor 21 is required. Therefore, in the present embodiment, the effect of preventing electrostatic destruction can be obtained even when a plurality of input pads 34-1 to 34-n are used, and this can be realized without increasing the chip area.

FIG. 7 is a schematic configuration diagram of an IC chip having an electrostatic discharge protection circuit according to a third embodiment of the present invention. In the figure, the first
Elements common to the drawings are denoted by common reference numerals.

The IC chip 50 has substantially the same configuration as the IC chip 30, and differs from the IC chip 30 in the following points. That is,
The ground pad 33 and the input pad 34 are arranged adjacent to each other, and the protection transistor 21 which is a discharge element is formed in a space between them. Further, the protection transistor 21 is connected to the diode 17a side of the static electricity suppressing circuit 17 via a power supply line 51 which is a third wiring. The impedance of the power supply line 51 is set to be smaller than the sum of the impedances of the wiring portions A11 and A12.
Static electricity is made to flow more easily on the power supply line 51 than on A11 and A12.

In the third embodiment, for example, when the power supply pad 32 is open and the ground pad 33 is grounded, positive static electricity applied to the input pad 34 passes through the diode 17a,
The current flows through the power supply line 51 without flowing through the wiring portion A11, and flows through the protection transistor 21 to the ground pad 33. When negative static electricity is applied to the input pad 34, the negative static electricity flows to the ground pad 33 via the ground line 36 via the diode 17b.

In the third embodiment, substantially the same advantages (a) and (b) as in the first embodiment can be obtained.

FIG. 8 is a schematic configuration diagram of an IC chip having an electrostatic discharge protection circuit according to a fourth embodiment of the present invention. In the figure, the first
Elements common to the drawings are denoted by common reference numerals.

The IC chip 60 includes a power supply pad 32, a ground pad 33, a protection transistor 21, power supply lines 35, 37, 39, and ground lines 36, 38, which are configured similarly to the IC chip 30.
Further, the IC chip 60 includes an output pad 61 and a wiring portion A11.
The static electricity suppressing circuit 62 is connected to the power supply pad 32 by the ground line 36 and is connected to the ground pad 33 by the ground line 36.
8 and an internal circuit 63 connected to the ground pad 33.

The static electricity suppressing circuit 62 includes a PMOS transistor 62a and an NMOS transistor 62a.
It is composed of a CMOS inverter composed of a transistor 62b, and a part thereof is connected to the output pad 61 and the internal circuit 63. The internal circuit 63 is, for example, a MOS constituting an inverter.
It is composed of transistors 63a, 63b and the like.

In the IC chip 60, normally, the output of the internal circuit 63 is output to the output pad 61 via the static electricity suppressing circuit 62. However, when static electricity is applied to the output pad 61, almost the same as in the case of the first embodiment. Similarly, the PMOS transistor 62a or the NMO
Static electricity is applied to the ground pad 33 via the S transistor 62b, for example.
Flows to

In the fourth embodiment, the same operation as in the first embodiment,
The effect is obtained, and the electrostatic breakdown of the internal circuit 63 can be prevented when static electricity is applied to the output pad 61.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following modifications.

(I) The circuit configuration of the IC chips 30, 40, 50, 60 can be modified.

The internal circuit 16 and the internal circuit array 43 are merely examples, and their circuit configurations can be variously modified.

The configuration of the static electricity suppressing circuit 17 and the static electricity suppressing circuit row 42 other than the combination of the diode and the resistance element can be applied. For example, it can be composed of multiple MOS transistors,
Various modifications can be considered, such as a combination of a transistor and a resistor.

The protection transistor 21 may be configured by a PMOS transistor. In this case, the gate electrode and the source electrode are commonly connected to the power supply pad 32. Further, as the discharge element, for example, a bipolar transistor, a Zener diode, or the like may be used instead of the protection transistor 21 corresponding to the configuration of the IC chips 30, 40, 50, and 60.

(II) In the first to fourth embodiments, the case where the power supply pad 32 is open and the ground pad 33 is grounded has been described.
Similarly to the power supply lines 35 and 37, the impedances of 36 and 38 are set according to the power supply wiring of the discharge element, and the configuration of the protection transistor 21 is appropriately set, so that the IC chips 30 and 40 are set. , 50, 60 can be applied to the case where the power pad 32 is in the grounding state by touching a person or an object and the grounding pad 33 is in the open state. is there.

(III) In the first to fourth embodiments, the IC chips 30, 40, 5
Although the description has been given of the MOS type semiconductor integrated circuit as 0,60, the present invention is applicable to IC chips of various semiconductor integrated circuits, such as bipolar type, mixed molding of bipolar and MOS, and those using compound semiconductors such as GaAs. It can be applied to a wide range of cases.

(Effects of the Invention) As described in detail above, according to the present invention, the first wiring for electrically connecting the internal circuit and the first power supply pad, and the internal circuit and the second power supply pad are connected to each other. The electrostatic protection circuit is electrically connected to the first power supply pad or the second power supply pad with a wiring different from the second wiring electrically connected, and further, the first wiring is formed using the third wiring. And a discharge element connected to the second power supply pad and the third power supply pad, and the impedance of the third wiring is made smaller than the impedance of the first wiring or the second wiring.

Thereby, for example, even if a high voltage due to static electricity is applied to the input pad or the output pad, this high voltage is
The power can be transmitted to one power supply pad (for example, a pad on the power supply voltage side) by a wiring different from the first and second wirings to which the internal circuit is connected. Therefore, transmission of a high voltage to the internal circuit can be more reliably prevented. In addition, the high voltage transmitted to one power supply pad can be transmitted to the other power supply pad (for example, a ground voltage side pad) by a discharge element. At this time, the impedance of the third wiring used for connecting the discharge element and the power supply pad is set lower than the impedance of the first wiring or the second wiring. For this reason, the high voltage transmitted to one power supply pad (for example, a pad on the power supply voltage side) is discharged via the discharge element without being transmitted to the internal circuit via the first wiring or the second wiring. Can be. Therefore, it is possible to more reliably protect the internal circuit.

Further, when the discharge element is arranged between the adjacent pads, it is not necessary to provide a special region for forming the discharge element in the semiconductor device, and the semiconductor device can be downsized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram of an IC chip having an electrostatic discharge protection circuit according to a first embodiment of the present invention, and FIG. 2 is a conventional first electrostatic discharge protection circuit. FIG. 3 is a configuration diagram of an IC chip, and FIG. 3 is a configuration diagram of an IC chip having a second conventional electrostatic discharge protection circuit.
FIG. 4 is a layout diagram showing one configuration example of an IC chip according to the electrostatic discharge protection circuit of FIG. 1, and FIG. FIG. 6 is a layout diagram showing one configuration example of an IC chip corresponding to the electrostatic discharge protection circuit of FIG. 5, and FIG. FIG. 8 is a schematic configuration diagram of an IC chip having an electrostatic discharge protection circuit according to a fourth embodiment of the present invention. 16,63 ... internal circuit, 17,62 ... static electricity suppression circuit, 21 ...
Protection transistor, 30, 40, 50, 60 ... IC chip, 32 ...
Power supply pad, 33 Ground pad, 34, 34-1 to 34-n
… Input pad, 35, 37, 39, 51… power supply line, 36, 38…
Ground line, 41: Input pad row, 42: Static electricity suppression circuit row, 43: Internal circuit row, 61: Output pad, A11, A12
... Wiring part.

Claims (5)

(57) [Claims] A first power supply pad to which a first power supply potential is supplied; and a second power supply pad to which a second power supply potential different from the first power supply potential is supplied. One power supply pad via a first wiring, and
And an internal circuit electrically connected to a power supply pad via a second wiring, and electrically connected to an input pad or an output pad and electrically connected to the first power supply pad and the second power supply pad. And a discharge circuit electrically connected to the first power supply pad using a third wiring and electrically connected to the second power supply pad. A wiring for connecting the electrostatic protection circuit to the first power supply pad or the second power supply pad, the wiring being different from the first wiring and the second wiring; 3. The semiconductor device according to claim 3, wherein the impedance of the third wiring is smaller than the impedance of the first wiring or the second wiring. 2. The semiconductor device according to claim 1, wherein said first power supply pad and said second power supply pad are electrically connected to a plurality of internal circuits. 3. The semiconductor device according to claim 1, wherein a width of said third wiring is wider than a width of said first wiring or said second wiring. 4. The static electricity protection circuit electrically connected to the output pad is a CMOS inverter having an input side connected to an output of the internal circuit and an output side connected to the output pad. The semiconductor device according to claim 1. 5. The device according to claim 1, wherein said discharge element is arranged between adjacent pads.
13. The semiconductor device according to item 9.