JP2919942B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a semiconductor device (monolithic IC) which needs to perform different processing for each chip on a wafer after a wafer process.

2. Description of the Related Art Conventionally, in a semiconductor device of this type, after a wafer process is completed, processing such as trimming is performed on each chip as fine adjustment of a semiconductor integrated circuit.

As this processing method, there is a method of cutting a connection path of a resistor or a capacitor portion by a laser beam or a current.

In this case, first, the value of the adjusted portion is actually measured, and then processing is performed based on the actually measured value. Thereafter, the value of the portion to be adjusted is measured again, and if the value is not adjusted to the target value, the portion is processed again. By repeating this operation, the value of the adjusted portion is successively adjusted to the target value.

By such trimming, it is possible to adjust the manufacturing variation of the product.

By the way, it is only possible to know from the actual measurement result how much the value of the portion to be adjusted has changed by one trimming process. is there.

However, when the adjustment is performed finely, it is the same as the adjustment range is expanded, and the work efficiency is reduced accordingly.
This decrease in work efficiency becomes more remarkable as the variation in manufacturing becomes larger.

Another problem is that the scale of the trimming circuit must be increased in order to perform fine adjustment.

That is, FIG. 4 shows a configuration in which a trimming circuit is assembled using the D / A conversion circuit 41. The D / A conversion circuit 41 that outputs an analog signal having a value corresponding to an input binary code is provided in a 3-bit bit configuration circuit. 41a to 41c are connected. The values A to C of the respective bit configuration circuits 41a to 41c output one of the logic "1" and the logic "0" in an unprocessed state, and irreversible processing is performed on the output to obtain the other value. Is output. Depending on whether or not the bit configuration circuits 41a to 41c are processed, either one of logic "1" and logic "0" is set, and a desirable value is obtained as an output of the D / A conversion circuit 41.

By the way, trimming is performed first in each bit configuration circuit 41a.
4141c is processed into one of logic “1” and logic “0”. Then, the output of the D / A conversion circuit 41 is actually measured, and if the value is not an appropriate value, the values A to C of the bit configuration circuits 41a to 41c are changed.

In this case, if each of the bit configuration circuits 41a to 41c outputs a logic "0" in a raw state, the logic "1" cannot be returned to the logic "0" after the logic "1" is written.

Therefore, "ABC" = "000" at first, then "00"
1 ", and so on.

However, the next largest value is originally "ABC" = "0
Although “10”, the value of the bit configuration circuit C constituting 1sb cannot be returned to logic “0”, so “ABC” =
You have to skip "010" and set "ABC" = "011". For similar reasons, the next value is "ABC" = "11
1 ”.

That is, the larger the set value, the larger the adjustment width. Therefore, even if the set value becomes large, the number of bits must be increased to keep the adjustment width to a small value to some extent, and as a result, the circuit scale must be increased.

This is a very inconvenient problem from the viewpoint of miniaturization of the semiconductor integrated circuit or improvement of the degree of integration.

Also, as a method of finding one specific value from a large number of numerical sets, there is a conventional method called the dichotomy, and it is considered effective to adopt this method when the adjustment range is large. It cannot be adopted because of the above-mentioned problem of irreversibility, and there is a situation in which work efficiency has been hindered.

(Problems to be Solved by the Invention) As described above, the conventional trimming circuit in a semiconductor device has a problem that the work efficiency is reduced and the circuit scale is increased from the viewpoint of preventing over-adjustment.

The present invention has been made in view of the above problems, and an object of the present invention is to make it possible to perform appropriate adjustment by preventing excessive adjustment beforehand, thereby improving work efficiency.
An object of the present invention is to provide a semiconductor device capable of reducing a circuit scale.

[Configuration of the invention]

(Means for Solving the Problems) According to a first aspect of the present invention, there is provided a fuse for storing a predetermined set value by burning out with an overcurrent after a wafer process is completed, and a fuse between one end of the fuse and a high potential power supply. A pull-up resistor connected, a pull-down resistor connected between the other end of the fuse and the low-potential power supply, an input terminal that supplies a trial input signal to one end of the fuse, and an overcurrent for blowing the fuse A second input terminal, and an OR gate that receives one of the signals generated at one end of the fuse and generates a trial output signal using the signal of the first input terminal as the other input.

The invention according to claim 2 is a fuse that stores a predetermined set value by burning out by an overcurrent after a wafer process, an input terminal that supplies a trial input signal to one end of the fuse, and one end of the fuse and a high potential power supply. A pull-up resistor connected between the other end of the fuse and the low-potential power supply; a first diode connected in anti-parallel to the pull-up resistor; A semiconductor device comprising: a second diode connected in anti-parallel; and a buffer circuit that generates a trial output signal corresponding to a signal appearing at one end of the fuse.

The invention according to claim 3 is the semiconductor device according to claim 1 or 2, wherein the resistance value of the pull-up resistor is larger than the resistance value of the pull-down resistor.

(Operation) According to the present invention, a setting candidate value is given as a trial input to an input terminal in the trial circuit unit, and by looking at the trial output, what value is set before processing is performed on the storage unit. You can find out what to do.

Therefore, in investigating the appropriate value, the setting candidate value can be changed in a free range, and it is not always necessary to make the value fine. Therefore, an appropriate value can be found quickly, and work efficiency can be improved.

In addition, since the dichotomy can be adopted in the investigation of the appropriate value, the work efficiency can be improved from this point as well.

In addition, it is possible to separate the measurement work and the processing work, and it is not necessary to perform the processing and measure the result as in the past. Can be done.

Since the circuit is not actually processed at the time of the trial, the adjustment width increases as the work progresses as in the past, and accordingly, the adjustment width is reduced to secure the holding accuracy. Since it is not necessary to take measures to increase the number of bits, the number of bits in the bit configuration circuit for trimming may be the minimum necessary number of bits, and the scale of the circuit for trimming can be reduced.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a principle diagram of a trimming circuit of a semiconductor device according to the present invention, showing a state before processing.

In this figure, reference numeral 11 denotes a D / A conversion circuit, which inputs a 3-bit binary code and outputs an analog signal according to the value.

Bit configuration circuits 12a, 12b, and 12c are connected to respective bit input terminals of the D / A conversion circuit 11. Since all of them have the same configuration, only the bit configuration circuit 12a will be described below.

13 is an input terminal, 14 is an output line leading to the input of the D / A converter 11, 15 is a pull-up resistor, 16 is a pull-down resistor, 1
Patterns 7 and 18 are burned out by overcurrent. The pull-up resistor 15 is connected to the input terminal 13 via a pattern 17, and the pull-down resistor 16 is connected to the input terminal 13 via a pattern 18.
It is connected to the.

The resistances 15 and 16 have the same resistance value, so that the input signal to the input terminal 13 is directly connected to the D / A through the output line 14.
It is provided to a converter 11. Therefore, a setting candidate value is given to the input terminal 13 and the value of the output line 14 is set to D /
By giving the signal to the A / A converter 11 and observing the output level of the D / A converter 11, it is possible to check what value should be set.

In such a D / A converter, the number of input bits is determined by accuracy.

In the device configured as described above, at the time of the trimming trial, the logic “1” and the logic “0” are input to the input terminal 13.
And supplies it to the D / A converter 11 to check which level of logic "1" or logic "0" is required.

If it is determined that the logic “1” is necessary, the pattern 18 is cut by laser light, and the output line 14 is pulled up to the logic “1” by the pull-up resistor 15. If a logic “0” is required, the pattern 17 is cut off, and the output line 14 is set to a logic “0” by the pull-down resistor 16.
Will be reduced to

As described above, according to the present principle circuit, the bit configuration circuit 12a
The setting candidate value is given as a trial input to the input terminal of the trial circuit section in ~ 12b, and by looking at the trial output from the D / A conversion circuit, what value should be set before processing is performed. You can find out.

Therefore, in investigating the appropriate value, the setting candidate value can be changed in a free range, and it is not always necessary to make the value fine. Therefore, an appropriate value can be found quickly, and work efficiency can be improved.

In addition, since the dichotomy can be adopted in the investigation of the appropriate value, the work efficiency can be improved from this point as well.

 Here, the search by the bisection method will be described.

 First, there are the following eight combinations of three bits.

"ABC" = "111", "110", "101", "100", "0"
11 "," 010 "," 001 "," 000 "At first, an intermediate value, for example," 100 "(or" 011 ") among these eight patterns is used as a trial input.

This value is given to the D / A conversion circuit 11 and its output is checked. If the output is higher than the target value, a set of values lower than “100” (that is, “011”, “010”, “001”, “000”) It can be seen that the target value exists in. As a result of the enforcement, D /
If the output of the A conversion circuit 11 is lower than the target value, a set of values higher than "100" (that is, "111", "110", "101")
Will have the desired value.

This narrows the search range to about half. Then, the intermediate value in the set of the narrowed range is used as a trial input, and the output of the D / A conversion circuit 11 is similarly examined. As a result, the search range can be further reduced to half.

As described above, by examining whether the target value belongs to the larger or smaller side with the middle value of the set as a boundary, the search range can be reduced to half each time measurement is repeated. In other words, the dichotomy is to divide the search range into two parts, detect and exclude the unnecessary range, and search for the target value.

In the above 3-bit example, if the target value is "101" and the search is performed in order from the maximum value,
It takes three measurements to find "101". In the case of searching from the minimum value, six measurements are required.

On the other hand, if the dichotomy is adopted, it can be seen that the value is the optimum value to be set in two measurements.

As described above, the employment of the dichotomy makes a great difference in work efficiency.

In addition, it is possible to separate the measurement work and the processing work, and it is not necessary to perform the processing and measure the result as in the past. Can be done.

In the case of laser cutting a pattern as in this embodiment, processing is performed by a dedicated laser cutting device,
Since the measurement is performed electrically, the two work processes must be different, and it is of great significance to separate the measurement work from the processing work.

Since the circuit is not actually processed at the time of the trial, the adjustment width increases as the work progresses as in the past, and accordingly, the adjustment width is reduced to secure the holding accuracy. Since it is not necessary to take measures to increase the number of bits, the number of bits of the bit configuration circuit for trimming may be the minimum necessary number of bits, and the scale of the circuit for trimming can be reduced.

FIG. 2 shows a one-bit configuration circuit (before processing) of a trimming circuit formed on one chip of the semiconductor device according to the first embodiment of the present invention.

21 to 23 are input terminals, 24 is an output line leading to the D / A conversion circuit, and 25 is an OR gate whose output is connected to the output line 24.

The input terminal 22 is connected to one input terminal of the OR gate 25, and its level is reduced to logic "0" by a pull-down resistor 26.

The input terminals 21 and 23 are connected via a fuse 24.
The input terminal 21 is connected to the other input terminal of the OR gate 25, and a pull-up resistor 27 is connected to the connection point.

The value of the pull-down resistor 28 is set sufficiently larger than that of the pull-up resistor 27, so that the input terminal 21 is set to logic "0" by the pull-down resistor 28 when the fuse 24 is not blown, and the fuse 24 is blown. In this state, the pull-up resistor 26 sets the logic "1".

In such a configuration, the input terminal 21 is
And 23 are opened, and the input from the input terminal 21 to the OR gate 25 is held at a logic "0", whereby the input terminal 22
Can be directly supplied to the D / A converter through the output line 29.

If the logic "1" is required, the input terminal 21 and
A current is caused to flow through the fuse 29 using the fuse 23, and the fuse 29 is burned out. If a logic "0" is required, the fuse 29 may be left without being blown.

According to the present embodiment, since the machining operation can be performed electrically similarly to the measurement operation, all the operations can be performed without moving the work place.

FIG. 3 shows a circuit configuration example of a semiconductor device according to a second embodiment of the present invention.

Reference numeral 31 denotes an input terminal, and 32 denotes an output line. A resistor 33 and a buffer gate 34 are inserted in a signal transmission path between the input terminal 31 and the output line 32 in this order from the input terminal 31 side.

A pull-up resistor 35 is connected to the input terminal 31 and a pull-down resistor 36 is connected via a fuse 37. The pull-up resistor 35 is set sufficiently larger than the pull-down resistor 36. As a result, when the fuse 37 is not blown, the output line 32 is set to logic "0" by the pull-down resistor 36, and the output line 32 is set to logic "1" and logic "0" depending on the level of the input terminal 31. 0 "
Can be set to any level. Conversely, when the fuse 33 is blown, the output line 32 becomes logic "1" by the pull-up resistor 35.

A diode 39 is connected to the pull-up resistor 35 and a diode 34 is connected to the pull-down resistor 34 in parallel with opposite polarities.

In this configuration, the input terminal is
A logic "1" and a logic "0" are given to 31, and the level is supplied to a D / A converter to search for which level is required.

As a result, if a logic "1" is needed, the diode 38
Fuse by flowing a current from
Burn off 37. If the logic "0" is required, the fuse 37 may be left without being blown.

Here, the reason for setting the direction of the current when the fuse 37 is blown out by the diode 38 is that when the diode 38 is in the opposite direction, that is, when the logic "1" is input to the input terminal 31, the current flows in the quasi-direction. This is because if the polarity is different, the fuse 37 may be burned out by the current flowing at that time.

〔The invention's effect〕

As described above, according to the present invention, a setting candidate value is given as a trial input to an input terminal in the trial circuit unit, and by looking at the trial output, what value should be set before processing is performed. You can find out.

Therefore, in investigating the appropriate value, the setting candidate value can be changed in a free range, and it is not always necessary to make the value fine. Therefore, an appropriate value can be found quickly, and work efficiency can be improved.

In addition, since the dichotomy can be adopted in the investigation of the appropriate value, the work efficiency can be improved from this point as well.

Furthermore, since the measurement work and the processing work can be separated from each other, it is not necessary to perform the processing as in the related art and perform the actual measurement of the result. When the location is different, the work efficiency can be greatly improved.

Since the circuit is not actually processed at the time of trial, the adjustment width increases as the work progresses, as in the past. Because there is no need to take measures to increase the number,
The number of bits of the bit configuration circuit for trimming may be the minimum necessary number of bits, and the scale of the circuit for trimming can be reduced.

[Brief description of the drawings]

1 is a circuit diagram of the principle of the present invention, FIG. 2 is a circuit diagram of a first embodiment of the present invention, FIG. 3 is a circuit diagram of a second embodiment of the present invention,
FIG. 4 is a circuit diagram of a conventional example. 13 input terminal, 14 output line, 15 pull-up resistor, 16 pull-down resistor, 17, 18 laser cut pattern, 21 to 23 input terminal, 24 output line, 25
…… OR gate, 26,28 …… Pull down resistor, 27 …… Pull up resistor, 29 …… Fuse, 31 …… Input terminal, 32…
... output line, 35 ... pull-up resistor, 36 ... pull-down resistor, 37 ... fuse.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-87664 (JP, A) JP-A-2-54565 (JP, A) JP-A-2-209751 (JP, A) JP-A-60-1985 15946 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 21/66 H01L 21/82

Claims (3)

(57) [Claims] 1. A fuse for storing a predetermined set value by burning out by an overcurrent after completion of a wafer process; a pull-up resistor connected between one end of the fuse and a high potential power supply; A pull-down resistor connected between the other end and a low-potential power supply; an input terminal for providing a trial input signal to one end of the fuse; a second input terminal for supplying an overcurrent for blowing the fuse; And an OR gate for generating a trial output signal by using a signal generated at one end of the fuse as one input and a signal of the first input terminal as the other input. 2. A fuse for storing a predetermined set value by burning out by an overcurrent after completion of a wafer process; an input terminal for applying a trial input signal to one end of the fuse; one end of the fuse and a high potential power supply; A pull-up resistor connected between the other end of the fuse and a low-potential power supply; a first diode connected in anti-parallel to the pull-up resistor; A semiconductor device comprising: a second diode connected in anti-parallel to a resistor; and a buffer circuit that generates a trial output signal corresponding to a signal appearing at one end of the fuse. 3. The semiconductor device according to claim 1, wherein a resistance value of said pull-up resistor is larger than a resistance value of said pull-down resistor.