JP2921087B2 - Real Chip Simulation Method for Hardware Accelerator - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial application fields Problems to be solved by the conventional technology and the invention Means to solve the problem Action Embodiment Effects of the invention [Overview] CAE (Computer Aided Engineering) To provide a simulation method that can simulate real parts with the same expression as a simulation model by reducing the time required to send and receive events on a real chip simulation method on a hardware accelerator for logic / timing simulation in the field. A simulation model including at least a function type of a logical block of the minimum unit, unique identification information, and information indicating a mutual connection relationship of the logical block of the certain unit is converted into a unit of the minimum simulation model. And the above function type The simulation model is simulated in accordance with the corresponding hardware logic, and repeatedly outputs and propagates an output pattern corresponding to the input pattern of the minimum simulation model and an event signal indicating that the output pattern has changed. On a hardware accelerator that simulates the above, a real chip simulation device is connected to a bus to which a device for calculating the simulation model is connected, and a device for calculating the simulation model, or Are identified by identification information unique to the logic block, and a simulation model and an actual chip are selectively simulated.

[Industrial applications]

The present invention relates to a real chip simulation method on a hardware accelerator for logic / timing simulation in the field of CAE (Computer Aided Engineering).

The necessity and importance of simulation in the CAE field is a known fact and has become common sense in design. Verification at the system / board level is also important for logic simulation. Here, a commercially available microprocessor (MP
When simulating a circuit including an element whose internal logic is unknown as in U), there is a method of performing simulation using real parts instead of constructing a simulation model, that is, a method called real chip simulation. It is an effective method for recent CAE system simulations, especially for simulations on workstations.

As a method of modeling the element whose internal logic is unknown by simulation, there is a method of expressing the element using an operation description language. However, this method is complicated in its language description, and therefore takes a very long time and is completely Modeling is not possible. There is also a problem that it is difficult to verify the created model.

The real chip simulation has advantages such as the fact that it is not necessary to create a simulation model of an element and that a complete modeling is possible. However, in the conventional method, in order to drive the real parts, a simulation model is used. It is necessary to detect an event for the output real component and transmit and receive the event to and from the real component, and the more events, the longer the simulation time becomes.
In recent years, an increase in the number of devices equipped with a logic element whose internal logic is unknown, for example, the above-described microprocessor (MPU), has necessitated an effective real part simulation method.

[Problems to be solved by conventional technology and invention]

FIG. 3 is a diagram for explaining a conventional real chip simulation method, in which (a) shows an example of a system configuration,
(B) shows a configuration example of a hardware accelerator.

First, an outline of a simulation operation of a logic device by a hardware accelerator (hereinafter, referred to as a simulator) will be described below with reference to FIG.

In order to simulate a logical device with a simulator, a simulation model of the logical device (at least the function type of the smallest logical block constituting the logical device, unique identification information, ), And the simulation model is, for example, 4-input-1
The output is divided into minimum models, and simulation is performed using the minimum model as a unit.

Specifically, one of the minimum models is read out, a specific input pattern is input to its input terminal, and a simulator (soft model calculation unit) 1 performs a simulation corresponding to the function of the model, and An output pattern is generated, and when a change occurs in the output pattern (the occurrence of an event), the event is transmitted to the next plurality of minimum models via the fan-out expanding unit 4 based on the connection relationship information. Repeat the propagation.

The scheduler 3 sets the order of simulation among the plurality of minimum models based on the output result (for example, the logical delay time or the like) from the minimum model.

In this way, the simulation output at the last stage of the logic device is compared with the expected value, and when the output matches the expected value, the simulation for the input pattern is determined to be normally completed. This operation is repeated for a plurality of input patterns.

In the conventional real chip simulation using the simulator, a special hardware device (real component driving device) 7 for driving real components is prepared as shown in FIG. ) And an environment connected using LAN and other technologies.

The simulation operation on this platform is based on the normal model (the above simulation model)
When it is necessary to drive a real part (hereinafter referred to as an event) during the processing by the soft model calculation unit 1, the simulation program (simulator) sends the event from the fan-out development unit 4 to the real part drive unit 7 Send to

Upon receiving the event, the real component driving device 7 initializes the corresponding component, supplies the event, samples the output value resulting from the event, converts the output value into an event format that can be understood by the simulation program, and then transmits the event from the event transmitting / receiving unit 6. Send back.

The simulation program (simulator) receives the event from the real component driving device 7 and ends the simulation of the real component, and restarts the simulation of the normal model. The conventional method performs a series of these processes.

However, it is necessary to transmit and receive events in order to drive real parts, and as the number of events increases, the time that cannot be reduced tends to increase.

Further, in the conventional method, since the real component driving device 7 is located outside the simulator, time that is not directly related to the simulation of transmitting and receiving the event to and from the real component driving device 7 is required. It is hindering. Also, as a simulation model,
It is necessary to clearly indicate that a real part outside the simulator is being used, and the simulation user needs to pay attention. Further, there is a problem that the simulation on the simulation model cannot be performed while the real parts are driven, or the simulation can be performed only in a considerably limited range.

The present invention has been made in view of the above-described conventional drawbacks, and provides a method for reducing the time required to transmit and receive an event to an actual component.
It is an object of the present invention to provide a real part simulation method in which the same expression as a normal model can be expressed for real parts by integrating with a normal simulation model.

[Means for solving the problem]

 FIG. 1 is a diagram illustrating the principle of the present invention.

The above problem is solved by a real chip simulation method in a hardware accelerator configured as described below.

A simulation model including at least a function type of a minimum unit logical block, unique identification information, and information indicating a mutual connection relationship of the certain unit logical block is divided into the unit of the minimum simulation model, Simulation is performed in accordance with the hardware logic corresponding to the function type, and an output pattern corresponding to the input pattern of the minimum simulation model and an event signal indicating that the output pattern has changed are output and propagated repeatedly. On a hardware accelerator for simulating the simulation model, a real chip simulation device 2 is connected to a bus 5 to which the device 1 for calculating the simulation model is connected.
To calculate the simulation model 1, or
The real chip simulation device 2 is identified by the unique identification information of the logic block, and the simulation model and the real chip are selectively simulated.

[Action]

That is, in the present invention, as shown in FIG. 1, a block (soft model calculation unit) 1 for performing a simulation calculation of a soft model (simulation model),
A block (real part calculation unit) 2 for performing a simulation calculation of a real part is configured to be connected to the common bus 5.

Therefore, the input and output of the block (soft model calculation unit) 1 for performing the simulation calculation of the soft model (simulation model) and the block (real component calculation unit) 2 for performing the simulation calculation of the real part can be the same.

The block (scheduler) 3 for controlling the operation result performs buffering of the event time and data, and the like.
An event is output from a block (fan-out expansion unit) 4 that controls the propagation of the event in the model.

As is clear from this figure, the configuration is the same as that of the conventional simulator except for the actual component calculation unit 2.

In the case of the present invention, the input / output interface of the real component operation unit 2 is made the same as that of the conventional soft model operation unit 1 so as to transmit / receive an event to / from the real component, which is required in the conventional method. Is unnecessary, and a simulation model integrating an actual part and a software model can be provided.

In FIG. 3, (a) shows the relationship between the actual component drive device 7 and the simulation program, and it can be seen that the configuration has a very low degree of coupling. Also, the third
FIG. 2B shows the general configuration of the simulation program (simulator). The event transmission / reception unit 6 transmits / receives events between the real component driving device 7 and the simulation program.

As is apparent from a comparison between the two, in the present invention, the block of the event transmission / reception unit 6 shown in FIG. 3B is unnecessary, and the effect of reducing the transmission / reception time of the event to / from the actual component is obtained. Can be

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing the principle of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention.

In the present invention, the real part operation unit 2 is positioned in the simulator (hardware accelerator) in the same order as the soft model operation unit 1, and the soft model operation unit 1 and the real part operation unit 2 are connected to the common bus 5. The connection destination of the event from the fan-out expansion unit 4 is the actual component operation unit 2
Means for propagating the event to the real part in the same manner as for propagating the event to the soft model calculation unit 1 and performing the subsequent simulation based on the output signal from the real part. , Means necessary for carrying out the present invention. Note that the same reference numerals indicate the same object throughout the drawings.

Hereinafter, the actual chip simulation method of the present invention will be described with reference to FIG. 2 while referring to FIG.

In the hardware accelerator according to the present invention, as described above, the real component operation unit 2 is positioned at the same level as the soft model operation unit 1, so that when generating a simulation model of a logic device to be simulated,
Like the other simulation models (soft models), the real parts (real chips) are also positioned as small simulation units, given unique identification information and the like, and connected to other logic blocks.

Therefore, when the simulation model is divided into the smallest models, the actual parts are connected to other smallest models.

Therefore, when an event occurs from a certain minimum model, whether the event is propagated to another minimum model or to a real part is determined simply by adding to the event information, for example, a unique part of the real part. It is only separated by identification information.

FIG. 2 is a block diagram of one embodiment of the present invention, showing a hardware accelerator. The simulation system is configured on the same platform, and has a multiprocessor configuration.

In the figure, reference numeral 10 denotes a block called a gate processor (GPO) which performs an operation in a unit of a gate model (corresponding to the aforementioned minimum simulation model), and 11 denotes a real component processor (RC) which drives a real component and performs an operation. Block. Reference numeral 12 denotes a block of a network processor (ET) that connects the processors, and the above-mentioned 10 and 11 correspond to the first
It comprises a software model operation unit 1 or a real part operation unit 2, a scheduler 3, a fan-out expansion unit 4, and a buffer 8 shown in the principle configuration diagram shown in FIG. 12) shows an output unit from the fan-out expansion unit 4 in FIG. 1 when an event has occurred and a propagation destination is outside the gate processor (GPO) 10 and the real component processor (RC) 11. Make up.

In the hardware accelerator configured as described above, when an event occurs at a certain gate on the gate processor (GP) 10, the gate processor (G)
In P) 10, an operation corresponding to the function type of the gate is performed to obtain an output value. If the output value changes (detected by comparison with the output value at the time of the previous simulation), a new event occurs and the event propagates.

If the destination gate is on another gate processor (GP) 10, the event is propagated to the corresponding gate processor (GT) 10 via the network processor (ET) 12.

If the propagation destination gate is a real part, the event propagates to the real part processor (RC) 11 via the network processor (ET) 12. The propagation of this event is
The destination gate processor (GP) 1 regardless of the type of the gate to which the event propagates (the above-mentioned function type)
0 or the position of the real component processor (RC) 11 in the simulation model (identification information unique to the real component), and the identification information is included in the event information as described above.

Therefore, it is not necessary to specifically recognize the actual part, and the actual part can be handled in the same manner as a gate of a normal soft model (simulation model).

As described above, according to the present invention, in the simulator (hardware accelerator), the real part operation unit 2 is positioned on the same level as the soft model operation unit 1, and the soft model operation unit 1 and the real part operation unit If the destination of the event from the fan-out expansion unit 4 is to the real component calculation unit 2, the event is propagated to the real component in the same way as the event is propagated to the soft model calculation unit 1. By propagating the event, based on the output signal from the real part,
The feature is that the subsequent simulation is performed.

〔The invention's effect〕

As described above in detail, in the real chip simulation method in the hardware accelerator of the present invention, a part for driving a real part is directly incorporated in a part for performing a simulation operation, so that event transmission / reception is performed outside the simulation execution module. Since the simulation can be performed without performing the simulation, the speed of execution can be increased, and the simulation model can be closed in the simulation execution module.
Since the integration of the models is performed, there is an effect that the hardware accelerator can be used for the simulation of the real parts as well as the simulation of the soft model.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a diagram illustrating an embodiment of the present invention, and FIG. 3 is a diagram illustrating a conventional real chip simulation method. In the drawing, 1 is a software model calculation unit, 2 is a real component calculation unit, 3 is a scheduler, 4 is a fan-out development unit, 5 is a common bus, 6 is an event transmission / reception unit, 7 is a real component drive unit, 8 is a buffer, 10 indicates a gate processor (GPO ~), 11 indicates a real component processor (RC), and 12 indicates a network processor (ET).

Claims (1)

(57) [Claims] 1. A simulation model comprising at least a function type of a logical block of a minimum unit, unique identification information, and information indicating a mutual connection relationship of the logical block of a certain unit, Divided into units, simulated according to the hardware logic corresponding to the function type, output an output pattern corresponding to the input pattern of the minimum simulation model and an event signal indicating that the output pattern has changed, and propagated Repeat to make
On a hardware accelerator for simulating the simulation model, a real chip simulation device (2) is connected to a bus (5) to which a device (1) for calculating the simulation model is connected. The device (1) for calculating or the real chip simulation device (2) is identified by the unique identification information of the logic block to selectively simulate the simulation model and the real chip. Real chip simulation method for hardware accelerator.