JP2921206B2 - PC with interlock control - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of programmable controllers (hereinafter, simply referred to as "PCs") connected via a link line for transmitting signals, and an input / output element for the plurality of PCs. , A PC used in a system capable of interlock control. Especially,
Even when the system is operated without connecting a certain PC, or when a special PC is connected and a test run is performed between specific PCs, such operation can be performed without modifying the sequence control program. Regarding PC.

[0002]

2. Description of the Related Art Conventionally, a system in which a plurality of PCs are connected to a link line and one PC can refer to the state of input / output elements belonging to another PC and perform interlock control between the PCs. It has been known. In such a system, each PC transmits the status of the input / output element referred to by the other PC to the other PC via the link line. The PC that receives the state of the input / output element stores the state in the link element memory that can be accessed similarly to the state of the input / output element belonging to its own PC. In this state, when the order control program executes an instruction for referring to the state of the input / output element belonging to another PC, the link element memory is accessed.

[0003]

However, the system does not always operate with all the PCs connected to the link line. For example, there is a case where the system is operated without connecting a certain PC, or the operation state of the system is checked or checked without connecting a certain PC in maintenance, trial operation of the system, or partial operation during system construction. .

In such a case, the state of the input / output element in the PC that is not connected to the link line or that is not powered on is determined by the other Ps via the link line.
Since the data is not transmitted to C, in the link element memory of each PC, the contents of the address of the link element memory corresponding to the unconnected PC become indefinite. However, since the sequence control program is programmed as if all the PCs are connected, the PCs that are not connected are
Therefore, the address of the link element memory corresponding to the above is also accessed, and the order control is not as originally designed.

Therefore, when operating the system without connecting a certain PC, it is necessary to temporarily correct the sequence control program of all the PCs referring to the state of the input / output elements of the PC. In addition, when the system is fully operated as originally designed, it is necessary to restore the sequence control program of each PC to its original state again, and a great deal of labor and time are required for correcting these programs. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to operate a system without connecting a certain PC without modifying a sequence control program, to perform maintenance, and to maintain the system. It is to enable a trial run or a partial run during system construction.

[0007]

According to the present invention, the state of an input / output element belonging to another programmable controller (PC) transmitted through a link line for transmitting a signal is determined.
It is stored in a link element memory that can be accessed in the same manner as the state of its own input / output element, and by accessing the link element memory, the state of the input / output element belonging to another PC is referred to, and the interface between each PC is referred to. In a programming controller (PC) capable of lock control, default value designating means for designating a default value of a state of an input / output element belonging to another PC referred to in a program describing sequence control of the PC, The reception determining means for determining whether the state of the input / output element belonging to the PC is in the normal reception state, and the state of the input / output element belonging to the PC determined not to be in the normal reception state by the reception determination means are as described above. Sequence control executing means for executing the sequence control with reference to the value designated by the default value command means.

[0008]

The default value designating means sets a default value of the state of the input / output element belonging to another PC to which a certain PC refers in the sequence control program. In other words, the default value of the input / output element is determined so that the PC referencing the input / output element of the PC can execute the sequence control program while the other PC is not activated.

Next, the reception determining means determines whether the state of the input / output element of the other PC being referred to is in a normal reception state from that PC. That is, by this determination, P
It is determined whether C is connected to the link line or whether the power is on.

[0010] Next, the order control execution means designates the input / output element which is determined not to be in the normal reception state by the reception determination means without accessing the contents of the link element memory by the default value designation means. The sequence control program is executed with reference to the set value. This allows
Even if the PC that refers to the input / output element is not connected to the link line, the PC that refers to the input / output element
Can execute the order control according to the default value. This default value is set to a value that allows the PC to execute processing without contradiction when the PC is not connected to the link line, so that some PCs are not connected to the link line. In addition, it becomes possible to partially operate the system without modifying the sequence control program.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to specific embodiments. First Embodiment (1) Configuration of System Controlled by Plurality of PCs FIG. 1 shows the configuration of a transfer machine controlled by a plurality of PCs PC01 to PC32. Each of the transfer machine stations ST0, ST1L, ST1R,. ing.

(2) Configuration of PC As shown in FIG. 2, this PC stores a CPU 200 for sequence control and communication control, and stores a sequence control program and link parameters loaded from a programming device. A RAM 250 storing the state of the input / output element to be controlled and the state of the input / output element of the other PC received from the link line L; a ROM 210 storing a monitor program of the CPU 200; Timer that provides timing for synchronous detection of data
260, a driving circuit 270, and an input / output interface 240
And The driving circuit 270 is a relay coil of the output element.
This is a device for driving the 2701 and inputting the state of the relay contact or limit switch 2702 of the input element.

In the RAM 250, addresses from 0000 to 1FFF are memories allocated to input / output elements belonging to the own PC, and the states of these input / output elements can be determined by referring to the contents of these addresses. Also, from address 3000
The address 3FFF is an address commonly assigned to all input / output elements referenced by other PCs in all PCs. Hereinafter, the virtual input / output element assigned to this common address is referred to as a link element.
Address 3FFF is called link element memory.

When all the PCs are connected to the link line L and all the PCs are started, the value of the link element memory 2505 is always common to all the PCs by the communication control at minute time intervals. Value. Therefore,
When referring to the state of the input / output element of another PC in a certain PC, the value of the link element memory 2505 is referred to.

In each PC, a sequence control program is created according to a ladder circuit diagram as shown in FIG. In the ladder circuit diagram of FIG. 3, the input elements are contacts such as relays and limit switches, and the output elements are relay coils and the like. An input element and an output element are collectively called an input / output element.

As shown in FIG. 3, input / output elements include each PC.
Is used to refer to the state of the input / output element. For example, "1200" indicates the address of an input element belonging to its own PC assigned to address 1200. "3000" indicates the address of a link element assigned to address 3000, that is, the address of a virtual input / output element that holds the same state as the state of the input / output element belonging to another PC.

For example, the input element “100” belonging to PCPC01
If “0” is referenced from PCPC11, PCPC01
In this program, a link circuit for making the state of the input element "1000" equal to the state of the link element "3000" is added. The value of the link element “3000” is stored in the link element memory 2505 of all the other PCs by mutual communication.
Written at 3000. Therefore, the program of PCPC11 can refer to the value of address 3000 in the link element memory 2505 to refer to the state of the input element "1000" belonging to PCPC01. Conversely, when the input element “1100” belonging to PCPC11 is referenced from PCPC01, the input element “1100”
Is added to the link element "3014". PCPC11 link element "3014"
Is transferred to PCPC01 and the link element “3014” of all other PCs by communication, and the state of the input element “1100” belonging to PCPC11 is changed to the link element “3014” in all PCs.
14 ".

(3) Communication Control by PC The values of the link element memories 2505 in all the PCs are mutually communicated so as to take the same value. Link line L
Are configured as shown in FIG. For example, from the start bit to 10 bits, P
The link data output from CPC01 (data indicating the state of the link element), the following 7 bits are link data sent from PCPC11, and the following 8 bits are PCPC12.
Means the link data sent from.

The link parameters which specify how many bits of data each PC sends to the link line L at which timing and at what timing which bit data is received from the link line L are stored in the link parameter storage area of the RAM 250. 2504. For example, PCPC
As shown in FIG. 4, the link parameter of 01 is that 10 bits from the start bit transmit data, the next 10 bits receive data from the link line L, the next 20 bits receive data, and the next 20 bits receive data. The 10 bits are data defining transmission or reception, such as receiving data.

Each PC updates the address for accessing the link element memory 2505 sequentially from address 3000 in synchronization with each PC. Then, for the currently accessed address, whether to transmit or receive data is determined according to the link parameter. For the address determined to be transmitted, the state of the link element stored at that address is output to the link line L, and for the address determined to be received, the status is received from the link line L. The data is stored at the address as the state of the link element. By such communication control in each PC, all the values of each address of the link element memory 2505 in all the PCs are always equal.

Next, communication control of each PC will be described. The communication control of each PC is executed by the CPU 200. Functionally, it is represented by a block diagram as shown in FIG.
FIG. 6 is a functional block diagram of PCPC01, but the same applies to other PCs. Each functional block includes a sequence processing unit 201 for sequence control for executing the sequence control program and a communication control unit 202 for communication control, and a sequence control program storage area 2503 as a storage block. , Link parameter storage area 2504,
Link element memory 2505, input / output element memory 2506, and
A communication state storage area 2502 is provided. Communication control unit 202
The transmission / reception unit 202a and the transmission / reception data number counter 20
2b, and each functional block of the transmission / reception data transfer unit 202c.

FIG. 7 is a diagram showing the configuration of the link element memory 2505 of each PC and the relationship between transmission and reception of link data between other PCs. The 10-bit data groups from addresses 3000 to 3009 of the link element memory 2505 transmitted from PCPC01 are all received by PCPC11 and PCPC12 in accordance with the link parameters of PCPC11 and PCPC12, respectively, and the link of each PC is received. It is stored in the corresponding address (3000 to 3009) of the element memory 2505. And then,
The 10-bit data group from the addresses 300A to 3013 of the link element memory 2505 transmitted from the PCPC11 is PCPC0.
1. All data are received by the PCPC 12 and stored in the link element memory 2505 of the PC at addresses 300A to 3013. Next, a 20-bit data group from the addresses 3014 to 3027 of the link element memory 2505 transmitted from the PC
All are received by PC01 and PCPC11, and are stored in addresses 3014 to 3027 of the link element memory 2505 of the PC.

The communication control process executed by each PC will be described with reference to FIGS. This processing is executed as a background job for order control according to the ladder circuit. Then, the process is executed from S501 every time the start bit is transmitted. As a result, data communication as described above becomes possible. First, "1" is set in the parameter I indicating the designation order, and "30" is set in the address pointer S for referring to the RAM 250 (link element memory 2505).
00 ”is set (S501). The designation order is the order of each frame of the link parameter storage unit 2504. For example, PCPC01
In the designation order "1", the number of data is "1" as shown in FIG.
0 ", and the communication designation is" transmission ".

Next, the number of data D (I) is substituted for the variable C, and the communication designation K (I) is substituted for the variable M (S503).
Here, “M = 0 is transmission” “M = 1 is reception” “M ≠ 0,
M # 1 is not received. "

If it is determined in step S511 that the transmission mode is set (S511; YES), data is read from the address (link element memory 2505) designated by the address pointer S in the RAM 250. Is transmitted to the link line L (S51
Five). Further, the variable C is decremented, and the address pointer S is incremented (S517). This processing is performed until the variable C becomes “0”, in other words, until all the data in the specified order is transmitted to the link line L.
Be executed. Thereafter (S513; YES), the parameter I is incremented (S541), and if the communication of the frame (a series of communication shown in FIG. 5) is not completed (S543; NO),
The process returns to step 503. When the communication of the frame has been completed (S543; YES), the apparatus enters a standby state until the next communication.

On the other hand, if it is determined in step S511 that the transmission mode is not the transmission mode (S511; NO) and if it is determined that the transmission mode is the reception mode (S521; YES), the link line data is deleted. −
Data is captured (S525). Next, it is determined whether the data is a normal value indicating either the ON or OFF state or an abnormal value indicating neither of these values (S527). When a certain PC is not connected to the link line, or is not powered on and is not transmitting data, the third state (abnormal state) that is neither on state nor off state ), The signal level on the link line is determined. If the received data is normal, RAM
It is stored in the address (link element memory 2505) designated by the address pointer S in the address 250 (S529). Further, the variable C is decremented, and the address pointer S is incremented (S531). This processing is executed until the variable C becomes "0", in other words, until all the data in the specified order is transmitted to the link line. Subsequent processing (S523; YES) is the same as in the case described above.

If it is determined in step S527 that the received data is an abnormal value, in step S532, the relative address determined by the parameter S in the communication state storage area 2502 is set as shown in FIG. A value “1” indicating that the state of the middle link element is an abnormal value is set.
Note that the contents of the communication state storage area 2502 are initially set to a value “0” indicating that the state of the link element being received indicates a normal value as an initial value.

In the step S511, the transmission mode is not set (S51).
1; NO), and if it is determined in step S521 that the receiving mode is not the receiving mode (S521; NO), since the receiving mode is the non-receiving mode, the variable C is maintained until the variable C becomes "0". Is decremented, and the address pointer S is incremented (S537). Subsequent processing (S533; YES) is the same as in the case described above. As a result of the communication control being performed as described above, each PC
As shown in FIG. 5, the data groups transmitted from the PC are arranged on the link line without any break in time, and each PC takes in only the data necessary for itself.

(4) Specification of default value PC executed when PC is connected to the link line
Will be described. The program corresponding to the ladder circuit shown in FIG. 3 and stored in the order control program storage area 2503 of the RAM 250 is executed. This program is an executable program, and the corresponding source program is as shown in FIG.

By the way, when a certain PC is not connected to the link line, or when the power of the PC is not turned on even though it is connected to the link line, the PC is not connected.
Does not send the status of the link element. Therefore, in the link element memory 2505, the state of the link element in which no link data is transmitted from another PC is indeterminate. Therefore, it becomes difficult to execute the order control corresponding to the ladder circuit shown in FIG. In such a case, the state of the link element whose state is uncertain is determined as follows.

As shown in FIG. 3, the link element (ie, 30
When specifying an address of an input / output element to which an address after address 00 is assigned, add a symbol "-N" or "-F" after the address. "-N" and "-F" indicate that the value of the link element at that address is indeterminate,
Force the link element to be "on" or "off"
Means that the instruction is to execute the sequence control program. In this way, in the ladder circuit diagram, when the value of the link element is uncertain, its default value is specified.

The ladder circuit shown in FIG. 3 is converted into a source program shown in FIG. 10, and further converted into an object program described in a machine language, and the program is stored in the RAM 250 as a sequence control program. ing.

(5) Execution of Sequence Control Program The CPU 200 executes processing according to the procedure shown in FIG. However, the case of an instruction referring to a link element is shown, and the processing procedure of other instructions is omitted. In step S100,
One instruction word of the program shown in FIG. 10 is read from the order control program storage area 2503. Then, step
In S102, it is determined whether or not a default value is specified (N, F is specified) for the instruction word. If no default value is specified, in step S104, the link element memory
The instruction is executed with reference to the contents of the designated address 2505. As described above, an instruction word for which no default value is specified is executed according to the value of the link element memory 2505.

If it is determined in step S102 that a default value has been specified, the flow advances to step S106 to read the communication state of the link element specified by the command from the communication state storage area 2502 shown in FIG. Is issued to determine whether the link element is in a normal communication state. If it is in the normal communication state, in step S104, the content of the address specified by the command in the link element memory 2505 is read, and the command is executed according to the content.

Next, if it is determined in step S106 that the link element is not in the normal communication state,
The flow shifts to S108, where it is determined whether the default value described in the instruction word is N (on) or F (off). Default value is N (on)
If so, in step S110, the instruction is executed with the link element at the address specified by the instruction being in the ON state. On the other hand, if the default value is F (off), in step S112, the command is executed with the state of the link element at the address specified by the command being off. In this way, if the link element at the address specified by the command is not in a normal communication state and the state of the link element is not determined, the command is executed according to the default value specified by the command. Become. Since the default value is a value appropriately determined in advance by an operator so that the program can be normally executed, the program can be properly executed even if a certain PC is not connected to the link line. .

Second Embodiment Next, an embodiment in which a default value is given by another method will be described. In the RAM 250, a default value storage area 2501 in which the relationship between the link element address and the default value as shown in FIG.

Before executing the control program, the CPU 200 executes the program of the processing procedure shown in FIG. In step S200, the communication state storage area 2502 is searched. In step S202, the default value storage area 2501 is searched for the link element that is not in the normal communication state, and the corresponding default value is stored in the link element memory 2505.
Is stored at the corresponding address. Since the link data of the link element that is not in the normal communication state is not received, the value of the link element memory 2505 does not change and becomes the set default value. In this way, the link element memory 25
After the default value is set to 05, the sequence control program is executed with reference to the link element memory 2505. As a result, an appropriate state can be determined for a link element that is not in a normal communication state, and an appropriate execution of the sequence control program can be performed.

Third Embodiment Next, a description will be given of an embodiment in which input / output elements are specified not by addresses but by signal names. In this case, the sequence processing unit 201 includes a control processing unit 2011 and a signal name information interpreting unit 2012 as shown in FIG. The control processing unit 2011 is a member that controls the corresponding station ST0 and the like based on the contents stored in the order control program storage area 2503. Further, for example, when a signal name is input from the outside, the signal name information interpreting unit 2012 sends the signal name to the input / output element memory 2506 or the order control program storage area.
It is interpreted as an instruction to check the contents of the corresponding input / output address portion of 2503. Alternatively, the signal name and the input / output address are interpreted as having been input based on the storage contents of the signal name / address conversion table section 2500. The signal name information interpreter 2012 uses the input / output element memory
2506 or the sequence control program, if it is performed together with a new writing instruction to the storage area 2503, the processing is performed with reference to the signal name / address conversion table section 2500, and other instructions, for example, the input / output element memory 2506 or the order. If the instruction is issued together with an instruction to read a corresponding location from the control program storage area 2503, the processing for referring to the signal name / input / output address conversion table 2500 is not particularly performed. Note that the reading, rewriting, or new writing of actual information is performed by the control processing unit 2011. Of course, the signal name processing unit 2012 may have the ability to perform such processing. The ladder circuit given by the signal name is a circuit as shown in FIG. Instead of the addresses of the input / output elements, signal names DOP, D1P, 12D2X, M2X, etc. are used. As for the default value of the link element, ON and OFF are designated by "-N" and "-F" as in the first embodiment.

A source program corresponding to the ladder circuit shown in FIG. 16 is as shown in FIG. The signal name is used instead of the address of the input / output element. The default value of the link element is specified by N, F.

A table shown in FIG. 18 defining the relationship between these signal names and addresses is stored in a signal name / address conversion table storage area 2500 formed in the RAM 250. Then, in the source program shown in FIG.
The signal name is converted into an address by searching a signal name address conversion table. Thereafter, the order control program is executed, and the processing procedure is as shown in FIG. 1 described in the first embodiment.
This is the same as the processing procedure of No. 1.

Fourth Embodiment Next, as in the third embodiment, in the embodiment using signal names, a default value can be given in the same manner as in the second embodiment. That is, a correspondence table between signal names and default values is created in the default value storage area 2501.
Then, before executing the sequence control program, the processing procedure shown in FIG. 14 is executed as in the second embodiment. That is,
The communication state storage area 2502 is searched, and a link element that is not in a normal communication state is selected. Next, the signal name address conversion table shown in FIG. 18 is searched from the address of the link element, and the signal name of the corresponding link element is determined.
Next, a default value storage area 2501 shown in FIG. 19 is searched from the signal name, and a corresponding default value is determined. And the default value is the link element memory 25
Stored at the corresponding address of 05. Such an operation is performed for all link elements that are not in a normal communication state. As a result, for a link element that is not in a normal communication state, a default value is set to a corresponding address in the link element memory 2505. When the order control program is executed, the state of the link element is determined by referring to the link element memory 2505.

[0042]

According to the present invention, the state of an input / output element belonging to another programmable controller (PC) is stored in a link element memory that can be accessed similarly to the state of its own input / output element via a link line. In the programmable controller (PC) that enables interlock control between the PCs by accessing the link element memory and referring to the states of input / output elements belonging to other PCs, the order control of the PCs is described. Value designation means for designating a default value of the state of the input / output element belonging to another PC referred to in the program, and determining whether or not the state of the input / output element belonging to the other PC is in the normal reception state. The receiving determination means for determining and the P determined to be not in the receiving state
The state of the input / output element belonging to C has order control executing means for executing the order control with reference to the value designated by the default value command means. Therefore, even if the PC which refers to the input / output element is not connected to the link line, the PC which refers to the input / output element can execute the order control according to the default value. This default value is set to a value that allows the PC to execute processing without contradiction when the PC is not connected to the link line, so that some PCs are not connected to the link line. In addition, partial operation of the system can be performed without modifying the sequence control program.
Thus, in system maintenance, inspection, start-up of a new system, and the like, it is possible to operate only some PCs without changing the sequence control program, thereby improving workability.

[Brief description of the drawings]

FIG. 1 shows a plurality of PCs connected by link lines and each PC
FIG. 4 is an explanatory diagram showing a station controlled by the control.

FIG. 2 is a block diagram showing the configuration of each PC in FIG. 1;

FIG. 3 is a circuit diagram showing a ladder circuit corresponding to an order control program.

FIG. 4 is an explanatory diagram showing link parameters.

FIG. 5 is an explanatory diagram showing link data transmitted to a link line.

FIG. 6 is a block diagram illustrating functions of a PC.

FIG. 7 is an explanatory diagram showing the correspondence between link element memories in each PC.

FIG. 8 is a flowchart showing a procedure of a communication control process in a CPU 200 of each PC.

FIG. 9 is a flowchart showing a procedure of a communication control process in a CPU 200 of each PC.

FIG. 10 is an explanatory diagram showing a source program corresponding to the ladder circuit.

FIG. 11 is a flowchart showing an execution procedure of an order control program by a CPU 200 of each PC.

FIG. 12 is an explanatory diagram showing the contents of a communication status storage area.

FIG. 13 is an explanatory diagram showing the contents of a default value storage area in another embodiment.

FIG. 14 is an explanatory diagram showing a procedure for setting a default value by the CPU 200 of each PC in the embodiment.

FIG. 15 is a block diagram illustrating functions of a PC according to another embodiment.

FIG. 16 is a circuit diagram showing a ladder circuit according to another embodiment.

FIG. 17 is an explanatory diagram showing a source program corresponding to the ladder circuit.

FIG. 18 is an explanatory diagram showing the correspondence between signal names and addresses in the embodiment.

FIG. 19 is an explanatory diagram showing the contents of a default value storage area in the embodiment.

[Explanation of symbols]

 PC01 ~ PC32 Programmable controller,

Continuation of the front page (56) References JP-A-3-127104 (JP, A) JP-A-59-205640 (JP, A) JP-A-2-155026 (JP, A) JP-A-2-257349 (JP) , A) JP-A-58-84307 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G05B 19/04-19/05

Claims (1)

(57) [Claims] A link element memory which can access the state of an input / output element belonging to another programmable controller (PC) transmitted via a link line for transmitting a signal in the same manner as the state of its own input / output element. To the other PC by accessing the link element memory.
In a programming controller (PC) that enables interlock control between PCs by referring to the states of input / output elements belonging to the PC, the input controller belonging to another PC referred to in a program describing the order control of the PCs Default value designating means for designating a default value of the state of the output element, reception determining means for determining whether the state of the input / output element belonging to the other PC is in a normal reception state, and normality by the reception determining means The state of the input / output element that is determined not to be in the receiving state is determined by a P-controllable P which includes an order control executing means for executing the order control by referring to a value designated by the default value command means.
C.