JP2922020B2 - Semiconductor device test method and semiconductor device test apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device test method and a semiconductor device test apparatus which are effective for testing highly integrated and multifunctional semiconductor devices and which have reduced relay circuits and increased packaging density. .

[0002]

2. Description of the Related Art In recent years, high integration and multifunctionality of semiconductor devices have been remarkable, and it has become important for a semiconductor device test apparatus and a test method to realize a function measurement at a high assurance level.

[0003] A conventional semiconductor device test method and test apparatus will be described below. FIG. 3 is a test circuit diagram of a general conventional semiconductor device test apparatus showing one terminal. The test apparatus 3 is connected to the terminal 2 of the device under test 1. On the test apparatus 3, two relays 4, 5 are arranged. One end of a DC signal transmission path 7 is connected to the former DC test relay 4 via an impedance 6, and a DC measurement system 8 is connected to the other end of the DC signal transmission path 7. The DC measurement system 8 includes a DC voltmeter, a voltage applied current measuring power supply, or a current applied voltage measuring power supply. On the other hand, a grounded impedance 10 and one end of an AC signal transmission line 11 are connected to the latter AC test relay 5 via a capacitance 9, and an AC signal source 12 is connected to the other end of the AC signal transmission line 11. . AC signal source 1
The internal impedance Z12 of FIG. 2, the characteristic impedance Z11 of the AC signal transmission line 11, and the value Z10 of the impedance 10 are in a matched relationship as follows: Z12 = Z11 = Z10. The AC signal source 12 generates a sine wave, a square wave, or an arbitrary waveform.

The operation of the semiconductor device test apparatus and test method configured as described above will be described below.

First, the DC test relay 4 is closed, and a DC voltage or the like is applied from the DC measurement system 8 so that the device under test 1
Conduct a DC test. Next, the DC test relay 4 is opened, the AC test relay 5 is closed, an AC signal is applied from the AC signal source 12, and the AC test of the device under test 1 is performed.

[0006]

However, in the above-described conventional configuration, when DC and AC tests are required for the device under test 1, a DC test relay 4 is connected to one terminal 2.
And two relays of the AC test relay 5. When DC and AC tests are required at many terminals in the device under test 1 with high integration and multifunctionality, the relays 4 and 5 to be connected are increased in proportion to the terminals, and the mounting area of the test apparatus 3 is reduced. There was a disadvantage that the size became large.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and eliminates two relays connected to one terminal to reduce a mounting area and a size of a test apparatus. It is intended to provide a device.

[0008]

In order to achieve this object, a semiconductor device test method and a test apparatus according to the present invention include two transmission systems for terminals of a semiconductor device to be measured, and one of the transmission systems. Connects one end of a series impedance Z1 to a terminal of the semiconductor device, connects the other end of a capacitance C1 having one end grounded to the other end of the series impedance Z1, and one end of a DC signal transmission line, and connects the other transmission system in series. One end of a capacitance C2 is connected to the terminal of the semiconductor device, the other end of the series capacitance C2 is connected to the other end of an impedance Z2 having one end grounded, and one end of an AC signal transmission line having a characteristic impedance Z0. Characteristic impedance Z0 of the road and a combined impedance Z1 of the impedance Z1 and the impedance Z2.

[0009]

[Outside 5]

Z2 is equal (Z0 = Z1

[0011]

[Outside 6]

Z2) The capacitances C1 and C2 are configured to have a sufficiently small impedance value with respect to an AC signal.

[0013]

With this configuration, the provision of the capacitance C2 prevents the DC component from being interrupted during the DC test and does not affect the transmission system for the AC test after the DC test is performed. When the test is performed, the AC component is cut off and the transmission system for the DC test is not affected. Further, Z0 = Z1

[0014]

[Outside 7]

Since the matching condition Z2 is satisfied,
A test similar to the conventional example can be performed without using a relay.

[0016]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a test circuit diagram of a semiconductor device test apparatus showing one terminal in one embodiment of the present invention. A test apparatus 23 is connected to a terminal 22 of the semiconductor device 21 to be measured. Two transmission systems are arranged on the test device 23. In the former DC test transmission system, a grounded capacitance 25 and one end of a DC signal transmission line 26 are connected via an impedance 24, and a DC measurement system 27 is connected to the other end of the DC signal transmission line 26. The DC measurement system 27 includes a DC voltmeter, a voltage applied current measuring power supply, or a current applied voltage measuring power supply. On the other hand, in the latter transmission system for an AC test, a grounded impedance 29 and one end of an AC signal transmission line 30 are connected via a capacitance 28, and an AC signal source 31 is connected to the other end of the AC signal transmission line 30. You. The internal impedance Z31 of the AC signal source 31 is equal to the characteristic impedance Z0 of the AC signal transmission line 30, and the value and the impedance 24, 29
Parallel impedance Z1

[0018]

[Outside 8]

Z2 is equal. That is, Z31 = Z0 = Z
1

[0020]

[Outside 9]

This is a matched relationship like Z2, and the capacitances 28 and 25 take a sufficiently small impedance value with respect to the AC signal. The AC signal source 31 generates a sine wave, a square wave, or an arbitrary waveform.

The operation of the semiconductor device test apparatus configured as described above will be described below.
First, a DC voltage or the like is applied from the DC measurement system 27 to perform a DC test on the semiconductor device 21 to be measured. next,
An AC signal is applied from an AC signal source 31 to perform an AC test on the semiconductor device 21 to be measured.

As described above, according to this embodiment, the provision of the capacitance 28 enables
It has no effect on the transmission system for AC test after the DC component is cut off, and by providing the capacitance 25,
When the AC test is performed, the AC component is cut off and does not affect the transmission system for the DC test. Further, Z31 = Z0
= Z1

[0024]

[Outside 10]

Since the matching condition of Z2 is satisfied,
The same test effect as the conventional example can be obtained without using a relay. In the embodiment, the parallel impedance Z1

[0026]

[Outside 11]

Although Z2 has been described, there are various combinations, and the present invention can be widely applied to the case of a combined impedance.

FIG. 2 shows a procedure of a method for testing a semiconductor device according to an embodiment of the present invention. First, a DC system test is performed, and then an AC system test is performed. As a unique effect of the present invention, a DC test and an AC test can be performed simultaneously. For example, a DC operating point can be measured while applying an AC signal, or an application test can be performed in which a DC operating voltage is applied and an AC signal is superimposed thereon.

As described above, in a highly integrated and multifunctional semiconductor device to be measured, even if a test of DC and AC is required at many terminals, the relay connected to the terminals is deleted.
A test method and a test apparatus for a semiconductor device that can reduce the mounting area and the size of the test apparatus can be realized.

[0030]

As described above, the present invention has two transmission systems for the terminals of the semiconductor device to be measured, and one transmission system has one end of the series impedance Z1 connected to the terminals of the semiconductor device. The other end of the capacitance C1 having one end grounded to the other end of the series impedance Z1 is connected to one end of a DC signal transmission line, and the other transmission system is connected to one end of a series capacitance C2 to a terminal of the semiconductor device. The other end of the impedance Z2 having one end grounded to the other end of the capacitance C2 and the characteristic impedance Z0
Is connected to one end of the AC signal transmission line, and a characteristic impedance Z0 of the AC signal transmission line and a combined impedance Z1 of the impedance Z1 and the impedance Z2.

[0031]

[Outside 12]

Z2 is equal (Z0 = Z1

[0033]

[Outside 13]

Z2) Since the capacitances C1 and C2 have a sufficiently small impedance value with respect to the AC signal, the relay connected to the terminal can be eliminated, and the DC test and the AC test with the reduced mounting area and size can be performed. It is possible to provide an excellent semiconductor device test method and a semiconductor device test apparatus capable of simultaneously performing tests.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a test apparatus for performing a semiconductor device test method according to an embodiment of the present invention.

FIG. 2 is a flowchart of a test method of a semiconductor device using the circuit diagram of FIG. 1;

FIG. 3 is a circuit diagram of a test apparatus for performing a conventional semiconductor device test method.

[Explanation of symbols]

 Reference Signs List 21 semiconductor device under test 22 terminal 23 test apparatus 24 impedance (impedance Z1) 25 capacitance (capacitance C1) 26 DC signal transmission path 27 DC measurement system 28 capacitance (capacitance C2) 29 impedance (impedance Z2) 30 AC signal transmission path 31 AC signal source

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/26 H01L 21/66

Claims (3)

(57) [Claims] 1. A terminal for a semiconductor device under test
One transmission system has one end of a series impedance Z1 connected to a terminal of the semiconductor device, the other end of a capacitance C1 having one end grounded to the other end of the series impedance Z1, and the other end of a DC signal transmission line. One end is connected, the other transmission system is connected to one end of the series capacitance C2 to the terminal of the semiconductor device, and the other end of the impedance Z2 having one end grounded to the other end of the series capacitance C2 and the AC signal transmission of the characteristic impedance Z0. One end of the AC signal transmission line and the characteristic impedance Z of the AC signal transmission line.
0, and a combined impedance Z1 of the impedance Z1 and the impedance Z2. Z2 is equal (Z0 = Z1) Z2) A method of testing a semiconductor device, wherein the capacitances C1 and C2 have a sufficiently small impedance value with respect to an AC signal. 2. The method according to claim 1, wherein one of the transmission systems is a DC test and the other transmission system is an AC test, and the DC test and the AC test are performed simultaneously. 3. The terminal of the semiconductor device under test has two terminals.
A series impedance Z1 having one end connected to a terminal of the semiconductor device;
A capacitor C1 having one end connected to the other end of the series impedance Z1 and having one end grounded;
At least a DC signal transmission path connected in parallel to the other end of the series impedance Z1, the other transmission system having a series capacitance C2 having one end connected to the terminal of the semiconductor device, and the other end of the series capacitance C2. And an AC signal transmission line having a characteristic impedance Z0 connected to the other end of the series capacitance C2 in parallel with the impedance Z2, and a characteristic impedance Z0 of the AC signal transmission line. And a combined impedance Z1 of the impedance Z1 and the impedance Z2. Z2 is equal (Z0 = Z1) Z2) The semiconductor device test apparatus, wherein the capacitances C1 and C2 have sufficiently small impedance values with respect to an AC signal.