JP2922066B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as a high-frequency high-power GaAs FET having a plated heat sink (PHS) and an IC.

[0002]

2. Description of the Related Art In high-power GaAs FETs and ICs, it is necessary to polish GaAs as a substrate thinly to reduce thermal resistance, and to form a metal layer serving as a heat sink on the back surface of the substrate. Conventionally, as a method of manufacturing such a GaAs IC, for example, a semiconductor element portion is formed on the front side main surface of a substrate, the back surface of the substrate is polished to a predetermined thickness, and a metal layer (PHS) serving as a heat sink is formed by vapor deposition and plating. ), The metal layer at the chip separation position is removed by a photolithography step and a metal layer etching step, and GaAs as a substrate is removed from the portion of the window where the metal layer is removed by etching until reaching the substrate surface. In this case, a method of separating the chips by performing the steps has been adopted.

Hereinafter, a conventional manufacturing method will be described.
2 (a) to 2 (h) show a high-power Ga having a conventional PHS.
It is a figure showing the manufacturing method of AsIC. In FIG. 1A, reference numeral 1 denotes a semiconductor element portion formed on the surface side of the substrate 2. As shown in FIG. 2B, the substrate 2 is attached to the support plate 5 using the wax material 4 and fixed, and the back surface of the substrate 2 is polished to reduce the thickness to 30 to 60 μm. Further, as shown in FIG. 3C, after dip-etching and cleaning the surface, Ni6 and Au7 as base metals serving as power supply layers during plating are deposited. FIG. 3D shows a step of forming Au8 serving as a PHS on the base metal by electrolytic plating.
Thereafter, a resist pattern 9 for etching and removing Au along the chip separation position as shown in FIG.
Is formed, and the resist is removed after Au 7 and 8 are etched as shown in FIG. Finally, Ni6 is removed by etching as shown in FIG. 5G, and then GaAs as the substrate 2 is etched to separate elements as shown in FIG.

[0004]

However, in the above-mentioned conventional manufacturing method, since the end point of the GaAs etching as the substrate is difficult to determine, a portion where the chip separation is not completely performed due to the variation in the progress of the etching remains in the wafer. If this occurs or the etching time becomes longer, side etching proceeds in the case of wet etching, and there is a problem that damage to the element portion and defects such as appearance and shape are likely to occur on the chip surface.

[0005] The present invention solves the above-mentioned problems, and P
It is an object of the present invention to provide a method of manufacturing a semiconductor device having high uniformity and controllability of a high-power GaAs IC having HS.

[0006]

In order to achieve this object, a method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device, wherein a chip separation line on a first principal surface of a substrate on which a semiconductor element portion is formed is etched to a predetermined width and Forming a separation groove having a depth, and reducing the substrate to a predetermined thickness that does not reach the bottom of the separation groove formed on the first main surface side from the second main surface side of the substrate. Forming a metal layer (PHS) serving as a heat sink on the second main surface of the substrate by vapor deposition, plating, etching, or the like; and further etching the substrate from the window portion of the metal layer until reaching the separation groove. And a step of separating chips.

[0007]

According to the above structure, GaAs as a substrate is arranged from the back side.
When s is etched, it can be used as an end point for etching the GaAs substrate when the etching reaches the groove formed for chip separation, and in order to cope with the progress of the etching in the wafer. Even if extra etching time is taken to eliminate the insufficient separation, the etching margin is equivalent to the depth of the separation groove formed from the front surface side, so the chip due to the progress of the side etch at the time of wet etching This makes it possible to manufacture a GaAs IC having excellent uniformity and controllability without causing damage to the element portion on the surface or defects such as appearance and shape.

[0008]

An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1J are sectional views showing steps of a method for manufacturing a GaAs IC semiconductor device according to an embodiment of the present invention. In FIG. 1A, reference numeral 1 denotes a semiconductor element portion formed on the substrate surface side, and reference numeral 2 denotes a GaAs substrate. FIG. 4B shows a process of forming a resist pattern 3 for forming a groove for chip separation, and FIG. 4C shows a state where the resist is removed after etching. Thereafter, as shown in FIG. 3D, the substrate 2 is attached to the support plate 5 by using a wax material 4 and fixed, and the back surface is polished or the like to 30 to 30 mm.
Substrate 2 is thinned to 60 μm. Further, as shown in FIG. 7E, after dip-etching and cleaning the surface, Ni6 and Au7 as base metals serving as power supply layers during plating are deposited. FIG. 1F shows a step of forming Au8 serving as a PHS on the base metal by electrolytic plating. Thereafter, a resist pattern 9 for etching and removing Au along the chip separation position is formed as shown in FIG. 6G, and the resist 9 is removed after Au etching as shown in FIG. . Finally, Ni is removed by etching as shown in FIG. 2I, and then, as shown in FIG. 2J, GaAs as the substrate 2 is etched until it reaches a separation groove previously formed from the front side. To separate the elements.

When chip separation is performed in such a manufacturing process, even if the etching rate of GaAs etching varies, the chip separation can be reliably performed without damaging the element portion of each chip or impairing the surface shape. Can be. That is, when the GaAs etching reaches the groove earliest in the wafer, the side etching proceeds until the slowest etching reaches the groove.
If the width is larger than the width of the s-etch, excess etching does not proceed in the depth direction. Further, even if the etching is further performed in the depth direction, the depth of the groove becomes a margin before reaching the surface side of the element. Therefore, it is possible to reliably perform chip separation of the entire wafer, and to extremely reduce the possibility of damaging the element portion or damaging the surface shape. In particular, it is effective when chip separation is performed by wet etching having large etching variation and side etching.

Here, in this embodiment, Au plating as a heat sink is performed on the entire wafer and then separated by etching. However, a resist pattern may be formed after a base metal is formed, and then formed by selective plating.
As the base metal, other than Ni / Au of the present embodiment, only Ni, Ti / Au, only Ti, Cr / Au, only Cr, and the like can be considered.

Further, a step of separating chips by dicing instead of etching may be considered. That is, FIG.
After proceeding to the step (h) or (i), a blade having a blade width smaller than the width of the PHS etching window reaches the ionization groove previously formed from the front side from the back side and the support plate. This is a method of performing dicing to a depth that does not reach. In this case, too, only the thickness of the wax material and the depth of the groove provide a margin for the dicing depth, so chip division may be incomplete or the support plate may be damaged as compared with the case where there is no separation groove. The reproducibility is extremely small and a stable process excellent in reproducibility can be obtained.

[0013]

As is apparent from the above description, the method of manufacturing a semiconductor device according to the present invention is characterized in that the chip separation line on the first principal surface of the substrate on which the semiconductor element portion is formed is etched to a predetermined width and a predetermined width. A step of forming a separation groove having a depth, and a step of reducing the substrate to a predetermined thickness that does not reach the bottom of the separation groove formed on the first main surface side from the second main surface side of the substrate. Forming a metal layer (PHS) serving as a heat sink by vapor deposition, plating, etching, or the like at a position where the chip separation groove is not formed on the second main surface side; And a step of separating chips by etching or dicing the substrate until the substrate reaches the separation groove, thereby providing a semiconductor device having a PHS structure with excellent reproducibility and uniformity. .

[Brief description of the drawings]

FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor element portion 2 GaAs substrate (substrate) 3 resist pattern 4 wax material 5 support plate 6 Ni 7 Au 8 Au (metal layer serving as heat sink) 9 resist

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-7182 (JP, A) JP-A-2-14839 (JP, A) JP-A-3-87027 (JP, A) JP-A-3- 274749 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 23/36 H01L 21/338 H01L 29/812

Claims (5)

(57) [Claims] A step of forming a separation groove having a predetermined width and a predetermined depth in a chip separation line on a first main surface of a substrate on which a semiconductor element portion is formed; A step of reducing the thickness from the surface side to a predetermined thickness so as not to reach the bottom of the separation groove formed on the first main surface side; A step of forming a resist pattern such that a window of the pattern is opened in a region on the metal layer corresponding to the separation groove formed in the first main surface; and Removing a portion of the metal layer, and separating each chip by etching from the second main surface of the substrate in a region where the metal layer is removed until reaching the separation groove. Semiconductor device manufacturing method Law. 2. A method according to claim 1, wherein each chip is separated by etching from the second main surface of the substrate in the region where the metal layer has been removed to reach the separation groove. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate is diced to separate each chip. 3. A step of forming a separation groove having a predetermined width and depth in a chip separation line on a first main surface of a substrate on which a semiconductor element portion is formed, and forming the substrate on a second main surface of the substrate. From the side, a step of reducing the thickness to a predetermined thickness so as not to reach the bottom of the separation groove formed on the first main surface side, and depositing a metal thin film on the second main surface of the substrate by vapor deposition or electroless plating. Forming, a step of forming a resist pattern on the metal thin film so as to cover a region corresponding to the separation groove formed on the first main surface, and selectively using the resist pattern as a mask. A step of forming a metal layer serving as a heat sink by plating, a step of removing the resist by removing the metal thin film in this portion after the removal of the resist, and a substrate in an area where the metal thin film is removed Separating each chip by etching from the second main surface until reaching the separation groove. 4. A method according to claim 1, wherein the step of separating the chips by etching from the second main surface of the substrate in the region where the metal thin film is removed to the separation groove is performed along the region where the metal thin film is removed. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the substrate is diced to separate the chips into chips. 5. The substrate is not moved from the second main surface side of the substrate to the bottom of the separation groove formed on the first main surface side.
The step of reducing the thickness to a predetermined thickness is such that after attaching a support plate to the first main surface side of the substrate with a wax material or the like, the substrate is formed on the first main surface side from the second main surface of the substrate. 3. A step of reducing the thickness of the separation groove to a predetermined thickness so as not to reach the bottom of the separation groove.
5. The method for manufacturing a semiconductor device according to 3 or 4.