JP2923570B2 - In-circuit emulator and microprocessor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing technique, and more particularly to a technique which is particularly effective when applied to an execution instruction notification method in an instruction prefetch type microprocessor. It relates to technology that is effective for use in computers.

2. Description of the Related Art Some conventional microcomputers have a prefetch-type instruction register for prefetching some instructions in addition to the instruction to be executed. As described above, by pre-fetching a plurality of instructions into the instruction register of the prefetch method, the speed of execution of the program can be increased.

Incidentally, when a user newly develops a microcomputer system or its software, emulation is often performed to perform debugging.

In such emulation, execution of a program is interrupted when a certain instruction in the program is executed, or data on the bus is traced to a memory from a certain point. Then, by analyzing the contents of the traced memory, the cause of the runaway of the program or the like is clarified, and the debugging of the program or the system can be easily performed.

Therefore, during emulation, the data bus and the address bus are monitored to detect break points and trace points.

As described above, in a microcomputer having an instruction register for fetching a plurality of instructions in advance,
When emulation is performed, the instruction code and address appearing on the actual bus will be different from those of the instruction being executed. Therefore, it is not possible to interrupt the execution of the program at a correct breakpoint or to start tracing from a desired point, and it becomes difficult to analyze the trace contents after emulation.

Therefore, a pin is provided for outputting the difference between the address of the instruction being executed and the prefetch address, so that the instruction being executed in the instruction prefetch type microcomputer can be externally known (Japanese Patent Application Laid-Open No. Sho 62). −19
Japanese Patent Application Laid-Open No. Sho 61-286936 in which the execution of a program is interrupted each time one instruction is executed by using an interrupt function, and another instruction sequence for notifying the internal state of the microprocessor to the outside is executed. ) Has been proposed.

[Problems to be Solved by the Invention] Among the above-mentioned prior arts, in a method of providing a pin for outputting a difference between an address of an execution instruction and a prefetch address, the number of pins of the microprocessor is increased or dedicated pins are used. Since it is necessary to prepare additional chips, the cost increases and the development period becomes longer,
There is a drawback in that it cannot cope with an increase in the required information amount.

On the other hand, in the method in which the program is interrupted each time one instruction is executed, the real-time property is lost and the system may run away during emulation.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a microprocessor of an instruction prefetch system capable of notifying internal information such as an instruction address being executed to the outside without increasing the number of pins or providing a complicated external circuit. It is in.

Another object of the present invention is to provide a microprocessor which can notify internal information to the outside without deteriorating the real-time property, and which is highly flexible with respect to an increase in required information amount.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a microprocessor having a buffer or a memory capable of holding a plurality of instructions in advance has a function of inserting a special bus cycle for outputting the internal information of the processor to the outside each time one instruction is executed in a predetermined operation mode. It is to make it.

The function of inserting the special bus cycle may be realized by hardware as an external bus control circuit or a circuit attached thereto, or may be realized by firmware such as microprogram control.

The internal information of the processor to be output to the outside in the special bus cycle includes an address in the memory space of the executed instruction (a logical address is better than a physical address) and an execution instruction in a prefetched instruction group. There is a code to identify.

[Operation] According to the above-described means, in emulation of a system using a microprocessor of the instruction prefetch method, it is possible to easily know externally which instruction has been executed, so that accurate emulation control becomes possible. In addition, analysis of trace data is facilitated, and debugging efficiency is improved.

In addition, since a special bus cycle which is originally unnecessary is inserted, there is no complete real-time property.
Since it is only a cycle, the real-time property is hardly impaired as compared with the conventional method in which a predetermined instruction sequence is executed by an interrupt function or the like to notify internal information to the outside.

FIG. 1 shows an embodiment in which the present invention is applied to an instruction prefetch type microprocessor.

Although not particularly limited, each circuit block shown in FIG. 1 is formed on one semiconductor chip such as a single crystal silicon substrate.

Although not particularly limited, the microprocessor of this embodiment is provided with two FIFO instruction buffers 10a and 10b each capable of holding two 16-bit instruction codes. Also, an external bus control circuit 11 for controlling a bus cycle.
The external bus control circuit 11 can be connected to a 30-bit address bus ADB and a 32-bit data bus DTB. The external bus control circuit 11 is configured to fetch instruction codes and data from an external memory with a 32-bit width at a time via a data bus DTB. The 32-bit instruction code fetched at one time in the instruction fetch cycle is divided into two 16-bit instruction codes and stored in the two instruction buffers 10a and 10b, respectively.

The instruction word length of the microprocessor of this embodiment is
The variable length is 16 bits × n (n is a positive natural number). Further, in this embodiment, the external bus control circuit 11 is configured to generate and output 4-bit byte codes BC0 to BC3, to take in 16-bit unit instructions and to read / write data in byte units. Can also. This byte code BC0
.About.BC3 is normally generated based on the lower 1 bit of the instruction fetch pointer 15a or the lower 2 bits of a 32-bit address supplied from the arithmetic processing unit 17 via the internal bus 18.

The instruction codes stored in the instruction buffers 10a and 10b are transmitted through the selector 12 to the 16-bit instruction decoder 13 or
It can be selectively supplied to an immediate value generation circuit 14 having a 32-bit width. The selector 12 has an instruction fetch pointer 15a
The switching is performed at an appropriate timing by the control signal SC from the instruction address control circuit 15 having the following.

The instruction decoder 13 decodes the supplied instruction code, detects the instruction length, notifies the instruction address control circuit 15 by a signal WL, and activates the arithmetic control circuit 16 of the microprogram control system. The arithmetic control circuit 16 forms a control signal for an arithmetic processing unit 17 having an arithmetic unit and a general-purpose register group, and causes the instruction decoder 13 to execute processing corresponding to the instruction code.

The operation result is sent to the external bus control circuit 11 or the instruction address control circuit 15 via the 32-bit internal data bus 18.
Supplied to The data read from the external memory is supplied to the arithmetic processing unit 17 via the data bus 18.
When reading data from the outside, the data access request signal DAR is supplied from the arithmetic control circuit 16 to the external bus control circuit 11.

In this embodiment, in the instruction address control circuit 15,
Instruction fetch pointer holding instruction fetch address
Separately from 15a, an instruction code pointer 15b having a 31-bit width indicating which of the instruction codes fetched into the instruction buffers 10a and 10b is to be executed, and a program counter 15c holding a start address of the executed instruction Is provided, and the least significant 1 of the instruction code pointer 15b is provided.
The bit is supplied to the selector 12 as the selector control signal SC. The instruction code pointer 15b is
Is automatically incremented by the instruction word length based on the signal WL indicating the instruction word length of the execution instruction from.

On the other hand, 31 held in the instruction fetch pointer 15a
The bit-length instruction fetch address is stored in the external bus control circuit 11.
The external bus control circuit 11 is
Outputs 30 bits on the external address bus ADB. The instruction fetch pointer 15a is automatically updated until the instruction buffers 10a and 10b become full.

In the case of a branch instruction, the branch destination address supplied from the arithmetic processing unit 17 is set in the instruction code pointer 15b and also in the program counter 15c. The program counter 15c has a 31-bit width. For example, when the data position is indicated by a relative address, the value of the program counter 15c is stored in the internal data bus 1.
The value obtained by adding the displacement (offset) to the arithmetic processing unit 17 via 8 is output to the outside as an address. The immediate value generation circuit 14 has a 32-bit width, extracts an immediate value from an instruction word according to a control signal from the instruction decoder 13, and transfers the extracted immediate value to the arithmetic processing unit 17.

In this embodiment, a special bus cycle generation circuit 19 is provided in association with the external bus control circuit 11.

Further, an end notification signal END is supplied from the arithmetic control circuit 16 to the special bus cycle generating circuit 19 and the instruction address control circuit 15 each time one instruction is completed. Upon receiving this signal, the value of the instruction code pointer (execution instruction address) is loaded into the program counter 15c, and the least significant bit is supplied to the special bus cycle generation circuit 19. At this time, the instruction buffers 10a and 10b are cleared.

On the other hand, the special bus cycle generation circuit 19 is enabled when a mode designating signal such as a special bus cycle generation request SBR is received from the outside, and when the execution of one instruction is known, the external bus control circuit 11 Instruction (16 bits × n
(N is a natural number)). A control signal is provided so as to insert a special bus cycle for outputting to the outside whether the head of the 32-bit instruction code taken simultaneously is the upper side or the lower side.

However, the external bus control circuit 11 has a function of determining whether to give priority to a special bus cycle or another bus cycle (such as a data cycle).

The microprocessor of this embodiment outputs a signal corresponding to the least significant bit of the program counter 15c by the bytecodes BC0 to BC3 in a special bus cycle, so that the next instruction to be executed is the upper or lower of the 32 bits. Indicates the side. Moreover, in this embodiment, the instruction buffers 10a and 10b are cleared when a special bus cycle is inserted.
Even if the next instruction code is fetched once, it is fetched again in the next cycle. Therefore, the instruction code to be executed can be known by looking at the signal on the data bus in the cycle following the special bus cycle.

However, instead of outputting only information corresponding to the least significant bit of the program counter 15c when a special bus cycle is inserted, all bits of the program counter 15c may be output in a special bus cycle. In that case, the address bus and the byte code may be used together. In this way, the next execution instruction can be externally known without clearing the instruction buffers 10a and 10b.

Further, the microprocessor of this embodiment confirms that the bus cycle is a special bus cycle during execution of the special bus cycle by using a 3-bit bus access type signal BA.
It is as shown by T0-BAT2. The bus access type signals BAT0 to BAT2 are used to identify an instruction fetch cycle, a data write cycle, a data read cycle, a command transmission cycle to the coprocessor, and the like, in addition to the special bus cycle.

In the above embodiment, the special bus cycle generation circuit 19 is described as being attached to the external bus control circuit 11. However, the special bus cycle generation circuit 19 is built in the external bus control circuit 11 or configured integrally with the external bus control circuit 11. It may be.

In the microprocessor of this embodiment,
When an interrupt request is made, a response is returned to the request source using a special bus cycle. At that time, a code indicating the interrupt level 0 to 6 (the lower 2 bits are 00, 04, 08, 0C, 10,14,18). Therefore, in this embodiment, the special bus cycle for notifying the upper / lower order of the instruction to be executed next is distinguished from the special bus cycle for the interrupt response.
The code 0000001C is put on ADB.

Further, in the above embodiment, a special bus cycle for notifying the upper / lower order is inserted immediately before the execution of the instruction.
Instruction code pointer in microprocessor of embodiment shown
By loading the instruction address from 15b to the program counter 15c at the same time that the least significant bit of the previous instruction address is sent to the special bus cycle generation circuit 19 and latched, the special bus is executed after the instruction execution cycle. A cycle may be inserted so that whether the executed instruction is higher or lower is notified to the outside in the next bus cycle.

FIG. 2 shows the operation timing of each bus when the following program is executed as an example in a system using the microprocessor.

The instruction BEQ at address 100 in the above program is a branch instruction, and the operation timing when jumping to LABEL1 (address 1002) by execution of this instruction is shown in FIG.

Referring to FIG. 2, the bus access type signals BAT0 to BAT2 are output as "010" in the bus cycle S1 immediately before the bus cycle S2 for taking in the instructions a and b, and the bus cycle is a special bus cycle. It is understood. And
During this bus cycle S1, byte codes BC0 to BC3 (1101)
Specifies the first byte position of the instruction to be executed in the 32-bit instruction code to be fetched next. In the figure, the position where “0” is set among BC0 to BC3 indicates the start position of the instruction to be executed. Then, in the next bus cycle S2, the instruction code a
And b have been fetched (executed simultaneously with the fetch because the instruction register is cleared). This indicates that the instruction executed in the bus cycle S2 is b (ADD # 1, R0.w).

At the operation timing shown in FIG. 2, a special bus cycle is inserted again in the bus cycle S3 next to the bus cycle S2, and the instruction executed in the next bus cycle S4 includes the instruction word (32 bits) taken in. It informs outside whether it is higher or lower.

In FIG. 2, bytes BC0 to BC3 are stored in special bus cycle S3.
Therefore, among the instructions c and d fetched in the next bus cycle S4, the instruction c (MOV@R0.h,
R1.w). Since the instruction c is a data transfer instruction, an instruction execution end signal END is output after the data write cycle is executed in the bus cycle S5. FIG. 2 shows that a special bus cycle is inserted in the next bus cycle S6.

FIG. 2 shows only a case where a one-word instruction is executed. However, when an instruction of two or more words is executed, two or more instruction cycles are continuous as in the bus cycles S4 and S5. .

Although the microprocessor of the above embodiment is of a type in which all instructions are fetched from the outside, a method of fetching instructions from the inside may be provided by providing a cache memory inside. However, in this case, since the instruction fetched into the instruction buffer cannot be known from the outside, it is necessary to stop the operation of the cache memory in the special bus cycle insertion mode and fetch the instruction from the outside. Therefore, it is preferable that the special bus cycle request signal SBR supplied from outside is also used as a request signal for stopping the operation of the cache memory.

FIG. 3 shows a system configuration example of an in-circuit emulator that emulates a microcomputer system (user system) using the microprocessor of the above embodiment.

In FIG. 3, reference numeral 1 denotes a microcomputer system board as a user system which is developed and debugged by a user, and 2 is a substitute microprocessor which substitutes the function of the microprocessor on the user system 1 or on a bus of the user system during emulation. Trace memory that samples and accumulates signals, an emulation control unit to implement emulation and various debugging functions, sets program execution start and trace stop conditions, and stops the program or trace when the conditions are met An emulator box having a built-in breakpoint control unit and a proxy memory lent out when no memory is prepared in the user system. The emulator box 2 is connected to the user system by inserting a connector 3a at the end of a cable 3 extended from the main body into a socket for a target processor provided on the user system 1.
At the same time, the emulator box 2 has a built-in serial interface for performing data communication with a host computer, a microcomputer for controlling the serial interface, a floppy disk driver 5a, and the like via another cable 4 extended from the main body. System development device body 5
It is connected to the.

A printer connection cable 6a, a host computer connection cable 6b, and a CRT display device connection cable 6c extend from the apparatus main body 5. Reference numeral 7 denotes a probe for sampling an arbitrary signal from the user system 1.

FIG. 4 representatively shows a configuration example of the user system 1 and only a trace memory among emulators connected thereto.

In FIG. 4, reference numeral 41 denotes a microprocessor according to the present invention shown in FIG.
Is connected to a memory 43 storing programs and data, a peripheral device 44 such as a hard disk controller, a trace memory 21, and the like via a system bus 42 including an address bus ADB, a data bus DTB, a control bus CTB, and the like. .

The next page shows a part of data accumulated in the trace memory 21 by emulating the user system 1 using the microprocessor of the embodiment of FIG. 1 by the in-circuit emulator of FIG. .

In the above data string, data belonging to the column indicated by AB is a data group (absolute address) sampled from the address bus, and data belonging to the column indicated by DB is sampled from the data bus. Data group, data belonging to the column indicated by reference code BC are data groups obtained by sampling byte codes BC0 to BC3, R / W is a read / write control signal, and BAT is a bus access type signal, which is easy to understand by sampling. It is displayed after being changed to reference numerals.

In the above data sequence, the code in the DB column of the row marked PGM in the BAT column is the instruction code, and the code in the DB column of the row marked DAT is the read / write data. Also,
The data in the row labeled I / P in the BAT column is data sampled during the special bus cycle. BC in this row
By looking at the column, it is possible to know which of the upper and lower instruction codes in the DB column of the next data line has been executed.

 FIG. 5 shows a second embodiment of the present invention.

The microprocessor of this embodiment includes an instruction buffer 10
, An instruction decoder 13 and four instruction execution units 20 are provided.
Four instructions are fetched at a time, and four instructions can be processed in parallel at the same time. Thereby, the processing speed of the microprocessor is improved.

However, even if the four instructions can be processed in parallel in this way, actually, among the four instructions fetched at the same time, some instructions may wait for the result of execution of the other instruction, so they are always executed simultaneously. Not necessarily. Therefore, even if the instruction buffer 10 has only one stage, it is not known from the outside which instruction will be executed.

Therefore, in this embodiment, when a special bus cycle generation request signal BSR from the outside is input, a special bus cycle for outputting the next instruction to be executed to the external data bus every one instruction cycle is completed. A special bus cycle generating circuit 19 to be inserted is provided.

The special bus cycle generating circuit 19 outputs end signals EN from the four instruction execution units 20a to 20d when the instruction execution ends.
D1 to END4 are supplied. The end signals END1 to END4 are also supplied to the instruction address control circuit 15. The instruction address control circuit 15 is provided with a program counter and four instruction pointers indicating an instruction address by a relative value from the address in the program counter. When the end signals END1 to END4 are received, the corresponding instruction pointers are provided. Only updated. When the value of the pointer is sent to the special bus cycle generation circuit 19, a signal indicating which instruction has been executed is output on the control bus CTB.

The microprocessor of this embodiment is particularly effective for the fixed-length instruction format.

FIG. 6 shows a modification of the microprocessor of the embodiment shown in FIG.

The microprocessor of this embodiment includes an instruction buffer 10
5 differs from the embodiment of FIG. 5 only in that a switching circuit 31 is added between a to 10d and the instruction decoders 13a to 13d.

In this embodiment, the instruction buffers 10a to 10d and the instruction decoders 13a to 13d are not in a one-to-one relationship.
The instruction code captured in ~ 10d can be supplied to any instruction decoder. Therefore, if some of the four instructions fetched at the same time end first,
The instruction can be processed efficiently by putting the next instruction code into the empty instruction decoder.

The microprocessor of this embodiment is also provided with a special bus cycle generating circuit 19 so that the code of the next instruction to be executed and the instruction address can be output to the outside.

FIG. 7 shows an embodiment in which the present invention is applied to a microprocessor having a built-in cache memory.
The configuration of the entire microprocessor is almost the same as that of FIG. Hereinafter, differences between hardware will be described.

In FIG. 7, reference numeral 22 denotes a cache memory built in the microprocessor. The external bus control circuit 11 has a function of providing an instruction code to the instruction buffer 10 and a function of accessing data externally in accordance with a data access request from the instruction execution unit 20. When the instruction is fetched, the cache memory 22 is accessed first, and if a hit occurs, the instruction code in the cache memory is supplied to the instruction buffer 10; if a miss occurs, the address bus ADB is accessed to access the external memory. It has the function of going to get.

Although not particularly limited, the external bus control circuit 11 has an address conversion table 11a for converting a logical address supplied from the instruction address control circuit 15 or the arithmetic processing unit 17 via the internal bus 18 into a physical address.

In this embodiment, a microprocessor of a fixed-length instruction format is considered, and therefore, the instruction address control circuit 15 includes an instruction fetch pointer 15a and a program counter 15c.

Further, in the microprocessor of this embodiment, in a special bus cycle inserted by the special bus cycle generation circuit 19, the code of the executed instruction is output onto the data bus DTB and the logical address in the program counter 15c is identified by the instruction. It is configured to output an address on the address bus ADB.

Next, the operation of the microprocessor will be described.

The external bus control circuit 11 first converts the address indicated by the instruction fetch pointer 15a into a physical address in the address conversion table 11a, sends it to the cache memory 22 for searching, and when the hit signal H is obtained, The code is read and provided to the instruction buffer 10. The instruction code taken into the instruction buffer 10 is transferred to the instruction decoder 13 and decoded, and the instruction type, addressing mode recognition, immediate value generation, operation control information, and the like are extracted. Based on this information, the instruction execution unit 20 performs processing such as data transfer and calculation.

Then, each time the instruction execution is completed, the instruction processing end signal END is output from the arithmetic processing unit 16, and the instruction address control circuit 15 and the special bus cycle generation circuit 19 are notified of the completion of the instruction execution. When receiving the end notification of the instruction, the instruction address control circuit 15 increments the program counter 15c.

When the program branches, the branch destination instruction address created in the instruction execution unit 20 is supplied to the instruction address control circuit 15 via the internal bus 18 and set in the program counter 15c and the instruction fetch pointer 15a. .

On the other hand, if a miss occurs in the search of the cache memory 22, the translated address (physical address) is output to the external address bus ADB, the instruction code is fetched from the external memory via the data bus DTB, and stored in the instruction buffer 10. Grant. Also, the fetched instructions are simultaneously stored in the cache memory.
Send to 22 for storage.

Instruction fetching is performed until the instruction buffer 10 becomes full while automatically incrementing the instruction fetch pointer 15a. When the instruction buffer 10 becomes full, the signal FULL is supplied from the instruction buffer 10 to the instruction address control circuit 15, and the updating of the instruction fetch pointer 15a is stopped.

In the normal operation mode described above, when the instruction code is in the cache memory 22, the execution instruction inside the processor cannot be identified from outside the processor. In this embodiment, when a special bus cycle generation request signal SBR is input from the outside, the mode shifts to a special bus cycle insertion mode, and an instruction code being executed internally and an address indicating the position of the instruction are output to the outside. In this special mode, in addition to the normal mode described above, the instruction is executed inside the processor, and every time the instruction execution end signal END is output, the special bus cycle generation circuit 19 controls the external bus control circuit 11. Address bus ADB and data bus DTB, each having an empty instruction identification address and execution instruction code in parallel with the internal instruction execution.
A signal for identifying the bus access type or the data type is output on the control bus CTB as a code indicating a special bus cycle.

Thereby, the execution instruction word and the address inside the processor can be identified by the observation outside the processor. However, at this time, the external bus control circuit 11 may conflict with the original instruction word fetch or data access due to the cache miss, but when the requests of a plurality of bus cycles conflict, the external bus control circuit 11 An external bus cycle is generated according to the order. Specifically, in the special bus cycle insertion mode, a special bus cycle is generated prior to a bus cycle caused by a data access request or a cache mishit.

A special bus cycle may or may not be inserted next to the instruction fetch cycle when the processor fetches an instruction from the external memory when a cache mishit occurs. This is because such instruction fetch cycle can be identified if the external bus is monitored. However, if a special bus cycle indicating the instruction fetch cycle at the time of a mishit is not inserted after the instruction fetch cycle, the hardware becomes slightly complicated, but the speed can be increased by the absence of the special bus cycle. There is.

FIG. 8 shows the operation timing of each bus when the following program is executed in the system using the microprocessor.

The operation timing shown in FIG. 8 is a timing when the instructions a to d are already stored in the cache memory 22.

Referring to FIG. 8, the instruction a executed in the processor in the bus cycle S1 and the instruction executed in the cycle S1 on the external data bus in parallel with the execution of the instruction b in the processor in the bus cycle S2. It can be seen that the code a is output on the external address bus and its instruction address is output, and the code indicating the special bus cycle is output on the control bus.

In FIG. 8, the following instruction c (MOV@R0.h, R1.W)
Is an instruction accompanied by data access, the execution of the instruction c is stopped inside the processor, the special bus cycle is preferentially executed in the bus cycle S3, and the instruction code and address of the instruction b executed in the previous cycle are changed. You can see that it is output. The execution of the instruction c is executed in the next cycle S4 after the special bus cycle S3, and an address indicating a desired data position is on the address bus, and read data is on the data bus. The code and address of the instruction c executed in the bus cycle S4 are stored in the next bus cycle.
Output to the outside in S5. At this time, the instruction d is executed in parallel in the processor, and the code and address of the instruction d are output to the outside in the next bus cycle S6.

In the microprocessor of the embodiment shown in FIG. 7, the address of the execution instruction is output as a logical address in the special bus cycle. However, the instruction identification address supplied to the special bus cycle generation circuit 19 from the program counter 15c is used. It may be output as a physical address by passing through the address conversion table 11a.

Although the embodiment of FIG. 7 shows a microprocessor that handles fixed-length instructions, as in the embodiment of FIG.
By providing two sets of instruction buffers and adding an instruction code pointer 15b in the instruction address control circuit 15, variable-length instructions can be handled, and the present invention can be applied to a microprocessor with a built-in cache memory.

As described above, in the above embodiment, the microprocessor having a buffer or a memory capable of holding a plurality of instructions in advance is provided with a special operation mode for outputting internal information of the processor to the outside each time one instruction is executed in a predetermined operation mode. With the function to insert bus cycles, the emulation of a system using an instruction prefetch type microprocessor can be easily known externally as to which instruction was executed. This makes it possible to analyze trace data easily and improve debugging efficiency.

Also, since a special bus cycle which is originally unnecessary is not inserted, there is no complete real-time property, but only one cycle is inserted. Therefore, a predetermined instruction sequence is executed by an interrupt function or the like to send internal information to the outside. The real-time property is hardly impaired as compared with the conventional method of notifying.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in the above embodiment, the special bus cycle insertion mode is performed based on the special bus cycle generation request signal SBR from the external pin, but a flag or a register is provided in the special bus cycle generation circuit 19, and writing to the special bus cycle generation circuit 19 is performed. The mode may be shifted to the special bus cycle insertion mode.

In the above description, the case where the invention made by the present inventor is mainly applied to a microprocessor which is a utilization field as a background has been described. However, the present invention is not limited to this, and a single chip microcomputer or other program control It can be used for general-purpose data processing devices.

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the internal information such as the instruction address being executed in the instruction prefetch type microprocessor can be notified to the outside without increasing the number of pins or providing a complicated external circuit.

In addition, it is possible to realize a microprocessor that can notify internal information to the outside without deteriorating the real-time property and that is highly flexible with respect to an increase in required information amount.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a microprocessor according to the present invention, FIG. 2 is an operation timing chart in a special bus cycle insertion mode, and FIG. 3 is a perspective view showing a configuration example of an in-circuit emulator. FIG. 4 is a block diagram showing a microcomputer system using a microprocessor according to the present invention and a part of its emulation system. FIG. 5 is a block diagram showing a second embodiment of the microprocessor according to the present invention. FIG. 6 is a block diagram showing a third embodiment of the microprocessor according to the present invention. FIG. 7 is a block diagram showing a fourth embodiment of the microprocessor according to the present invention. 5 is a chart showing operation timing in a bus cycle insertion mode. 1 ... User system (microcomputer system), 2 ... Emulator box, 3,4 ... Cable, 5 ... System development device body, 11 ... External bus control circuit, 15 ... Instruction address control circuit, 18 ... ... system bus, 19 ... special bus cycle generation circuit, 20 ... instruction execution unit.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshiyuki Kondo 111 Nishiyokote-cho, Takasaki City, Gunma Prefecture Inside the Takasaki Plant of Hitachi, Ltd. No. Hitachi Microcomputer Engineering Co., Ltd. (56) References JP-A-1-201737 (JP, A) JP-A-1-137339 (JP, A) (58) Fields studied (Int. Cl. ⁶ , (DB name) G06F 11/28-11/34

Claims (5)

(57) [Claims] 1. A trace memory for collecting and accumulating signals on a bus during emulation for program debugging, a microprocessor, and a breakpoint control for collecting signals to the trace memory and stopping the above. An in-circuit emulator comprising: an instruction buffer for holding a plurality of instructions fetched from an external memory; an instruction buffer coupled to the instruction buffer, decoding the fetched instruction, and a decoding result. An instruction decoder coupled to the instruction decoder and executing a process corresponding to the instruction in accordance with the decoding result; and an instruction coupled to the instruction execution unit and holding an address of the instruction to be taken into the instruction buffer. An address control circuit including a fetch pointer; An instruction buffer coupled to the instruction execution unit and the address control circuit, based on a special bus cycle request signal from the breakpoint control circuit and a signal indicating the end of one instruction output from the instruction execution unit. A bus cycle control circuit having a function of inserting a bus cycle for outputting internal information to enable external debugging of a program after execution of one instruction and before execution of the next instruction; An in-circuit emulator wherein a buffer, an instruction decoder, an instruction execution unit, an address control circuit, and a bus cycle control circuit are formed on one semiconductor chip. 2. The in-circuit emulator according to claim 1, wherein said bus cycle control circuit outputs a signal indicating an instruction executed as said internal information. 3. A microprocessor capable of executing a plurality of instructions in parallel, comprising: a plurality of instruction buffers for holding a plurality of instructions fetched from an external memory; An instruction decoder for decoding an instruction and outputting a decoded result; an instruction executing unit coupled to the instruction decoder, for executing processes corresponding to a plurality of instructions in parallel according to the decoded result; An address control circuit including an instruction fetch pointer for holding an address of an instruction to be fetched into the instruction buffer; and an instruction control unit coupled to the instruction buffer, the instruction execution unit, and the address control circuit. Between the execution of two different instructions based on the output signal indicating the end of one instruction. And a bus cycle control circuit having a function of inserting a bus cycle for outputting internal information for enabling internal buses to the outside. A microprocessor, wherein the control circuit is formed on one semiconductor chip. 4. The microprocessor according to claim 3, wherein said bus cycle control circuit outputs a signal indicating an executed instruction as a signal indicating said internal information. 5. The microprocessor according to claim 3, wherein the special bus cycle request signal is supplied from a predetermined circuit external or internal to the microprocessor.