JP2925826B2 - Digital signal recording / reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the recording and reproduction of digital signals, and more particularly to a digital signal recording method suitable for recording and reproducing digital data in a specific area by dividing an area on a recording medium by a rotary head. It relates to a playback device.

[0002]

2. Description of the Related Art In an apparatus for recording and reproducing PCM audio signals, a RAM for temporarily storing PCM data is usually used.
Since the access amount per unit time is almost constant, the access cycle is often fixed. In addition, in the access to the RAM, it is necessary to read and write data at different frequencies in parallel, and the access slot design for this becomes complicated. For example, during recording, input of PCM data from the A / D converter, data input / output to / from the encoder, and data output to the recording medium are performed in parallel. At the time of reproduction, input of reproduction data from the recording medium, decoding When data input / output to / from the data and data output to the D / A converter are performed in parallel, the access cycle of the RAM is determined by the transmission rate of the data transmitted at the highest speed. Depends on the transmission rate of recording and reproduction.

As an example of an apparatus for recording and reproducing digital signals, a PCM signal recording and reproducing apparatus as described in, for example, JP-A-62-86584 is known.
In this method, data reading and writing can be performed in parallel by selectively using the access timing of the RAM for even-numbered access slots and odd-numbered access slots. In addition, it is possible to perform the processing with one system of RAM, regardless of the plurality of RAMs.

[0004]

In the above-mentioned conventional PCM recording / reproducing apparatus, the recording / transmission rate per byte is 94.
Since it is not so high as 0 kHz, the timing cycle of the access slot of the RAM is always fixed, and as described above,
Use access slots for writing and reading, RAM
However, if the transmission rate further increases, the access slot frequency also increases. In general, the power consumption of a digital signal processing circuit is proportional to its operating frequency. Therefore, when the transmission rate increases, the power consumption increases. Also, the recording transmission rate
RAM access speed in encoding, decoding, and audio systems not affected by the
The problem of an increase in the critical path of the signal processing circuit occurs.

[0005] When a video signal and a PCM audio signal are divided into areas for each track on a magnetic tape and recorded as in the case of overlap recording and reproduction of a PCM audio signal in a VTR, the PCM audio signal is output. If the length of the area to be recorded is short, it is wasteful to always set the access slot cycle to a very short cycle at the time of recording and reproduction.

An object of the present invention is to provide a digital signal recording / reproducing apparatus which solves such a problem and can avoid an increase in power consumption and a critical path of a signal processing circuit even when a recording / transmission rate is high. It is in.

[0007]

In order to achieve the above object, according to the present invention, a slot cycle for accessing a RAM is defined by a data recording or reproducing period in a recording medium and a period other than the period. Make it different.

[0008]

The slot frequency for accessing the RAM at the time of recording or reproduction on the recording medium is determined by the recording transmission rate and is high, but during other periods the data transmission rate is low. The slot frequency for accessing the RAM is set low. As a result, the average access slot frequency becomes lower than that when the access slot frequency is always used for recording and reproduction.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings, taking a home high definition VTR as an example. FIG. 1 is a block diagram showing an embodiment of a digital signal recording / reproducing apparatus according to the present invention, wherein 1 is a magnetic tape, 2 is a rotary cylinder, 3 is a recording / reproducing switch, 4 is a reproducing amplifier, and 5 is a recording amplifier. Amplifiers 10, 11 are crystal oscillators, 15 is a data bus, 19 is an audio signal output terminal, 20 is an audio signal input terminal, and 21 is a segmentation circuit.

In FIG. 1, a rotary cylinder 2 is provided with two pairs of magnetic heads H1 and H2 and H3 and H4, and these two pairs are provided to face each other. The magnetic tape 1 travels in a spiral shape over substantially 180 ° around the outer circumference of the rotary cylinder 2. Therefore, each time the rotary cylinder 2 rotates half a turn, each head pair alternately
, But data is recorded and reproduced by the magnetic heads H1 and H1.
This is repeated in the order of 2, H3 and H4. The rotary cylinder 2 rotates at twice the speed of a home NTSC VTR. Therefore, the rotary cylinder 2 rotates at a cycle of one field, and one track is formed on the magnetic tape 1 for each half turn, and data is recorded for each half field on each track. Thus, a high recording density is realized.

The audio signal is a PCM signal (PCM audio signal)
In this case, the error correction code, interleave and the like are used for the S-VHS format using the format of the PCM audio signal in the existing S-VHS VTR.
In the PCM audio signal in the format, data for one field is divided into four segments, and is recorded in a predetermined area of each track on the magnetic tape 1.

The recording area of the PCM audio signal on the magnetic tape 1 is, as shown in FIG.
The PCM audio signal is recorded in the area 25 corresponding to the period during which the rotary cylinder 2 rotates by 10 ° in the track formed by the rotation of 0 °, which is compressed in the time axis in such a very narrow area. . Therefore, the recording transmission rate
The frequency is as high as 38.592 Mbps.

In FIG. 1, the existing S-VHS
A signal processing circuit for the PCM audio signal is used.
A processing circuit 21 for segmentation is newly provided. Here, first, a basic operation at the time of recording of this embodiment shown in FIG. 1 will be described with reference to FIG.

The rotary cylinder 2 is driven by a servo circuit 7
The rotation is controlled as described above, and the servo circuit 7 generates a head switching signal SWH of 60 Hz and a signal SWH 'of 30 Hz synchronized in phase with the head switching signal SWH. The audio signal Ain input from the input terminal 20 is
8, the signal SW is subjected to processing such as encoding for adding a parity for error correction performed during reproduction in accordance with the S-VHS PCM audio format.
The signal is supplied to the block processing circuit 17 in the segmenting circuit 21 as a PCM audio signal Asg synchronized with H ′. The block processing circuit 17 divides the PCM audio signal Asg into four segments for each field and temporarily stores them in the RAM 16. The transmission rate at this time is the P rate of the S-VHS system.
327.5 kHz per byte according to the CM audio standard
z.

On the other hand, the area generating circuit 8 sets an area (recording area 25 in FIG. 2) for recording a PCM audio signal on each track on the magnetic tape 1 from the edge timing of the head switching signal SWH. A PCM area signal PE that matches the timing at which the magnetic head scans is generated. When the PCM area signal PE is “H” (high level),
RA at a high transmission rate of 7.72 MHz per byte
The above-mentioned blocked PCM audio signal is read from M16, that is, read out after being compressed in the time axis, and subjected to predetermined processing by the recording / reproducing processing circuit 6, and then as recorded PCM audio data Ard. The data is supplied to the magnetic head via the recording amplifier 5 and the switch 3 and is recorded on the recording area 25 shown in FIG.

At the time of reproduction, as shown in FIG. 3B, when the PCM area signal PE is "H", PCM audio data is reproduced from the recording area 25 of the magnetic tape 1 (FIG. 2). PCM via switch 3 and playback amplifier 4
After being processed as audio data Apd by the recording / reproducing processing circuit 6, it is temporarily stored in the RAM 16 at a high transmission rate of 7.72 MHz per byte.

Thereafter, the reproduced PCM is read from the RAM 16.
The audio data is read out at a transmission rate of 327.5 kHz per byte, that is, read out after being expanded on the time axis, processed by the block processing circuit 17, and then output as a block output signal Abs. The signal is supplied to a processing circuit 18 and subjected to processing such as error correction, deinterleaving, and D / A conversion, and is output from an output terminal 19 as an audio signal Aot.

The above is the basic operation of this embodiment from the viewpoint of the flow of the audio signal. When this operation is performed, the RAM 16 is accessed when data is transmitted to and from the recording / reproducing processing circuit 6. A transmission rate as high as 7.72 MHz is required, and to achieve this, 100 n
It is necessary to access the RAM 16 with a cycle time of less than sec. As a result, the operating frequency of the entire signal processing circuit increases, and the number of critical paths increases. In general, the power consumption of a digital signal processing circuit is proportional to the operating frequency. Therefore, cooling means for preventing unnecessary radiation and temperature rise are also required.

However, when data transmission is performed between the RAM 16 and the signal processing circuit 18, 327.5 kHz is required.
Since the transmission rate is low, the access slot frequency of the RAM 16 is increased only during a period during which data is transmitted to and from the recording / reproducing processing circuit 6 (hereinafter referred to as a PCM period). , The access slot frequency is lowered. According to this, the RAM 16
, The average access slot frequency becomes lower, and the power consumption can be reduced.

In order to realize this, in this embodiment, slot generating circuits 12 and 13 and a selecting circuit 14 are provided, and the slot generating circuit 12 operates a clock generating circuit operated by the crystal oscillators 10 and 11. 9 to the access clock CK1 of the RAM 16 having the access slot frequency f ₁ and the slot generation circuit 1
3, the access slot frequency f ₂ (f ₁ <
f ₂ ), the selection clock 14 generates the access clock CK 2 for the RAM 16. When the PCM area signal PE is “L” (low level), the selection circuit 14 generates the clock CK 1.
, When the clock is “H”, the clock CK2 is selected, and R
AM16, recording / reproduction processing circuit 6, block processing circuit 1
7 is supplied. In the RAM 16, when writing the output signal of the blocking processing circuit 17 or supplying the signal to the blocking processing circuit 17, the access slot frequency is set to f _1, and when transmitting data to and from the recording / reproducing processing circuit 6, the slot frequency and f _2.

Here, for example, f ₂ = 15.4 MHz
(2 times 7.72 MHz), f ₁ = 960 kHz (f ₂
/ 16), the access slot timing of the RAM 16 in this case is as shown in FIG. That is, at the time of recording, as shown in FIG.
The segmented PCM audio signal Asg supplied to the RAM 16 has a cycle of about 3 μsec per byte, and the cycle of the access slot is 1 / f _{1 11} μsec. Of, ie, about 3
The data is written to the RAM 16 in the access slot 40 at an interval of μsec. In the PCM period, the cycle of the access slot of the RAM 16 is 1 / f ₂ 265 nsec.
1 in the period of about 65 nsec indicated by hatching in the figure.
PCM from RAM 16 in every other access slot 41
The audio data is read out, and about every 3 μs indicated by hatching with a horizontal line in the other access slots of every other access slot
The segmented input signal Asg is written into the RAM 16 in the access slot 42 at the interval c.

During reproduction, as shown in FIG. 4B, the access slot timing of the RAM 16 is the same as during recording, and outside the PCM period, the block output signal Abs is output at every third access slot 40. The read PCM audio data Apd is read out from the RAM 16 at every other access slot 41 during the PCM period, and is written into the RAM 16 at intervals of about 3 μsec.
Reads the blocked output signal Abs. However, since the reproduced PCM audio data Apd generally contains jitter, it does not become a constant frequency, and therefore, unlike recording, it does not always occur every other access slot.

In this embodiment, since the PCM period has a time width that is 1/18 times as long as one track period, the access slot timing as described above is used in the RAM 16 so that an average access slot frequency of 1.3 MHz is used. A transmission rate of 0.72 MHz can be realized, and power consumption can be reduced. By the way, the whole period is 7.7
Compared to the case where the access slot of the RAM 16 is configured at 2 MHz, the power consumption is about 1/6 times that of the case where the access slot is configured, and the power consumption can be significantly reduced.

In the above frequency setting, the access slot in the PCM period is set to the transmission rate in order to simplify the description.
In the other than the PCM period, the frequency is set to 1/16 of the PCM period. However, in practice, a lower frequency may be used, and it is easy to further lower the average access slot frequency.

FIG. 5 is a block diagram showing another embodiment of the digital signal recording / reproducing apparatus according to the present invention, wherein 50 is a crystal oscillator, 51 is an error correction circuit, 52 is an interpolation circuit,
Reference numeral 3 denotes a voice input processing circuit, and portions corresponding to those in FIG.

The embodiment shown in FIG. 1 is based on the existing S-VHS.
Although the PCM audio signal signal processing circuit of the system is used as it is, in the embodiment shown in FIG. 5, encoding and decoding processes from audio input / output to recording / reproducing data input / output are performed by one system of RAM. It is made possible.

First, the basic operation of this embodiment will be described with reference to FIG. The operation at the time of recording will be described with reference to FIG. 6A. The PCM audio signal Ain ′ input from the input terminal 20 is processed by the audio input processing circuit 53 into four segments for each field. It is temporarily stored in the RAM 16. The processing written in the RAM 16 is as follows.
As shown in FIG. 6A, the operation is always performed at a constant frequency determined by the sampling frequency. The PCM audio data written to the RAM 16 is read once and supplied to the error correction circuit 51, where the parity is added (encoded) and written to the RAM 16 again. After a while
The PCM audio data to which the parity is added is read out from the RAM 16 after being compressed on the time axis and processed by the recording / reproducing processing circuit 6, and then as the recording PCM audio data Ard via the recording amplifier 5 and the switch 3 via the recording amplifier 5. H1, H2, H
3, supplied to H4 and recorded on magnetic tape 1.

At the time of reproduction, as shown in FIG. 6B, the reproduction PCM audio data Apd compressed on the time axis from the magnetic tape 1 is transmitted via the switch 3 and the reproduction amplifier 4 to a recording / reproduction processing circuit. Is input to
The data is written to the RAM 16. The reproduced PCM audio data stored in the RAM 16 is temporarily expanded on the time axis, read out, supplied to the error correction circuit 51, and subjected to error correction (decoding) by the parity added at the time of recording. Is written to the RAM 16 again. In this decoding process, a correction result flag is generated, and the processed reproduction PC
It is added to M audio data. Thereafter, the reproduced PCM audio data and the flag of the error correction result are read from the RAM 16 and supplied to the interpolation circuit 52, and the data for which error correction by the error correction circuit 51 becomes impossible is subjected to average value interpolation. Are processed as the audio output signal Aot.
Output from The process of reading the reproduced PCM audio data into the interpolation circuit 52 is always performed at a constant frequency determined by the sampling frequency, as shown in FIG.

In this embodiment, similarly to the embodiment shown in FIG. 1, the clocks CK1, C2 for the access slot are selected by the selection circuit 14 between the PCM period and the outside of the PCM period.
By switching K2, the average access slot frequency is lowered, thereby reducing power consumption. Further, as shown in FIG. 6, encoding and decoding are not performed during the PCM period, whereby the access from the error correction circuit 51 to the RAM 16 for encoding and decoding is performed. Does not need to be performed at a high frequency according to the recording / transmission rate,
It is possible to prevent an increase in critical paths in circuit design.

FIG. 7 shows that the access slot frequency f ₂ = 1
5.4 MHz (the same frequency as in FIG. 4), f ₁ = 3.
Shows the RAM16 access slot timing when a 86MHz (f _2/4).

Outside the PCM period, as shown in FIG. 7A, the access slots 70 indicated by horizontal lines are hatched.
At the time of recording, data is written from the audio input processing circuit 53 to the RAM 16 at the time of recording. At the time of reproduction, data is read from the RAM 16 to the interpolation circuit 52. The RAM 16 is accessed for data transmission with the RAM 51. Generally, it is necessary to increase the number of accesses to the RAM 16 for data transmission with the error correction circuit 51. Therefore, the access slot frequency outside the PCM period is higher than that in FIG. Is 3.86 MHz as described above.

The input / output PCM audio data Ain
'And Aot' have a sampling frequency of 48 kHz.
In (a), R is performed four times for one sample data.
The AM 16 is accessed because the sample data of the PCM audio data is composed of two bytes, and needs to be accessed twice for each byte. This is because at least two accesses are required to read the resulting flag.

During the PCM period, as shown in FIG. 7B, every other access to recording data or reproduction data at a transmission rate of 7.72 MHz per byte is performed. , That is, access slots 73 indicated by hatching with diagonal lines (however, at the time of reproduction, the intervals are not necessarily every other access slot due to jitter). Access slots 74 shown hatched with horizontal lines
In recording, data is written from the audio input / output circuit 53, and in reproduction, data is read from the interpolation circuit 52. During the PCM period, since the encoding or decoding process is not performed as described above, the RAM 1 is not used except for the access slots 73 and 74.
6 is not accessed.

By using the above-described access slot timing for the RAM 16, the average access slot frequency becomes 4.5 MHz, which is about ３ of the power consumption when all the access slot frequencies are set to f _2. Can be reduced by 70%.

Although the above f ₁ and f ₂ are set to the frequencies synchronized with the recording transmission rate (7.72 MHz), the frequencies synchronized with the sampling frequency may be set. FIG. 8 shows that f ₁ = 3.072 MHz (64 kHz of 48 kHz).
₂ ) and the access slot timing of the RAM 16 when f ₂ = 12.288 MHz (4f ₁ ). However, FIG. 5A is outside the PCM period, and FIG.
Is within the PCM period.

In this case, the access slot of the RAM 16 at the time of data transmission with the audio input / output circuit 53 or the interpolation circuit 52 can be fixed during the audio area period indicated by reference numeral 80 in the figure. Design becomes easier.
However, in the PCM period, it is necessary to give the highest priority to the access to the RAM 16 when transmitting data to and from the recording / reproducing processing circuit 6. Therefore, in FIG. By using an access slot that does not access the RAM 16 for data transmission in the reproduction processing circuit 6, the audio input / output circuit 53 or the interpolation circuit 5
It is necessary to access the RAM 16 in data transmission between the RAM 16 and the RAM 16.

Therefore, in the example shown in FIG.
The ratio of the access slot frequency of the RAM 16 to the RAM 16 is 1.8
8: 3, an empty access slot always occurs at a rate of once in three access slots.
1 is 12 access slots, and the access to the RAM 16 in data transmission with the audio input / output circuit 53 or the interpolation circuit 52 is performed in an empty access slot using a period of 3 access slots for 1 byte. Good.

Further, other options such as synchronizing the access slot of the RAM 16 with the sampling frequency during the PCM period and synchronizing with the recording transmission rate outside the PCM period are also possible. The clock frequencies f ₁ and f ₂ with a low critical path can be selected.

[0039]

As described above, according to the present invention,
Even when recording / reproducing at a high transmission rate in a short area with respect to the whole, the average access frequency of the RAM can be lowered, so that the power consumption in the signal processing circuit can be reduced. The critical path can be reduced, and the temperature characteristics and the yield of the LSI are greatly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a digital signal recording / reproducing apparatus according to the present invention.

FIG. 2 is a diagram showing a recording format on a magnetic tape in FIG. 1;

FIG. 3 is a timing chart showing operations during recording and reproduction in the embodiment shown in FIG. 1;

FIG. 4 is a timing chart showing an operation of a RAM access slot in FIG. 1;

FIG. 5 is a block diagram showing another embodiment of the digital signal recording / reproducing apparatus according to the present invention.

6 is a timing chart showing an operation at the time of recording and at the time of reproduction in the embodiment shown in FIG. 5;

FIG. 7 is a timing chart showing one operation example of a RAM access slot in FIG. 5;

FIG. 8 is a timing chart showing another operation example of the RAM access slot in FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 magnetic tape 2 rotating cylinder 6 recording / reproducing processing circuit 8 area generating circuit 12 access slot generating circuit A 13 access slot generating circuit B 14 selecting circuit 16 RAM 17 blocking processing circuit 34 PCM area signal 51 error correction circuit 52 interpolation circuit 53 Audio input / output circuit

Claims (12)

(57) [Claims] At least a signal input from the outside is A
Storage means for temporarily storing a digital signal subjected to / D conversion or a digital signal input from the outside as recording data, and storing the recording data stored in the storage means only in a specific area on the recording medium In a digital signal recording / reproducing apparatus for recording, the storage circuit includes a period in which the recording data is read from the storage unit and recorded in the specific area on the recording medium, and a period in which the recording data is written in the storage unit. A digital signal recording / reproducing apparatus provided with means for making the access cycle of the digital signal different. 2. An apparatus according to claim 1, wherein said means generates an area signal indicating a period during which said recording data is recorded in a specific area on said recording medium, and generates a first clock. A first slot generating circuit for generating a second clock having a frequency different from the first clock, and selecting the first clock outside the signal period of the area signal Selecting means for selecting the second clock within the signal period of the area signal, and accessing the storage means at the frequency of the clock selected by the selecting means. Signal recording / reproducing device. 3. The digital signal recording / reproducing apparatus according to claim 2, wherein the frequency of the first clock is lower than the frequency of the second clock. 4. The recording medium according to claim 1, wherein the recording data is not recorded in the specific area on the recording medium during a part or all of a period during which the recording data is not recorded. A digital signal recording / reproducing apparatus characterized in that a video signal is recorded in an area of (1). 5. A digital signal recorded in a specific area divided into areas on a recording medium is reproduced, and the reproduced digital signal is temporarily stored in a storage means as reproduction data. A digital signal recording / reproducing apparatus configured to read out the digital signal from the specific area on the recording medium, and a digital signal from the specific area on the recording medium. A digital signal recording / reproducing apparatus characterized in that an access cycle of the storage means is made different from a period during which the data is not reproduced. 6. The apparatus according to claim 5, wherein the means includes: an area generating means for generating an area signal indicating a period for reproducing the specific area on the recording medium; and a first slot generating means for generating a first clock. Means, second slot generating means for generating a second clock having a different frequency of the first clock, selecting the first clock outside the signal period of the area signal,
A selection circuit for selecting the second clock within the signal period of the area signal, and accessing the storage means at the frequency of the clock selected by the selection means. Playback device. 7. The digital signal recording / reproducing apparatus according to claim 6, wherein the frequency of the first clock is lower than the frequency of the second clock. 8. The method according to claim 5, wherein in a part or all of the period other than the specific region,
A digital signal recording / reproducing apparatus for reproducing a video signal. 9. At least a signal input from outside
Storage means for temporarily storing a digital signal subjected to / D conversion or a digital signal input from the outside as recording data, and storing the recording data stored in the storage means only in a specific area on the recording medium A digital signal recording / reproducing apparatus for recording and temporarily storing a signal reproduced from the specific area of the recording medium as reproduction data in the storage means and reading out and outputting the signal as the output signal. A first period in which the recording data is recorded in the specific area above, and a first period in the recording mode.
A third period in which the access period of the storage means is made different from the second period other than the period, and the reproduction data is reproduced from the specific area on the recording medium in the reproduction mode; 2. A digital signal recording / reproducing apparatus comprising: means for making the access frequency of the storage means different from a fourth period other than the third period. 10. The apparatus according to claim 9, wherein said means comprises: an area generating means circuit for generating an area signal representing said first period and said third period; and a first slot generating circuit for generating a first clock. Means, a second slot generating means for generating a second clock having a frequency different from the frequency of the first clock, and selecting the second clock during a signal period of the area signal, A digital signal recording / reproducing apparatus, comprising a selecting means for selecting the first clock outside the signal period, wherein the storage means is accessed at the frequency of the clock selected by the selecting means. 11. The digital signal recording / reproducing apparatus according to claim 10, wherein the frequency of the first clock is lower than the second frequency. 12. The method according to claim 9, wherein a video signal is recorded during part or all of the second period, and a video signal is reproduced during part or all of the fourth period. A digital signal recording / reproducing apparatus characterized by the following.