JP2927273B2 - Clock skew correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly, to a clock skew correction circuit for correcting a phase shift of a clock signal and a semiconductor integrated circuit having the same.

[0002]

2. Description of the Related Art In recent years, as the degree of integration of semiconductor integrated circuits has increased and their size has increased (increased in scale), wiring lengths in the semiconductor integrated circuits, particularly clock signals, have been supplied to each functional block. Therefore, the delay of the clock signal cannot be ignored. That is, the phase of the clock signal commonly supplied to a plurality of functional blocks is shifted between the functional blocks, which hinders the high-speed operation of the entire semiconductor integrated circuit.

As a conventional technique for correcting a phase difference between clock signals, a feedback path is provided corresponding to a path for supplying a clock signal as described in, for example, Japanese Patent Application Laid-Open No. 6-273478. A phase comparison between the clock signal waveform of the feedback path and the reference clock signal waveform is performed, and a variable delay circuit provided in the clock supply path is adjusted based on a result of the phase shift detection to reduce the clock skew in the clock distribution system. There is known a technique of correcting.

FIG. 2 is a block diagram showing an example of a conventional clock skew correction circuit. In FIG.
Is an external input terminal of a reference clock, 102 is an external input terminal of a clock signal, 111 and 112 are input buffers, 121
Denotes a phase comparator, 122 denotes a control circuit, 123 denotes a variable delay circuit, 124 denotes a clock distribution system, 125 denotes a flip-flop, and 131 denotes a feedback path.

The operation of this conventional clock skew correction circuit will be described. As shown in FIG.
2 is input to the input buffer 112,
Through the variable delay circuit 123 and the clock distribution system 124,
The signal is supplied to the flip-flop 125.

The clock signal output from the clock distribution system 124 is supplied to a phase comparator 121 by a feedback path 131.
Is input to one of the input terminals. The other input terminals of the phase comparator 121 are connected to the input buffer 1 from the external input terminal 101.
The reference clock signal input through 11 is input. The phase comparator 121 performs a phase comparison operation between the reference clock signal and the clock signal that has passed through the feedback path 131 from the clock distribution system 124, and outputs the comparison result to the control circuit 122 as a signal.

The control circuit 122 that has received the phase comparison result signal outputs a control signal for advancing or delaying the phase of the clock signal to the variable delay circuit 123 in accordance with the phase comparison result.

The variable delay circuit 123 adjusts the phase of the clock signal by increasing or decreasing the delay according to the received control signal for adjusting the phase.

As described above, the clock skew is reduced by matching the phases of the reference clock signal and the clock signal output from the clock distribution system.

[0010]

However, the above-described conventional clock skew correction circuit has the following problems.

(1) The first problem is that when the semiconductor integrated circuit is miniaturized, the input buffer 11 may be changed due to variations in device characteristics, changes in temperature, power supply voltage, and the like.
This means that the variation of the characteristic 1 becomes large, and the reference clock signal itself, which is the basis for adjusting the phase of the clock signal, may vary.

(2) The second problem is that a plurality of clock skew correction circuits are used in the same semiconductor integrated circuit, or a similar clock skew correction circuit is used in another semiconductor integrated circuit. The output load condition of the input buffer 111 of the reference clock signal may be different. In such a case, the input buffer 1 of the reference clock signal
11 means that the accuracy of the clock skew correction is affected.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to reduce the occurrence of clock skew and to input a reference clock signal. An object of the present invention is to provide a clock skew correction circuit that absorbs variations in the characteristics of a buffer, improves the performance of the clock skew correction circuit, and consequently speeds up the entire system.

[0014]

In order to achieve the above object, a clock skew correction circuit according to the present invention comprises: a clock feedback path formed corresponding to a clock distribution system for distributing a clock signal; Means for correcting the clock signal by a delay of an input buffer for inputting the reference clock signal into the semiconductor integrated circuit, provided in the middle of the path, a clock signal passing through the means for correcting the clock signal, A phase difference detection unit for detecting a phase difference from the clock signal; a unit for generating a control signal for adjusting a delay time of the clock signal based on a result of the phase difference detection; Means for making the delay time of the clock signal variable.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. In a preferred embodiment, the clock skew correction circuit of the present invention has an input buffer (111 in FIG. 1) to which a reference clock signal is input, and a control for receiving a signal of a phase comparison result as an input and outputting a control signal corresponding to the input buffer. A circuit (122 in FIG. 1), a control signal and a normal clock signal are input, and the propagation delay time of the normal clock signal is increased / decreased in accordance with the control signal to advance the phase of the input normal clock signal. Alternatively, a variable delay circuit (12 in FIG. 1) that outputs a delayed clock signal
3) and a clock distribution system (FIG. 1) that distributes a clock signal to a functional block such as a flip-flop in a semiconductor integrated circuit by using an output clock signal from a variable delay circuit as an input.
124), a clock signal from the clock distribution system is input to a first input terminal through a feedback path (131 in FIG. 1), and a signal immediately before an input buffer of the reference clock signal is input to a second input terminal. Then, a signal immediately after the input buffer of the reference clock signal is input to a third input terminal, and a clock signal which is a first input signal based on phase difference information between the second input signal and the third input signal. A delay correction circuit (126 in FIG. 1) for correcting and outputting the delay of the reference clock signal, and an output signal of the input buffer of the reference clock signal is input to a first input terminal, and the delay input circuit of the delay correction circuit is input to a second input terminal. Input the output signal and
Phase comparator for comparing the phases of two input signals and outputting a signal of the phase comparison result to the control circuit (121 in FIG. 1)
And

In the embodiment of the present invention, the delay correction circuit uses a clock feedback path (FIG. 1) based on the phase difference between the input signal of the input buffer (111 in FIG. 1) to which the reference clock signal is input and the output signal thereof. Of the clock signal 131). For this reason, in addition to the clock skew reduction effect in the clock distribution system, it is possible to correct even the input buffer characteristic variation of the reference clock signal, thereby further improving the clock skew reduction.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In FIG. 1, reference numeral 101 denotes an external input terminal for supplying a reference clock signal to a semiconductor integrated circuit;
Is an external input terminal that normally supplies a clock signal to the semiconductor integrated circuit, 111 and 112 are input buffers, 121 is a phase comparator, 122 is a control circuit, 123 is a variable delay circuit,
24 is a clock distribution system, 125 is a synchronization circuit such as a flip-flop, 126 is a delay correction circuit, and 131 is a clock feedback path.

Next, the operation of this embodiment will be described.

As shown in FIG. 1, a reference clock signal is input from an external input terminal 101 of a semiconductor integrated circuit through an input buffer 111 to a first input terminal of a phase comparison circuit 121. The output signal of the delay correction circuit 126, which is a feature of the present invention, is input to the second input terminal of the phase comparator 121, and the phase comparison operation between the reference clock signal and the output signal from the delay correction circuit 126 is performed.

As a result, a signal indicating whether the phase of the normal clock signal is advanced or delayed is output based on the phase comparison,
Input to the control circuit 122. The control circuit 122 outputs to the variable delay circuit 123 a control signal indicating how much the phase of the normal clock signal is adjusted in accordance with the input signal from the phase comparison circuit 121.

The variable delay circuit 123 adjusts the delay circuit based on the control signal input from the control signal, changes the phase of the clock signal input from another input terminal, and outputs the clock signal to the clock distribution system 124.

The clock distribution system 124 distributes the clock signal whose phase is adjusted and output from the variable delay circuit 123 to a synchronization circuit 125 such as a flip-flop.

The clock signal output from the clock distribution system 124 passes through the feedback path 131 and
6 is input to the third input terminal.

A first input terminal of the delay correction circuit 126 is input from the external input terminal 101 to the input buffer 11
The reference clock immediately before the first input terminal is input, and the reference clock signal output from the input buffer 111 and immediately before the input terminal of the phase comparator 121 is input to the second input terminal.

The delay correction circuit 126 detects a delay between the reference clock signals input from the first and second input terminals before and after the input buffer 111 of the reference clock signal.
Then, based on the delay amount information detected here, the phase of the clock signal returned from the output of the clock distribution system 124 by the feedback path 131 and input from the third input terminal is adjusted. Output.

The cause of the clock skew is a delay difference of a clock distribution system or the like, and a variation in device characteristics. By suppressing the clock skew as much as possible, a synchronous circuit operating in synchronization with a clock signal operates at high speed. By using a semiconductor integrated circuit having such a built-in clock skew correction circuit or the like, the entire system such as a computer can be operated at high speed.

In the conventional example shown in FIG. 2, the clock skew is reduced by returning the output of the clock distribution system to the phase comparator through the feedback path and comparing and matching the phase with the reference clock signal.

In the clock skew correction circuit of this embodiment, in addition to the clock skew adjustment of the conventional example, the delay of the portion of the reference clock signal from the external input terminal of the semiconductor integrated circuit to the input of the phase comparator, and the variation in device characteristics. By performing the correction, it is possible to further reduce the clock skew.

[0030]

As described above, according to the present invention,
The clock skew in the clock distribution system can be reduced, and in addition, the delay of the input section of the reference clock signal, which serves as a reference for adjusting the phase of the clock signal, and the variation in device characteristics can be corrected. Can be reduced.

The reason is that, in the present invention, the delay correction circuit corrects the delay of the clock signal from the clock feedback path based on the phase difference between the input signal of the input buffer to which the reference clock signal is input and the output signal. Depending on the configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a clock skew correction circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a conventional clock skew correction circuit.

[Explanation of symbols]

 Reference Signs List 101 external input terminal 102 external input terminal 111 input buffer 112 input buffer 121 phase comparator 122 control circuit 123 variable delay circuit 124 clock distribution system 125 flip-flop 126 delay correction circuit 131 clock feedback path

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ identification code FI H03K 5/00 S (58) Fields investigated (Int.Cl. ⁶ , DB name) G06F 1/10 H03K 5/13 G01R 31 / 28

Claims (2)

(57) [Claims] A clock feedback path formed corresponding to a clock distribution system for distributing a clock signal; and a clock feedback path provided in the middle of the clock feedback path for inputting a reference clock signal into the semiconductor integrated circuit. Means for correcting the clock signal by an amount corresponding to the delay of the input buffer; phase difference detecting means for detecting a phase difference between the clock signal passing through the means for correcting the clock signal and the reference clock signal; A clock skew comprising: means for generating a control signal for adjusting a delay time of the clock signal based on the result; and means for varying the delay time of the clock signal in response to the control signal. Correction circuit. 2. A clock signal input from a clock input terminal via a first input buffer and inserted into a path for feeding back a clock signal output from a clock distribution system to a synchronous circuit from a clock distribution system for inputting a reference clock signal. A delay correction circuit that corrects and outputs a delay time of a clock signal input from the feedback path based on a phase difference immediately before an input terminal and an output terminal of a second input buffer, that is, a phase difference immediately before an input terminal of a phase difference detection circuit. A phase difference detection circuit for detecting a phase difference between a clock signal output from the delay correction circuit and a reference clock at an output terminal of the second input buffer; and an output result of the phase difference detection circuit A control signal for adjusting a delay time of a clock signal input from the clock input terminal via the first input buffer based on A variable delay circuit that varies a delay time of a clock signal input from the clock input terminal via the first input buffer in response to the control signal, and outputs the clock signal to the clock distribution system. A semiconductor integrated circuit device characterized by the above-mentioned.