JP2928059B2 - Interlace display control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlace display control circuit, and more particularly to a method for driving an interlace display in a liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal display device, when performing interlaced display with a good resolution, there is a method of doubling a video signal using a double speed conversion circuit. In addition to this method, a vertical driver for even-numbered lines and a vertical driver for odd-numbered lines are provided on both left and right sides of the liquid crystal display panel, or a double-speed conversion circuit is provided by using four sets of sample and hold circuits of horizontal drivers. There is a method that makes it unnecessary.

In the case of a method of doubling a video signal using a double-speed conversion circuit, as shown in FIG. 6, the video signal is doubled using a double-speed conversion circuit 8 and the liquid crystal is controlled by horizontal drivers 2 and 3 and a vertical driver 4. Write two lines to the display panel 1 at a time.

At this time, the control of the horizontal drivers 2 and 3 and the vertical driver 4 by the control circuit 7 makes the combination of the two lines different for each field. The control circuit 7 controls the driving of the horizontal drivers 2 and 3 by the clock HCK and the LP pulse, and controls the driving of the vertical driver 4 by the start pulse VSP and the shift clock VCK. The above-mentioned method is described in detail in JP-A-62-284592.

In the case of providing a vertical driver for even lines and a vertical driver for odd lines on both left and right sides of the liquid crystal display panel, as shown in FIG. On the left side, the row electrodes of the even-numbered lines are drawn out on the right side, and the vertical drivers 4 and 10 are connected to the respective row electrodes.

The control circuit 11 has a start pulse VSP
(L) and the shift clock VCK (L) to drive and control the vertical driver 4, and the start pulse VSP (R) and the shift clock VCK (R) to control the vertical driver 1.
By driving and controlling 0, only odd lines or even lines are driven for each field. The above method is described in detail in Japanese Patent Application Laid-Open No. 3-132274.

Further, a method for eliminating the need for a double speed conversion circuit by using four sets of sample and hold circuits of a horizontal driver is described in detail in Japanese Patent Application Laid-Open No. 63-231395.

[0008]

In the above-described conventional interlace display control circuit, in order to perform interlace display at a good resolution, double speed conversion by a line memory or the like, the complexity of a horizontal driver, or the liquid crystal display panel is required. It is necessary to change the method of extracting the row electrodes and install a dedicated vertical driver. Therefore, there is a problem that the cost is increased as compared with the normal line sequential driving for performing the interlaced display.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an interlace display control circuit which can solve the above-mentioned problems and can perform an interlace display with a good resolution without increasing the cost.

[0010]

Means for Solving the Problems The liquid crystal display panel of the present invention
The interlace display control circuit controls a vertical driver connected to a row electrode of the liquid crystal display panel and a horizontal driver connected to a column electrode of the liquid crystal panel, and displays a first signal indicating data of an even line of an image signal. An interlace display control circuit for sequentially displaying an image of a field and an image of a second field indicating data of an odd line of the image signal on the liquid crystal panel, wherein the vertical driver is a
N times the frequency of the signal (n is an integer of 2 or more)
Control means for sequentially driving each line by a clock signal, and a start pulse given to the vertical driver by n
And second control means for giving a shift by / 2 lines ,
The first control means and the second control means
Each line of the first field and the second field
The image signal is displayed for each of n lines, and is displayed on the liquid crystal panel.
The image of the first field displayed on the
Field display display lines are n / 2 lines from each other
Display alternately by shifting.

[0011]

The vertical driver reads the start pulse VSP with the shift clock VCK and outputs a voltage to the row electrodes of the liquid crystal display panel. As a result, the voltage applied to the column electrodes is written into the liquid crystal display panel, and an image is displayed.

The output of the horizontal driver maintains the output voltage to the liquid crystal display panel during one horizontal period. When a clock n times the horizontal synchronization frequency is given to the vertical driver as the shift clock VCK during this one horizontal period, the vertical driver scans n lines during one horizontal period, and sends the video signal of the same line to the liquid crystal display panel for n times. Operates to write the number of lines.

Further, the position at which the vertical driver reads the start pulse VSP when displaying the second field is n / 2 smaller than the position at which the vertical driver reads the start pulse VSP when displaying the first field.
Make the clock faster. As a result, the line between the first field and the line of the second field is shifted by n / 2 lines.

For example, when n = 4, the first field is (1, 2, 3, 4), (5, 6, 7, 8), (9, 1)
0, 11, 12), ... On the other hand, the second field is (3, 4, 5, 6), (7, 8, 9, 10),
(11, 12, 13, 14),... Thus, the average between adjacent lines in each field is displayed on the liquid crystal display panel, and an interlaced signal can be displayed.

[0015]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, horizontal drivers 2 and 3 are connected to column electrodes of an active matrix type liquid crystal display panel (hereinafter referred to as a liquid crystal display panel) 1, and a vertical driver 4 is connected to row electrodes.

The control circuit 5 receives a horizontal synchronizing signal, a vertical synchronizing signal, and a video signal, respectively, controls driving of the horizontal drivers 2 and 3 by the clock HCK and the LP pulse, and controls the vertical driver by the start pulse VSP and the shift clock VCK. 4 is driven and controlled.

FIG. 2 is a time chart showing the operation of one embodiment of the present invention. FIG. 2A is a time chart showing the driving operation of the vertical driver 4, and FIG. 2B is a time chart showing the operation for each field. These figures 1
The operation of the embodiment of the present invention will be described with reference to FIG.

The video signal input to the control circuit 5 is sampled by the horizontal drivers 2 and 3 at the timing of the clock HCK. The horizontal drivers 2 and 3 simultaneously output the sampled video signals to all the column electrodes every one horizontal period by using the LP pulse synchronized with the horizontal synchronization signal.

The control circuit 5 supplies the vertical driver 4 with a shift clock VCK having a frequency twice as high as that of the horizontal synchronizing signal. The shift clock VCK drives the vertical driver 4 continuously for two lines during one horizontal period. [Figure 2
(A)].

When the display of the first field is completed, 240 480 video signals of the first field (video signals of the even-numbered lines in the video to be displayed) are provided on the vertical 480 lines of the liquid crystal display panel 1 by two lines for each line. Written.

The control circuit 5 supplies a start pulse V to the vertical driver 4 when displaying a video signal of the second field (a video signal of an odd line of the video to be displayed).
The timing of the SP is given one shift clock earlier than when displaying the first field [FIG.
(B)].

Thus, in the first field, the combinations of lines on the liquid crystal display panel 1 where the same data is written are (1, 2), (3, 4), (5, 6),.
9,480).

On the other hand, in the second field, the combination of lines on the liquid crystal display panel 1 on which the same data is written is (2, 2).
3), (4, 5), (6, 7), ..., (478, 47)
9).

Therefore, the first field and the second field are displayed with a shift of one line. That is, the video signal of the even-numbered line and the video signal of the odd-numbered line of the video to be displayed are displayed with a shift of one line.

FIG. 3 is a diagram showing a display operation on the liquid crystal display panel 1 according to one embodiment of the present invention. Using this figure,
A display operation according to one embodiment of the present invention will be described.

If the video signal to be displayed is composed of the data a1 to a240 of the even lines and the data b1 to b240 of the odd lines, the control circuit 5 sends the data a1 to the even line.
1 to a240 are input as a first field, and data b1 to b240 of an odd line are input as a second field.

The control circuit 5 supplies the vertical driver 4 with a shift clock VCK having a frequency twice as high as the horizontal synchronizing signal, and controls the vertical driver 4 for two lines continuously during one horizontal period to thereby control the first field. The data a1 to a240 are displayed on the liquid crystal display panel 1 for each two lines.

Thereafter, the control circuit 5 supplies the vertical driver 4 with a shift clock VCK having a frequency twice as high as the horizontal synchronizing signal, and also supplies the vertical driver 4 with a start pulse VCK.
SP is given one clock earlier than in the first field. Thereby, the data b1 to b in the second field
240 is 1 for data a1 to a240 of the first field.
The image is displayed on the liquid crystal display panel 1 two lines at a time, shifted by lines.

Therefore, as the display of each line of the liquid crystal display panel 1, the average between adjacent lines of the video signal to be displayed is observed. That is, (a1 + b0) / 2 is set on the first line of the liquid crystal display panel 1 and (a1 + b0) / 2 is set on the second line.
1 + b1) / 2 is written on the third line as (a2 + b1) / 2.
On the fourth line, (a2 + b2) / 2 on the fifth line, (a3 + b2) / 2 on the fifth line,.
0 + b239) / 2 on the 480th line (a240 + b24).
0) / 2.

As a result, 480 vertical interlaced signals can be displayed on the liquid crystal display panel 1 although they are pseudo.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, in another embodiment of the present invention, the liquid crystal display panel 6 has the same configuration as that of the embodiment of the present invention except that the liquid crystal display panel 6 has 960 vertical lines. is there. The operation of the same component is the same as the operation of the embodiment of the present invention.

FIG. 5 is a time chart showing the operation of another embodiment of the present invention. FIG. 5A is a time chart showing the driving operation of the vertical driver 4, and FIG. 5B is a time chart showing the operation for each field. The operation of another embodiment of the present invention will be described with reference to FIGS.

In this case, the liquid crystal display panel 6 is vertically 960
Since the line is a line, the control circuit 5 supplies the vertical driver 4 with the shift clock VCK having a frequency four times the frequency of the horizontal synchronizing signal.
Is continuously driven for four lines during one horizontal period [FIG.
reference].

When the display of the first field is completed, 240 video signals of the first field (the video signals of the even-numbered lines of the video to be displayed) are provided on the vertical 960 lines of the liquid crystal display panel 6 by 4 lines each. Written.

The control circuit 5 supplies a start pulse V to the vertical driver 4 when displaying a video signal of the second field (a video signal of an odd-numbered line of the video to be displayed).
The timing of SP is given by two shift clocks earlier than when displaying the first field [FIG.
(B)].

Thus, in the first field, the combination of lines on the liquid crystal display panel 1 where the same data is written is (1, 2, 3, 4), (5, 6, 7, 8),. 9
57, 958, 959, 960).

On the other hand, in the second field, the combination of lines on the liquid crystal display panel 1 where the same data is written is (3, 3).
4, 5, 6), (7, 8, 9, 10), (11, 12,
13, 14), ..., (955, 957, 957, 95)
8).

Therefore, the first field and the second field are displayed with a shift of two lines. That is, the video signal of the even-numbered line and the video signal of the odd-numbered line of the video to be displayed are displayed with a shift of two lines.

As described above, the shift clot VCK supplied from the control circuit 5 to the vertical driver 4 is set to n times the frequency of the horizontal synchronizing signal, and the start pulse VSP supplied from the control circuit 5 to the vertical driver 4 is supplied for each field. By alternately shifting n / 2 lines at a time, interlaced display can be performed on the liquid crystal display panel with simple control. Therefore, it is possible to perform the interlaced display with a good resolution without increasing the cost.

[0041]

As described above, according to the present invention, the shift clot supplied to the vertical driver is made n times the frequency of the horizontal synchronizing signal, and the start pulse supplied to the vertical driver is n / f for each field. By alternately shifting two lines at a time, there is an effect that interlaced display can be performed with good resolution without increasing the cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2A is a time chart illustrating a driving operation of a vertical driver according to an embodiment of the present invention, and FIG. 2B is a time chart illustrating an operation for each field according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a display operation on a liquid crystal display panel according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of another embodiment of the present invention.

5A is a time chart showing a driving operation of a vertical driver according to another embodiment of the present invention, and FIG. 5B is a time chart showing an operation for each field according to another embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional example.

FIG. 7 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1,6 liquid crystal display panel 2,3 horizontal driver 4 vertical driver 5 control circuit

Claims (2)

(57) [Claims] A first driver for controlling a vertical driver connected to a row electrode of the liquid crystal display panel and a horizontal driver connected to a column electrode of the liquid crystal display panel; An interlace display control circuit for sequentially displaying an image of a second field indicating data of an odd line of the image signal on the liquid crystal panel, wherein the vertical driver is n times the frequency of a horizontal synchronization signal.
(N is an integer of 2 or more) with a shift clock of frequency
A first control means for sequentially driving each line, the vertical
Start pulse given to driver is shifted by n / 2 lines
And a second control means for providing to said first control hand
The first field by means of a stage and the second control means
And the image signal of each line of the second field is n
Display line by line and display on the liquid crystal panel
The image of the first field and the image of the second field are displayed.
Display start lines are alternately shifted by n / 2 lines from each other.
Interlace display control circuit of the liquid crystal display panel, characterized in that Shimesuru. 2. The first control means synchronizes with a horizontal synchronizing signal, which is a timing of taking the signal into the horizontal driver, and multiplies the frequency by n (n is an integer of 2 or more).
Driven line by line by shift clock of different frequency
To constitute a means for driving the vertical driver, the second control means, to the driving timing of the vertical driver in the first field and the second field respectively consisted means for shifting n / 2 lines 2. An interlace display control circuit for a liquid crystal display panel according to claim 1, wherein: