JP2928537B2 - RAM scan method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a maintenance data update and reference function for a RAM provided in a data processing device.

[Conventional technology]

Conventionally, for a register in a data processing device, a different scan address is assigned to each bit of all registers, and by sequentially specifying this address, a fixed procedure is performed regardless of the function, structure, and size of the register. Scan in / out operation could be performed. Incidentally, Japanese Patent Application Laid-Open No. 55-32158 is mentioned as this kind of technology.

[Problems to be solved by the invention]

Regarding the RAM in the data processing device, if a scan address is given to all bits of the RAM data as in the case of the above register, it becomes enormous, and the RAM is structurally a RAM.
Since it is necessary to write / read one word of data after specifying the word address in advance, the RAM
If the data bits are to be specified uniformly using only the scan address, a considerable amount of hardware dedicated to the scan operation needs to be added around each RAM in order to incorporate this into the RAM access framework.

Conventionally, the firmware that activates the RAM scan operation is aware of the RAM access procedure, scans in / outs the RAM word address register and data register, and writes / reads data from the data register to RAM. The RAM scan operation was performed by combining the operations.

However, in the above method, since the firmware side is aware of the access procedure for each RAM, the RAM scan operation procedure depends on the hardware structure around each RAM and becomes complicated, resulting in a drastic reduction in scan operation speed. There was a problem of doing.

An object of the present invention is to solve such a problem.

[Means for solving the problem]

In the present invention, generalization and simplification of the firmware procedure are achieved by absorbing the above-described access procedure for each RAM into the hardware of the scan control unit provided commonly to all the RAMs in the data processing device. As a result, the speed of the RAM scan operation is increased.

[Action]

According to the method of the present invention, if the information for selecting the RAM to be accessed, the head word address of the RAM and the data length of one word of the RAM are set in the scan control unit in advance, the RAM word address can be stored in the RAM unit. Settings, updates, RAM
Processing that depends on the structure of each RAM, such as generation and updating of addresses in words, is automatically performed by the hardware of the scan control unit.
The scan-in / out operation of the RAM data is performed by a general and simple procedure of writing / reading data.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
The figure shows the configuration of the hardware necessary to implement the present invention. The control hardware 1 to 11 are provided in the scan control unit and are used for performing a scan in / out operation on the RAM 15. Although only one RAM to be scanned is shown in the figure, a scan operation can be performed on a plurality of RAMs by the same control hardware.

The RAM selection address 1 of the scan control unit specifies the RAM to be scanned, and the scan address 12 is generated by adding the bit address 2 to the lower order. The scan address is given to each bit in one word of the data of the RAM 15 to be scanned and also to each bit of the address register 16 of the RAM. The relationship between the two is as shown in FIG. The selected address is the same for each RAM, and a fixed-length address register for all RAMs is assigned to the lower bits of the bit address, and each bit of RAM data having a different length for each RAM is assigned to the higher addresses. The bit address 2 is sequentially incremented by the update circuit 3 during the RAM scan operation, and the bit address 2
The M data is compared with the word length of the data, that is, the bit address 5 of the word end bit.
Is initialized, that is, cleared to zero. RA
The word address 7 of M is updated by the update circuit 8 when the comparison circuit 4 detects a match, and when the bit address 2 indicates each bit of the RAM address register 16, the address is controlled by the selector 9. • Scanned into register 16.

After setting the RAM selection address 1, the word end bit address 5 and the word address 7 as a procedure by the firmware, the bit address 2 is cleared to zero and the RAM scan operation is started. The operation of the hardware after startup is shown below. Bit address 2 is first RA
To indicate the M address register 16, each bit of the word address 7 is sequentially scanned into the address register 16 as it is incremented by the update circuit 3. Next, when bit address 2 indicates a RAM data bit, register 10
Scan data in to or register 1 from RAM15
Data scan out to 1 is performed. When bit address 2 is sequentially updated to indicate the data bit at the end of the word, comparison circuit 4 detects a match, updates word address 7 and clears bit address 2 to zero, and updates the updated word. The above operation is repeated from the scan-in of the address register 16 at the address 7 and the scan operation for the next data word of the RAM 15 is continuously performed. The above setting and updating of the RAM address register 16 and detection of the end of the RAM word
Since the RAM scan operation is automatically performed by the hardware, after the RAM scan operation is started, the data set to register 10 is set for scan-in and the data set to register 11 is read for scan-out when necessary. The RAM scan operation can be realized by a general and simple procedure that does not depend on the structure of the RAM.

〔The invention's effect〕

According to the method of the present invention, the firmware that activates the RAM scan operation does not need to add hardware dedicated to the RAM scan around each RAM and the firmware that activates the RAM scan operation is generally used for all the RAMs without being aware of the structure of each RAM. The data can be scanned in / out by a simple procedure. RAM has been simplified by simplifying the firmware procedure.
The speed of the scanning operation can be increased.

[Brief description of the drawings]

FIG. 1 is a hardware configuration diagram for realizing one embodiment of the present invention, and FIG. 2 shows an address map of a scan address assigned to each bit of RAM data and an address register in the embodiment. FIG. 1 ... address register, 2 ... bit address
Register, 3... Bit address update circuit, 4... Comparison circuit.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 12/16 G06F 11/22

Claims (1)

(57) [Claims] A plurality of RAMs for realizing various functions of a data processing device, and a data scan-in / read-out operation for the RAMs.
In a data processing apparatus having a scan control unit for controlling an out operation, a word address register for setting a head word address of the RAM and a first update circuit for updating the contents thereof are provided in the scan control unit; RAM 1
A word end bit address register for setting the data length of a word, a bit address register for holding an in-word address of the RAM data, a second updating circuit for updating the contents thereof, and an initializing circuit for initializing the contents A comparison circuit for comparing the contents of the word end bit address register with the contents of the bit address register; a scan-in data register for setting scan-in data; A selector for selecting an output of an address register and an output of the scan-in data register;
The address register is sequentially incremented by the second update circuit during a scan operation and initialized when the comparison circuit detects a match with the word end bit address, and the word address register is The content of the word address register is incremented by the first update circuit when the comparison circuit detects a match, and the output of the selector is switched by the output of the bit address register. A RAM scan method for controlling whether to scan in a register or scan in the contents of the scan-in data register into the RAM.