JP2931395B2 - Method for manufacturing thin film transistor array - Google Patents

Description

The present invention relates to a method for manufacturing a thin film transistor array suitable for a liquid crystal display device.

(B) Conventional technology In recent years, an active matrix display device has been developed in which a thin film transistor (hereinafter referred to as a TFT) that operates as a switching transistor is coupled to each of a large number of display electrodes of a pixel arranged in a matrix and the TFT is used as a drive circuit. Have been. Since this display device can obtain a very clear display, it has attracted attention as a thin display device replacing the CRT.

FIG. 9A is a plan view of a TFT array in a conventional active matrix display device in pixel units, and FIG. 9B is a cross-sectional view of the TFT position along the line AA '. T
The FT array includes a transparent insulating substrate 1, a gate wiring 20 having a gate electrode 2, a first insulating film (gate insulating film) 3, a semiconductor film 4, a second insulating film (passivation insulating film) 5, a source electrode 6, and a drain. It comprises a drain electrode 70 having an electrode 7 and a display electrode 8. When manufacturing this TFT,
At least five photomask steps are required to form the gate electrode 2, the island of the second insulating film 5, the island of the semiconductor film 4, the display electrode 8, and the source and drain electrodes 6 and 7. .

(C) Problems to be Solved by the Invention As described above, the biggest cause of the decrease in the throughput in the manufacture of the TFT array is the long manufacturing process. Particularly, from the viewpoint of reduction of manufacturing cost, improvement of throughput is strongly desired. A TFT array is manufactured by repeating three steps of film formation, photolithography, and etching.
It is the photolithography process using a mask aligner that requires high-precision alignment that determines the throughput during array fabrication.

Therefore, by reducing the number of photomasks used in the TFT array manufacturing process, the throughput can be improved and the manufacturing cost can be reduced. It is not an exaggeration to say that, for example, with the current apparatus capability, if four TFTs are manufactured using five photomasks, for example, the throughput will be 5/4 times as large.

(D) Means for solving the problem A gate wiring forming step of forming an opaque gate wiring having a gate electrode region and a thinned region having a locally reduced wiring width on a transparent insulating substrate, Forming a first insulating film on at least the gate wiring, forming a semiconductor film on the first insulating film, forming a second insulating film on the semiconductor film; Forming a first resist pattern on the second insulating film by using the gate wiring as a mask by a first exposure process from the back surface of the substrate; Forming the islanded second insulating film at a position of the gate wiring other than the thinned region by etching and removing the second insulating film on the thinned region using the first resist pattern as a mask; Back of A second exposure process having a smaller exposure energy than that of the first exposure process is performed from the surface, and a second exposure process is performed on the second insulating film using the gate wiring as a mask and on the semiconductor film exposed from around the second insulating film. A second resist pattern forming step of forming a resist pattern, a first semiconductor film forming a semiconductor film having a width larger than the width of the second insulating film in at least a gate electrode region using the second resist pattern as a mask A forming step, an electrode forming step of forming a drain electrode and a source electrode on the semiconductor film, and etching and removing the semiconductor film on the thinned region so that the second insulating film has at most the same width and at most the same shape. The method comprises a second semiconductor film forming step of forming an islanded semiconductor film.

(E) Function According to the present invention, the number of photomasks used in the TFT array manufacturing process can be reduced, the throughput can be improved, and the manufacturing cost can be reduced. In addition, since the second insulating film and the semiconductor film are finely processed by the self-alignment method, both patterns can be patterned into a fixed shape with high precision alignment, which contributes to stabilization of TFT characteristics.

(F) Example <Example 1> FIG. 1 is a plan view of a pixel unit of a TFT array of an active matrix liquid crystal display device obtained by a first example of the manufacturing method of the present invention. AA 'line of FIG. 1 (TFT
2 (i) to 2 (vii) are cross-sectional views of each manufacturing process along the region (region), and cross-sectional views of each manufacturing process along the line BB '(normal region of gate wiring) in FIG. FIGS. 3 (i) to 3 (vii) are cross-sectional views of each manufacturing step taken along the line CC ′ (thinned region of the gate wiring) in FIG. 1 and FIGS. 4 (i) to 4 (vii). And will be described accordingly.

First step [FIG. 2 (i), FIG. 3 (i), FIG. 4 (i)] On a transparent insulating substrate made of glass or the like, Mo, Cr, W, Ti, Ta,
Gate wiring locally provided with a gate electrode 2 made of Al or the like
20 is formed, and a first insulating film 3 (gate insulating film), a semiconductor film 4, and a second insulating film 5 (passivation insulating film) are continuously deposited by P-CVD.

Step 2 [FIG. 2 (ii), FIG. 3 (ii), FIG.
i)] A positive resist is applied, and a resist 30 serving as a mask for etching the second insulating film is formed on the gate electrode 2 and the gate wiring 20 by exposure from the back surface of the substrate. However, since light diffraction occurs at the pattern edges of the gate electrode 2 and the gate wiring 20, the resist 30 is formed in a smaller pattern than the gate electrode 2 and the gate wiring 20. Therefore, when the exposure energy (the product of the illuminance and the exposure time) is increased, the pattern size of the resist 30 is reduced. Therefore, by making the exposure energy very large, C-C '
It is also possible not to form the resist only in the thinned area on the line.

Step 3 [FIG. 2 (iii), FIG. 3 (iii), FIG.
i)] The second insulating film 5 is etched. In this step, the amount of etching is controlled to generate a side etch larger than the size of the resist formed in the line CC 'in FIG. 1, and the second insulating film 5 is etched only in the line CC' in FIG. Remove. That is, by this step, the second insulating film 5 is islanded on the gate wiring 20.

Step 4 [FIG. 2 (iv), FIG. 3 (iv), FIG.
v)] An impurity semiconductor film 4 'is deposited by P-CVD, a positive resist is applied, and the semiconductor film 4 and the impurity semiconductor film 4' are etched on the gate electrode 2 and the gate wiring 20 by exposure from the back surface of the substrate. A resist 30 serving as a mask is formed. Since light diffraction occurs at the pattern edge between the gate electrode 2 and the gate wiring 20, the resist 30 is formed in a smaller pattern than the gate electrode 2 and the gate wiring 20. Therefore, when the exposure energy is increased, the pattern size of the resist 30 is reduced. Therefore, it is possible to prevent the resist from being formed only in the thinned area on the line CC 'by increasing the exposure energy very much.

In this step, the resist 30 is formed by minimizing the exposure energy, and a resist pattern having a width larger than the width of the second insulating film is formed. In the step of performing the exposure process from the back surface of the substrate, the resist 30 is exposed with light that has passed through the semiconductor film 4 and the impurity semiconductor film 4 '. Therefore, the semiconductor film 4 and the impurity semiconductor film 4' It takes a long time to complete the exposure due to absorption. Therefore, reducing the exposure energy in this step is advantageous in terms of throughput.

Fifth step [FIGS. 2 (v), 3 (v), 4 (v)] The semiconductor film 4 and the impurity semiconductor film 4 'are etched.
In this step, the amount of side etching is reduced, and the semiconductor film 4 and the impurity semiconductor film 4 ′ protruding from the second insulating film 5 in the channel portion, the source electrode 6 and the drain electrode 7 are formed.
In order to increase the area of contact with
The semiconductor film 4 is formed in the C'-line region (a thin region of the gate wiring).
And the impurity semiconductor film 4 'remains. In this step, the semiconductor film 4 and the impurity semiconductor film 4 'have substantially the same shape as the gate wiring.
Is patterned.

Step 6 [FIG. 2 (vi), FIG. 3 (Iv), FIG. 4 (v
i)) The display electrode 8 is formed.

Step 7 [FIG. 2 (vii), FIG. 3 (vii), FIG.
i)] A drain wire 70 locally including a drain electrode 7 made of Mo, Cr, W, Ti, Ta, Al, or the like, and a source electrode 6 are formed, and are covered with a second insulating film 5 on the gate wire 20. The remaining portions of the semiconductor film 4 and the impurity semiconductor film 4 'are removed by etching. At this time, in the channel portion, only the impurity semiconductor film 4 'on the second insulating film 5 is simultaneously etched and removed.

As described above, the number of photomasks used in each of the islanding of the second insulating film 5 and the islanding of the semiconductor film 4 can be reduced by devising the gate wiring pattern (making it thinner locally) and performing exposure processing from the back surface of the substrate. Can be reduced. In other words, the semiconductor film 4 and the impurity semiconductor film 4 'are not made into islands only by the exposure process from the back surface of the substrate, and the semiconductor film 4 and the impurity semiconductor film 4 are made to have substantially the same shape as the gate wiring region by the exposure process from the back surface of the substrate. After patterning, the islanding of the semiconductor film 4 and the impurity semiconductor film 4 'on the gate wiring and the etching removal of the impurity semiconductor film 4' in the channel portion are simultaneously performed in the final step. By doing so, there is an advantage that the contact area of the channel portion can be increased, the exposure time from the back surface of the substrate after the deposition of the impurity semiconductor film 4 'can be reduced, and as a result, the throughput can be increased.

Also, with the current resist material and exposure equipment, by increasing the exposure energy from the back of the substrate,
A resist pattern having a size smaller by about 6 μm than that of the gate wiring 20 can be formed (however, if the exposure energy is further increased, a resist pattern having a smaller size can be formed, but the throughput is reduced and it is not practical). Furthermore, a pattern smaller by about 2 μm than the resist size can be formed by controlling the etching amount (however, if the etching amount is further increased, a smaller pattern can be formed, but control is difficult and not practical). Therefore, the pattern dimension of the thinned region in the gate wiring is preferably 8 μm or less.

<Example 2> A gate wiring shape enabling the manufacturing process of Example 1 will be described with reference to a specific example.

1) A recessed region is provided in the gate wiring to locally reduce the wiring width [FIG. 5 (a)].

2) A hollow region is provided in the gate wiring to locally reduce the wiring width [FIG. 5 (b)].

3) A mesh region is provided in the gate wiring to locally reduce the wiring width (FIG. 5C).

As described above, the line width of the gate wiring to be formed only needs to be locally reduced, and the line width of that region is equal to that of the first embodiment.
However, as described above, it is preferably 8 μm or less. However, in the shapes 1) to 3), there is a problem that the gate wiring resistance is increased due to the local thinning.

Therefore, the following contents are effective in preventing the increase of the gate wiring resistance.

4) dividing the gate line into at least two or more thin lines;
The outermost pattern of the divided region is expanded more than the peripheral portion, and the total line width obtained by adding the divided fine lines is equal to the line width of the peripheral portion (FIG. 6A).

5) The mesh region of the gate wiring is expanded more than the peripheral portion [FIG. 6 (b)].

6) The gate wiring is composed of the opaque conductive film 10 and the transparent conductive film 11, and only the opaque conductive film 10 is locally thinned. The transparent conductive film 11 may be in either the upper layer or the lower layer of the opaque conductive film 10. Since the transparent conductive film 11 transmits light, it does not affect the resist pattern in the exposure process from the back surface of the substrate. The transparent conductive film 11 lowers the wiring resistance and repairs the disconnection of the opaque conductive film 10 (FIG. 7A).

7) The transparent conductive film 11 is disposed only in a region where the gate wiring formed of the opaque conductive film 10 is locally thinned (FIG. 7B).

8) The gate wiring is composed of a line formed of the opaque conductive film 10 and a line formed of the transparent conductive film 11, and a line formed of the opaque conductive film 10 and a line formed of the transparent conductive film 11 in a thinned region where the opaque conductive film 11 is locally thinned. Overlap.
However, the region where the transparent conductive film 11 and the opaque conductive film 10 overlap may be outside the thinned region where the opaque conductive film 10 is locally thinned. The line formed by the transparent conductive film 11 has a role of lowering the wiring resistance and repairing the disconnection of the opaque conductive film 11, but also has a role of overlapping the TFT display electrode of the adjacent gate wiring with the opening. The auxiliary capacitance can be formed without lowering the efficiency [FIG. 7 (c)].

With the above-described method, it is possible to prevent a reduction in wiring resistance due to the local thinning of the gate wiring. 4)
The methods of 5) and 5) can most effectively prevent the reduction of the gate wiring resistance, but may increase the opaque electrode area and may cause a decrease in the aperture ratio of the TFT. On the other hand, the problems 6) to 8) do not cause a problem of a decrease in the aperture ratio, but the specific resistance of the transparent conductive film is generally large, and the wiring resistance is higher than 4) and 5). The transparent conductive film 11 is formed not only when the opaque opaque conductive film 10 is disposed on the locally thinned electrode as in the thinned region in the present invention, but also between the islanded electrodes. It is also effective if you do.

As described above, various contents can be considered for the pattern of the gate wiring that enables the first embodiment. In short, the region where the second insulating film or the semiconductor film is removed by etching has a small gate line width. In the region where the insulating film or the semiconductor film remains, the gate line width may be increased. Further, it is realistic that the line width of the region where the gate wiring is thinned is 8 μm or less, and the smaller the line width, the larger the margin in the manufacturing process, but it is necessary to consider wiring resistance.

In addition, by arranging such various gate wiring patterns on a TFT array in which a matrix is arranged in a predetermined pixel cycle, TFT addresses can be easily identified from the gate wiring patterns. For example, four different patterns having different shapes as shown in FIGS. 8 (a) to (d) may be arranged, or the patterns of FIGS. 5 (a) to (c) may be added. Good. When the gate wiring is formed by arranging patterns of various shapes as described above, it is necessary to consider wiring patterns having the same resistance value so that the wiring resistance does not become non-uniform.

(G) Effects of the Invention According to the present invention, the number of photomasks used in the TFT array manufacturing process can be reduced, the throughput can be improved, and the manufacturing cost can be reduced. In addition, since the second insulating film and the semiconductor film are finely processed by the self-alignment method, both patterns can be patterned into a fixed shape with high precision alignment, which contributes to stabilization of TFT characteristics.

[Brief description of the drawings]

FIG. 1 is a plan view of a pixel unit of a TFT array showing an embodiment of the present invention, FIG. 2 is a sectional view of each manufacturing process along the line AA 'in FIG. 1, and FIG. 4 is a cross-sectional view of each manufacturing process along the line BB ', FIG. 4 is a cross-sectional view of each manufacturing process along the line CC' in FIG. 1, and FIG. 5 is another embodiment of the present invention. FIG. 6 is a plan view of a thinned region of a gate wiring showing another embodiment of the present invention, and FIG. 6 is another plan view of a thinned region of a gate wiring showing another embodiment of the present invention. FIG. 9 (a) is a plan view of a pixel unit of a conventional TFT array, and FIG. 9 (b) is a plan view of a pixel unit of a conventional TFT array. Sectional view. 1 transparent insulating substrate 2 gate electrode 3 first
Insulating film, 4 ... semiconductor film, 4 '... impurity semiconductor film, 5
... second insulating film, 6 ... source electrode, 7 ... drain electrode, 8 ... display electrode, 10 ... opaque conductive film, 11 ... transparent conductive film, 20 ... gate wiring, 70 ... drain wiring .

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G02F 1/136 500

Claims (1)

(57) [Claims] 1. A gate wiring forming step of forming an opaque gate wiring having a gate electrode region and a thinned region having a locally reduced wiring width on a transparent insulating substrate, at least on the gate wiring Forming a first insulating film on the first insulating film; forming a semiconductor film on the first insulating film; forming a second insulating film on the semiconductor film; A first resist pattern forming step of forming a first resist pattern on a second insulating film by using the gate wiring as a mask by a first exposure process from the back surface of the substrate; Forming an islanded second insulating film at a gate wiring position other than the thinned region by etching and removing the second insulating film on the thinned region using the mask as a mask. 1 dew Performing a second exposure process with a smaller exposure energy than during the process, and forming a second resist pattern on the second insulating film and on the semiconductor film exposed from around the second insulating film using the gate wiring as a mask; A first semiconductor film forming step of forming a semiconductor film having a width larger than the width of the second insulating film in at least a gate electrode region using the second resist pattern as a mask; An electrode forming step of forming a drain electrode and a source electrode; and removing the semiconductor film on the thinned region by etching to form a semiconductor film that has been formed into an island having at most the same width and at most the same shape as the second insulating film. A method for manufacturing a thin film transistor array, comprising a step of forming a second semiconductor film.