JP2932294B2 - Pulse generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator, and more specifically, to attributes of pulses such as phase (time axis), pulse width, and polarity (binary state). Is suitable for generating a pair of pulses having a fixed correlation, and particularly relates to a method suitable for generating a gate pulse of a pair of switching elements related to a power conversion device such as an inverter.

[Conventional technology]

The control of the power converter etc. is performed by a computer (hereinafter, CPU
Digital control using (abbreviated as) is widely applied. In such digital control, a pattern of a gate pulse for performing ignition control of a power conversion circuit switching element is obtained by digital arithmetic processing, and this pattern data is transferred to a pulse generation device formed using hardware or a microprocessor. There is known a device in which an actual gate pulse is generated by the pulse generation device and output to each switching element (Japanese Patent Laid-Open No. 59-1137).
No. 92, JP-A-61-116994, etc.).

[Problems to be solved by the invention]

By the way, in order to generate one pulse, each time data of the rising and falling points of the pulse and at least four data specifying the binary state of the signal at each time are required. Therefore, the CPU must transfer at least four data per pulse to a register or the like of the pulse generator. For example, in the case of a three-phase inverter having a bridge configuration for driving and controlling an electric motor, three phases of U, W, and W ×
Since each gate pulse of the six-arm switching element must be generated, at least 24 data in total are generated and transferred.

The upper and lower arms of the bridge configuration are turned on and off complementarily, but in order to avoid a short circuit between the upper and lower arms, a period called dead time is provided in which a pair of gate pulses corresponding to the upper and lower arms are both turned off. .

However, the prior art has a problem in that the load on the transfer of the CPU is large because reduction in the number of data transfers for pulse generation is not considered. In particular, if the frequency of the carrier wave is increased in the pulse width modulation (PWM) control, the transfer load increases.

Similarly, even in the dead time calculation process, there is a problem that the load on the CPU increases in consideration of the increase in the frequency.

An object of the present invention is to reduce the number of generated data required to generate a pair of pulses whose pulse attributes have a fixed correlation, and to reduce the time relationship (for example, dead time) between the rising or falling points of the pulses. An object of the present invention is to provide a pulse generation device capable of reducing the load on a host CPU by performing arithmetic processing for control.

[Means for solving the problem]

In order to achieve the above object, a pulse generation device according to the present invention includes: a reference time data register storing reference time data defining a time axis of a pair of pulses to be generated; and a time of each pulse with respect to the reference time data. First and second processing time data registers each storing processing time data indicating the relationship between the first and second processing time data registers, and state data specifying the binary state of one of the pair of pulses. 2 pulse output register, a control register storing a control signal, a counter for counting clock pulses, and taking in the reference time data and the processing time data to obtain rising and falling time data of each pulse. And the respective times of the respective pulses obtained by the arithmetic unit. A transfer control unit for controlling transfer timing of data, first and second time data registers in which time data of the respective pulses output from the transfer control unit are respectively stored, and a time of the time data registers. Comparing the data with the value of the counter and outputting first and second comparators when they match, the arithmetic unit includes an arithmetic control signal stored in the control register. The transfer control unit controls a transfer timing of each time data according to a transfer control signal stored in the control register, and the first pulse output register stores the stored data. And an output terminal that is reset to a binary state obtained by inverting the state data to be output. The pulse output register has an output terminal that is reset to a binary state of the stored state data, and the first and second pulse output registers receive one coincidence signal from the corresponding comparator. When the next match signal is input, the binary state of the output terminal is inverted.
The value state is reset, and the counter is reset by a reset signal stored in the control register at regular intervals. The reference time data, the respective processing time data, the state data, and the control signal Is input from the outside in accordance with the transfer cycle of the count-up / reset signal of the counter.

If the processing time data of one pulse is matched with the reference time data, the reference time data register or the first processing time data register can be omitted, and the number of transfer data can be reduced by one.

Further, it is preferable that each of the pulse output registers has an inverted output terminal which is held in an inverted state of the output terminal. In this case, an output switch for selectively selecting the output terminal and the inverted output terminal of each pulse output register is provided, and each switch is controlled by an output switch control signal stored in the control register. The versatility of the polarity of the generated pulse can be provided.

The counter can be applied to a normal free-run counter or an up-down counter. in this case,
The operation processing content of the operation unit and the control signal are determined according to the counter type.

[Action]

With such a configuration, according to the present invention, the above object is achieved by the following operations.

That is, using one reference time data and a pair of machining time data, the time data of the rising point and the falling point of the pair of pulses is obtained by the arithmetic unit, and this is stored in the pair of pulse output registers. Then, when the value of the counter matches the rising time data by the comparator, the output terminal of the first pulse output register is changed to the designated binary state (positive or negative), and then matches the falling time data. Reset when you do. Similarly, the output terminal of the second pulse output register is operated in reverse to the first. As a result, a pair of pulses having a pattern suitable for driving the switching elements of the upper and lower arms that are operated complementarily are generated. Therefore, since the time data that must be transferred from the upper CPU is reduced by one per phase, the data transfer load on the upper CPU is reduced. Further, the host CPU does not need to perform the arithmetic processing for controlling the time difference between the pair of pulses, so that the load is reduced.

Also, according to the one using the up / down counter,
By performing up-reset and down-reset of the counter in accordance with the cycle of the PWM carrier, the rising and falling points of the pulse can be controlled with only one time data, and the processing of the arithmetic unit is simplified.

〔Example〕

 Hereinafter, the present invention will be described based on examples.

FIG. 1 shows a block diagram of a pulse generating apparatus according to a first embodiment to which the present invention is applied. In the present embodiment, a pair of pulses are generated in which the time axis and the width of the pulses are in a fixed relationship, and the binary states are in a mutually complementary relationship (hereinafter, referred to as opposite polarity). That is, it is suitable for generating a gate pulse for driving a switching element of an inverter upper and lower arm, for example. In FIG.
Control register 1 and reference time data register 2
First and second processing time data registers 3 and 4;
And the second state data registers 5 and 6 are connected to an upper CPU (not shown) via a bus 7, respectively. In each of these registers, a control signal, reference time data, first and second processing time data (1) and (2), and state data are stored by transfer from the upper CPU. ing. The state data is transferred at the time of initialization, and the other data is transferred periodically according to the count-up signal as described later.

The reference time data and the processing time data (1) and (2) are taken into the arithmetic unit 8, and the time data (1) and (2) are obtained by predetermined arithmetic processing. The time data (1) and (2) are transferred by the transfer control unit 9 to the first and second time data registers 10 and 11, respectively.

The control signals include a counter control signal 12, an operation control signal 13, a transfer control signal 14, and an output switch control signal 15. The counter control signal 12 includes a count-up signal and a count-down signal input at a predetermined cycle, and is input to the up-down counter 16. The up / down counter 16 receives a clock pulse. The count value 17 of the up / down counter 16 is input to first and second comparators 18 and 19. The comparators 18 and 19 are compared with the time data (1) and (2) of the time data registers 10 and 11, respectively. When they match, the match signals 20 and 21 are sent to the first and second pulse output registers 5 and 6, respectively. Is entered. The pulse output registers 5 and 6 have the same configuration including flip-flops, and each have a pair of output terminals (+) and inverted output terminals (-) that are held in a complementary state. When the state data is input, the state data is reset to the inverted state of the binary state specified by the state data. The pair of output terminals are connected to the pulse (1) via output switches 22 and 23,
It is connected to the output lines 24 and 25 of (2). The output switches 22 and 23 are connected to the output switch control signal 17
And a pulse having a desired polarity can be obtained. In this embodiment, the pulse (1) is set to a positive pulse, and the pulse (2) is set to a negative pulse.

The operation of the embodiment configured as described above will be described with reference to FIGS. 2 and 3. FIG. 3 is a conceptual diagram of a PWM pulse calculated and processed by the host CPU. The host CPU compares the output voltage command of the inverter with the triangular carrier wave to determine the reference pulse for the upper and lower arms. Based on this, the positive pulse is narrowed and the negative pulse is widened considering the dead time described above. Is determined. This operation is U, V,
W Performed for each phase. Then, the time T from the base point of the cycle T0 of the triangular wave to the rising point of the reference pulse, the processing time data T1 of the upper arm pulse, and the processing time data T2 of the lower arm pulse are obtained. Or, the state data (positive or negative) of the lower pulse and the control signal are transferred to the pulse generator. This transfer timing is performed in accordance with a count-up signal output in synchronization with the base point of the cycle of the triangular wave.

When data is transferred to the pulse generator in this way, first, the up / down counter 16 starts counting up. The up / down counter 16 is reset by a countdown signal stored in the control register 1 at a timing of 1/2 of the period T0, and starts counting down. The arithmetic unit 8 is started by the arithmetic control signal 13 and obtains time data (1) and (2) by a predetermined arithmetic process. Various methods can be considered for this arithmetic processing. In this embodiment, the processing time data (1) is added to the reference time data T to obtain the time data (1), while the processing time data (2) is obtained from the reference time data T. ) Is subtracted to obtain time data (2). The time data (1) and (2) are transferred to the transfer control unit 9 in accordance with the transfer destination and transfer timing indicated by the transfer control signal 14.
Are transferred to the time data registers 10 and 11, respectively. It is desirable that the arithmetic unit 8 and the transfer control unit 9 be constituted by a simple microprocessor. In this case, the arithmetic processing and transfer control can be realized by a program, and the control signal given from the host CPU is simplified. However, the present invention is not limited to this.
Obviously, each transfer control can be configured by hardware.

When the time data (1) and (2) are stored in the time data registers 10 and 11 in this manner, the comparators 18 and 19 compare the count value of the up / down counter 16 with each other. At that time, the coincidence signals 20 and 21 are output to the corresponding pulse output registers 5 and 6, respectively. As a result, the flip-flops of the pulse output registers 5 and 6 are set, and the output line 24 becomes positive and the output line 25 becomes negative via the output switches 22 and 23. Then, when the counter 16 switches to countdown, when the count value again matches the time data (1), (2), the match signals 20, 2
1 is output. As a result, the flip-flops of the pulse output registers 5 and 6 are reset, the polarities of the output lines 24 and 25 are inverted, and desired pulses (1) and (2) are obtained.

As described above, according to the present embodiment, upon generating a pair of pulses each having a complementary relationship and a wide negative pulse with respect to the positive pulse, the reference time data defining the time axis of the pair of pulses, One time data (1) and (2) are obtained by the arithmetic unit 8 from the two machining time data indicating the relationship with the processing time data, and this is compared with the count value of the up / down counter 16 to form a pair. Since the rising and falling points of the pulse are defined, the time data that must be transferred from the upper CPU is reduced by one per pair of pulses.
Therefore, in the case of three phases, the transfer data is reduced by three.

In defining the binary state of a pair of pulses,
Since the two pulse output registers are formed in a complementary relationship, only one state data needs to be transferred from the host CPU, and in the case of three phases, the transfer data is further reduced by three.

In addition, since the dead time calculation process is performed by the pulse generation device, the upper CP related to the data transfer is performed.
In addition to reducing the load on U, the calculation load can be further reduced.

Also, because an up-down counter is used,
Since the rising and falling points of the pulse can be defined by one piece of time data, the arithmetic processing of the arithmetic unit 8 is simple.

Further, since the pulse output registers 5 and 6 have a pair of complementary output terminals, and the binary state of the pulse can be selected by the output switches 22 and 23, the pulse output registers 5 and 6 can be applied to a pulse generator other than the switching pulse of the upper and lower arms of the inverter. Applicable,
There is versatility.

The method of determining the processing time data for narrowing the positive pulse and widening the negative pulse in consideration of the dead time described above is described in the first embodiment, and in addition to FIGS. 4, 5, and 6. Can be applied.

In FIG. 4, the required dead time is provided by delaying only the rising point of both the positive pulse and the negative pulse with respect to the reference pulse. Therefore, the arithmetic unit 8 calculates T + T1 and T-T2 as in the first embodiment, but treats T + T1 and T as time data (1), and treats T and T-T2 as time data (2) as one set. Will be Then, the transfer control unit 9 transfers T + T1 to the time data register 10 and T to the time data register 11 in synchronization with the count-up signal, and transfers T to the time data register 10 and the time data register 11 in synchronization with the count-down signal.
To T-T2. Thereby, the illustrated pulse (1),
(2) is output.

In FIG. 5, the required dead time is provided by delaying only the falling point of both the positive pulse and the negative pulse with respect to the reference pulse.

In FIG. 6, the positive pulse coincides with the reference pulse, the falling point of the negative pulse is accelerated, and the rising point is delayed.

FIG. 7 shows a time chart of the second embodiment of the present invention. This embodiment differs from the first embodiment in that a free-run counter is used instead of the up-down counter 16. In addition, the operation functions of the arithmetic unit 8 and the transfer control unit 9 are different. The operation of this embodiment will be described with reference to FIG. The pulse relationship is the same as in FIGS. 7 and 2. The transfer data from the host CPU is almost the same as in the case of FIG. 2, except that the command given to the free-run counter is a reset signal synchronized with the cycle of the carrier wave. A transfer control signal 14 is provided for each half of the carrier wave cycle (corresponding to the countdown signal). When each data is transferred, the arithmetic and control unit 8 sets one set of T as time data (1).
+ T1, T0- (T + T1) and time data (2)
To obtain a set of T-T2, T0- (T-T2). Then, these time data are transferred to the time data registers 10 and 11 in accordance with the transfer timing, that is, the illustrated timing. Thereby, the same pulse (1) as in FIG.
(2) can be generated and output.

Although this embodiment is not shown, FIGS.
The present invention can be similarly applied to pulse generation corresponding to the modification shown in FIGS.

8 and 9 show configuration diagrams of an embodiment in which the pulse generation device of the present invention is applied to a motor control device. Particularly, in the present embodiment, the method of providing the dead time can be selected according to the direction (polarity) of the load current flowing through the motor. In the present embodiment, the electric motor 31 is driven and controlled by the voltage-source inverter 30, and the switching elements 34a, b and 35a, b and 36a, b of the voltage-source inverter 30 are each controlled by a pulse output from the inverter controller 33. It is designed to be driven on and off. The inverter control device 33 includes a CPU and a pulse generation device, and the pulse generation device generates the pulse based on control data input from the CPU.
The inverter control device 33 has load currents 38a, 38b, 38c for each phase.
, A magnetic pole position signal of the electric motor and a rotation direction detection signal are input from the rotation detector 39.

FIG. 9 shows the configuration of the pulse generator 33. Since the PWM pulse generation method in this device is the same for each phase, only one phase will be described here. In the motor control using the voltage source inverter device shown in FIG. 8, when one switch of the upper and lower arms is turned off at the same time as the other switch is turned on, a certain time is required for turning off the switch as described above. Therefore, an arm short circuit occurs. In order to avoid this arm short circuit, it is necessary to provide a dead time during which both the upper and lower arms are turned off. The inverter control device 33 fetches the data of the motor current, the magnetic pole position, and the rotation direction, and executes the control calculation by the CPU. The CPU calculates the speed of the electric motor by control calculation, and obtains reference time data which is data of a duty of a pulse signal according to a deviation between the detected speed and the command speed. Then, dead time data T ₁ , dead time data T ₂ and a state signal for generating the dead time are obtained. Further, the CPU discriminates the direction of the current and determines the data processing method in the arithmetic unit 8 by using the arithmetic control signal 1.
3. A transfer control signal 14 for instructing the transfer order and timing of data in the transfer control unit 9 is generated. Finally CPU
Storing the reference time data register 2 the reference time data T, the dead time data T ₁ processing time register 3, the dead time data T ₂ processing time register 4, each control signal in the control register 1. The data stored in each register is added and subtracted by the arithmetic unit 8 according to the method indicated by the control signal.

The method of adding a dead time according to the present embodiment is as shown in FIG.
The three types shown in FIGS. 4 and 5 are switched and applied. That is, the first method delays the rising point of the pair of positive and negative pulses with respect to the reference pulse, and advances the falling point. The second method delays only the rising points of the positive and negative pulses with respect to the reference pulse. The third method is to advance only the falling point of the positive and negative pulses with respect to the reference pulse. The time data obtained by any of these is transferred to the transfer control unit 9 and transferred to the time data register 40 at a timing according to a transfer control signal given from the CPU. The time data transferred to the time data register 40 is immediately compared with the count value of the counter 16, and when they match, a binary PWM pulse is output according to the state data stored in the state data register 41, This allows the motor 3
One is to control.

Incidentally, the output voltage during the dead time period changes depending on the direction of the load current. For example, in the case of the second method,
As shown in Figure 10, when the direction of the load current is to the load,
The output voltage (point a) decreases with respect to the reference pulse only in the shaded portion. On the other hand, when the load current is flowing from the motor to the inverter, the output voltage is increased by the hatched portion with respect to the reference pulse. Therefore, if the dead time method is fixed to one method, an error voltage as described above may be generated, and the output voltage does not conform to the command, resulting in a problem that control accuracy is reduced.

Therefore, in order to solve such a problem, in the present embodiment, the above three methods are switched and used according to the direction of the self-load current. That is, the CPU determines the direction of the load current, selects a method in which the error voltage does not occur, and transfers the operation control signal to the operation control unit 8.

FIG. 12 shows a time chart of the arithmetic processing in the CPU of the FIG. 8 embodiment. As shown, the inverter control device
The 33 CPU fetches the data of the current, the magnetic pole position, and the rotation direction, and executes the control calculation. In the control calculation, as shown in FIG. 12, the speed of the motor to be controlled is calculated, and reference time data, which is data for defining the duty of the pulse signal according to the deviation between the detected speed and the command speed, is calculated. Next, machining time data (1) for generating dead time for avoiding a short circuit between the upper and lower arms of the voltage type inverter 30,
(2) is calculated. Further, a current direction is determined, and an arithmetic control signal for determining a processing method is generated. The CPU stores the reference time data in the reference time data register 2, the processing time data (1) and (2) in the processing time data registers 3 and 4, and the control signal in the control register 1. Thus, the arithmetic unit 8 generates time data for obtaining a desired PWM signal by adding or subtracting the reference time data and the processing time data (1) and (2). Therefore, as described above, also in this embodiment, the function of the arithmetic unit 8 reduces the load of the arithmetic processing of the CPU.

〔The invention's effect〕

As described above, according to the present invention, the following effects can be obtained.

That is, using one reference time data and a pair of machining time data, the time data of the rising point and the falling point of the pair of pulses is obtained by the arithmetic unit, and this is stored in the pair of pulse output registers. Then, when the value of the counter matches the rising time data by the comparator, the output terminal of the first pulse output register is changed to the designated binary state (positive or negative), and then matches the falling time data. Reset when you do. Similarly, the output terminal of the second pulse output register is operated in reverse to the first. As a result, a pair of pulses having a pattern suitable for driving the switching elements of the upper and lower arms that are operated complementarily are generated. Therefore, since the time data that must be transferred from the upper CPU is reduced by one per phase, the data transfer load on the upper CPU is reduced. Further, the host CPU does not need to perform the arithmetic processing for controlling the time difference between the pair of pulses, so that the load is reduced.

Also, according to the one using the up / down counter,
By performing up-reset and down-reset of the counter in accordance with the cycle of the PWM carrier, the rising and falling points of the pulse can be controlled with only one time data, and the processing of the arithmetic unit is simplified.

When the processing time data of one pulse is matched with the reference time data, the reference time data register or the first processing time data register can be omitted, and the number of transfer data can be further reduced by one.

Further, each of the pulse output registers has an inverted output terminal that is held in an inverted state of the output terminal, and an output for selectively selecting an output terminal and an inverted output terminal of each of the pulse output registers. According to the configuration in which the switches are provided and each switch is controlled by the output switch control signal stored in the control register, versatility can be provided for the polarity of the generated pulse. According to the motor control device of the present invention,
Since the method of adding the dead time is switched and selected from among the three methods according to the direction of the load current, an error in the output voltage is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a pulse generating apparatus according to the present invention, FIG. 2 is a time chart for explaining the operation of the embodiment of FIG. 1, FIG. 3 is a time chart for explaining the concept of a PWM pulse, FIGS. 4, 5, and 6 are time charts for explaining the operation of another embodiment of the pulse generation calculation method, respectively, and FIG. 7 is a time chart of another embodiment of the pulse generation device of the present invention. FIG. 8 is a block diagram of an embodiment of a motor control device of the present invention, FIG. 9 is a block diagram of a main part of the embodiment of FIG.
10 and 11 are diagrams for explaining the effects of load current and dead time on the output voltage, and FIG. 12 is a diagram showing the CPU of FIG.
6 is a time chart of the calculation contents according to FIG. 1 ... Control register, 2 ... Reference time data register, 3,4 ... Processing time data register, 5,6,41 ...
Pulse output register, 8 arithmetic unit, 9 transfer control unit, 10, 11, 40 time data register, 16
… Up / down counter, 18,19 …… Comparator, 22,23 ……
Output switch, 30 ... Inverter circuit, 33 ... Inverter control device.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Sanshiro Ohara 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (58) Field surveyed (Int.Cl. ⁶ , DB name) H02M 7/42- 7/98

Claims (5)

(57) [Claims] 1. A reference time data register storing reference time data defining a time axis of a pair of pulses to be generated, and processing time data indicating a relationship of the time of each pulse with respect to the reference time data. First and second processing time data registers, first and second pulse output registers respectively storing state data designating a binary state of one of the pair of pulses, and a control signal. A control register to be stored, a counter that counts clock pulses, an arithmetic unit that takes in the reference time data and each of the processing time data and obtains time data of the rise and fall of each of the pulses by an addition / subtraction operation, Transfer for controlling transfer timing of each time data of each of the pulses obtained by the arithmetic unit Control unit, first and second time data registers respectively storing time data of the respective pulses output from the transfer control unit, and time data of the respective time data registers and the value of the counter. The first that outputs a coincidence signal when a comparison and a coincidence are made
And a second comparator, wherein the arithmetic unit performs arithmetic processing determined by an arithmetic control signal stored in the control register, and the transfer control unit performs a transfer process stored in the control register. The transfer timing of each time data is controlled according to a control signal, the first pulse output register has an output terminal that is reset to a binary state obtained by inverting the stored state data, The second pulse output register has an output terminal that is reset to a binary state of the stored state data, and the first and second pulse output registers each have one match from the corresponding comparator. Inverts the binary state of the output terminal when a signal is input, and the binary state of the output terminal when the next match signal is input The counter is reset by a reset signal stored in the control register at a constant period, and the reference time data, the respective processing time data, the state data, and the control signal are the counter. The pulse generator of the power converter, which is externally input in accordance with the transfer cycle of the count-up / reset signal. 2. A reference time data register storing reference time data defining a time axis of a pair of pulses to be generated, and processing time data indicating a time relationship of each pulse with respect to the reference time data are stored. First and second machining time data registers, first and second pulse output registers respectively storing state data designating a binary state of one of the pair of pulses, and a control signal stored therein. A control register, a counter that counts clock pulses, an arithmetic unit that takes in the reference time data and each of the processing time data, and obtains rising and falling time data of each of the pulses by an addition / subtraction operation. A transfer system for controlling a transfer timing of each time data of each pulse obtained by the arithmetic unit; A unit, first and second time data registers respectively storing time data of the respective pulses output from the transfer control unit, and comparing the time data of the respective time data registers with the value of the counter. And a first comparator and a second comparator that output a match signal when they match with each other, wherein the arithmetic unit performs arithmetic processing defined by an arithmetic control signal stored in the control register, The transfer control unit controls a transfer timing of each time data according to a transfer control signal stored in the control register, and each of the pulse output registers is reset to a binary state different from the stored state data. Output terminal and an inverted output terminal held in an inverted state of the output terminal. In addition, when one match signal is input from the corresponding comparator, the binary state of the pair of output terminals is inverted, and when the next match signal is input, the binary state of the pair of output terminals is reset. The counter is reset by a reset signal stored in the control register at a constant cycle, and the reference time data, the respective processing time data, the state data, and the control signal are stored in the control register. A pulse generation device of a power conversion device which is externally input in accordance with a transfer cycle of a count-up / reset signal. 3. The pulse generator according to claim 1, wherein each of said pulse output registers has an inverted output terminal which is held in an inverted state of said output terminal. 4. An output switch for selectively selecting an output terminal and an inverted output terminal of each of the pulse output registers,
4. The pulse generator according to claim 2, wherein each switch is controlled by an output switch control signal stored in the control register. 5. The pulse generator according to claim 1, wherein said counter is a free-run counter.