JP2932855B2 - Multiple input / output memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexed input / output memory, and more particularly to a multiplexed input / output memory which is connected to a bus for inputting / outputting a plurality of data, and writes / reads data into / from a main memory via the plurality of buses. Multiplex input / output memory.

[0002]

2. Description of the Related Art Conventional multiple input / output memories connected to a plurality of buses and having one main storage unit are arranged on a first-come, first-served basis.
When writing or reading data in accordance with external data read or write instructions connected to these buses is performed only one at a time, and when read or write instructions for data from different buses conflict, Only when data is written or read for one of the buses, after the above-described operation for the previously accessed bus is completed, the write or read operation according to the next instruction is performed. ing.

[0003]

In the above-described conventional multiple input / output memory, as the number of connected buses increases, the frequency of read or write instructions to the main storage unit increases, It has the disadvantage that the average access time for reading and writing data to and from the main storage unit for one bus is increased, and the efficiency of reading and writing data is reduced.

[0004] It is an object of the present invention to provide a multiplexed input / output capable of simultaneously performing data write or read access in parallel when a single main storage unit has a different address range through a plurality of different buses. To provide memory.

[0005]

A multiplex input / output memory according to the present invention has a main storage section composed of a plurality of data bank memories, and is connected to a plurality of data buses in a one-to-one correspondence. A plurality of memory bus interface units for separating and outputting the write data to be added and the command including the address and outputting the data read from the main storage unit to the data bus; One-to-one on the side opposite to the bus connection side
Address that is connected to and receives the address and command /
A command control unit, a data input / output unit connected to the memory bus interface unit on a one-to-one side opposite to the bus, and a plurality of the address / command control units connected one-to-one for each memory bank A memory bank control unit that selects one by one from a command and an address output from the unit and outputs an address and a command to the connected memory bank; and a memory that is connected to the memory bank on a one-to-one basis. A memory data input / output unit that outputs write data to the bank and read data from the data bank to the data input / output unit, and the address / command control unit includes the memory / input / output unit.
Upon receiving an address and a command from the bus interface unit, a corresponding memory bank is selected from the plurality of memory banks, an access request signal is output to the memory bank control unit connected to the selected memory bank, and the address is held. The data holding signal is output to the data input unit connected to the same memory bus interface unit until the end signal is received from the corresponding memory bank control unit. Outputs a data output signal when is a write instruction, and outputs a read data selection signal for selecting read data from a corresponding data bank when the command is a read instruction. When a signal is received, the memory bus interface unit The write data latch that holds the received write data and outputs the held data when receiving the data output signal, and selects the corresponding read data when receiving the read selection signal and is connected to the data input / output unit. A read data selector for outputting to the memory bus interface unit, wherein the memory bank control unit receives the access request signal on a first-come, first-served basis and when writing or reading is not performed on the corresponding memory bank or when the memory bank is completed. The end signal is output to the address / command control unit that has output the address request signal, and the corresponding address / command is output.
An address and a command from a command control unit are selected to perform write or read access to the connected memory bank, and when the selected command is a write command, a corresponding one of the plurality of data input / output units is selected. A write data selection signal for selecting write data from the data input / output unit to be output to the corresponding memory data input / output unit, and the memory data input / output unit outputs the read data read from the corresponding memory bank to the data When the read data buffer output to the input unit and the write data selection signal are received, the write data specified by the write data selection signal is selected and connected among the write data output from the plurality of data input / output units. A write data selector for outputting to the memory bank. It is.

[0006]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the multiplexed input / output memory of the present invention. FIG. 2 shows the configuration of the address / command control unit 5A and the data input / output unit 9A shown in FIG. FIG. 3 is a detailed block diagram showing the configuration of the memory bank control unit 12A and the memory data input / output unit 15A shown in FIG.

As shown in FIG. 1, the multiplex input / output memory according to the present embodiment has a main storage unit 2 composed of N memory banks 2A to 2N and a one-to-one correspondence between memory banks 2A to 2N.
Memory bank control units 1 respectively connected to
2A to 12N and one each for the memory banks 2A to 2N.
Memory data input / output units 15A-1 connected to one to one
5N and M address / command controllers 5A to 5A to 5M connected to the memory bank controllers 12A to 12N.
5M and the aforementioned memory data input / output units 15A to 15N
M input / output units 9A to 9M connected to each other, and M memories connected to one of the above-mentioned address / command control units 5A to 5M and the other connected to buses 4A to 4M, respectively. Bus interface units 3A to 3M
It is composed of

The above-mentioned data input / output unit 9A is also connected to a memory bus interface unit 3A, and similarly, the data input / output unit 9B is connected to the memory bus interface unit 3B. Similarly, the data input / output unit 9M is also connected to the memory bus interface unit 3M.

Each of the memory bank controllers 12A to 12N determines whether the memory bank to which it is connected is being accessed and outputs the above-described write data selection signal to the corresponding memory data input / output unit. Except for the memory data input / output unit 1
5A to 15N have the same configuration.

The address / command control units 5B to 5B
M has the same configuration as the address / command control unit 5A, and the data input / output units 9B to 9M have the same configuration as the data input / output unit 9A.

Further, a memory bus interface unit 3A
To 3M also have the same configuration. As is clear from the above description, the number of buses is equal to the number of the address / command control units and the memory bus interface units, and similarly, the number of data input / output units is also equal to the number of buses.

Each of the buses 4A to 4M is connected to an information processing device (not shown), and an address in the main storage unit to be accessed when writing data to the main storage unit 2 and reading data from the main storage unit 2. And when the command is a data write, the data to be written is externally applied to any of these buses 4A to 4M.

When a command including such an address and data for writing to the main storage unit 2 are applied to the memory bus interface unit 3A via the bus 4A, for example, the memory bus interface unit 3
A separates a command including an input address from the above-described data, and converts a command including an address into an address /
It outputs to the command control unit 5A, and outputs data to the data input / output unit 9A.

When data read from the main memory is output from the data input / output unit 9A to the memory bus interface unit 3A, the data is output to the bus 4A.

Other Memory Bus Interfaces 3A-3
M performs the same operation.

The address / command control unit 5A and the data input / output unit 9A are configured as shown in FIG. 2, that is, the address / command control unit 5A includes an address latch 7A, a command latch 8A, The input side of the address latch 7A and the command latch 8A is connected to a terminal for outputting a command including an address of the memory bus interface 3A.

The address latch 7A separates and latches the address output from the memory bus interface unit 3A.
The address is output to each of the memory bank control units 12A to 12N as an address 25A and is also output to the command determination unit 6A. The command latch 8A latches the command output from the memory bus interface unit 3A and outputs it to the command determination unit 6A. When the command latch 8A outputs a command, the command determination unit 6A receives the command, and determines the memory bank specified by the command from the memory bank 2A to the memory bank 2A based on the separately received address value.
N is determined, and one of the access request signals 26A1 to 26AN to the memory bank control units connected to the corresponding one of the memory bank control units 12A to 12N is determined. Output one.

When the command judging unit 6A receives the corresponding access end signal described later, the hold signal 27
A is output to output the address and the command latched in the address latch 7A and the command latch 8A, respectively, to the corresponding one of the memory bank controllers 12A to 12N. Command judgment unit 6
If the command received by A is a write command, the command determination unit 6A outputs a data holding signal 30A. If the command input so far is a read command when the end signal is received, A read data selection signal for selecting an output from a memory data input / output unit connected to a corresponding one of the memory data input / output units 15A to 15N is output. If a related command is a write instruction, , And outputs a data output signal 30A.

As shown in FIG. 2, the data input / output section 9A receives write data output from the memory bus interface section 3A whose input side is connected to the data input / output side of the memory bus interface section 3A. It comprises a write data latch 10A to be latched and a read data selector 11A whose output side is connected to the data input / output side of the aforementioned memory bus interface 3A.

The output side of the write data latch 10A is connected to each of the memory data input / output units 15A to 14N. When the data output signal 30A is output from the command determination unit 6A, the write data held in the write data latch 10 is output. Output.

The read data selector 11A receives the read data 32A to 32N output from the memory data input / output units 15A to 15N, selects the read data specified by the read data selection signal 29A, and selects a memory bus interface. Output to the unit 3A.

The address / command control units 5B to 5M shown in FIG.
A, and the data input / output units 9B to 9M shown in the figure also have the same configuration as the data input / output unit 9A.

The configuration of the memory bank control unit 12A receives addresses 25A to 25M output from the address / command control units 5A to 5M, and receives an address selection signal 3 described later.
4A, an address selector 13A that selects one of them and outputs it to the memory bank 2A, and an access request signal 26 output from the address / command control units 5A to 5M.
A1 to 26N1 are received, and the addresses 25A to 25N output from the address / command control units 5A to 5M in the order of reception.
An address selection signal 34A for designating a corresponding address within 25M is output and access request signals 26A1 to 26M
1, the memory bank 2A is accessed in response to the corresponding address request signal, and when the received access request is a write command, the write data 31A to 31M output from the data input / output units 9A to 9M are used. And a command selection unit 14A that outputs a write data selection signal 33A for designating one of the above.

As shown in FIG. 3, the memory data input / output unit 15A receives the write data 31A to 31M output from the data input / output units 9A to 9M, and receives the write data designated by the write data selection signal 33A. A write data selector 16A for selecting data and outputting the selected data to the memory bank 2A; and a read data buffer 1 for accessing data read from the memory bank 2A by the command selection unit 14A and receiving and outputting the data as read data 32A.
7A.

The memory bank control units 12B to 12N shown in FIG. 1 are connected to the memory banks 2B to 2N, respectively, and are similar to the above-described memory bank control unit 12A except that they access the corresponding memory banks. It has the same configuration and performs the same operation.

The memory data input / output units 15B to 15N shown in FIG.
B to 2N, and is controlled by write data selection signals from the memory bank control units 12B to 12N, respectively, and selects one of the write data 31A to 31M output from the data input / output units 9A to 9M, and It has the same configuration as the memory data input / output unit 15A and performs the same operation except that the data is output to the data bank to be executed.

Now, when a command including an address designating the address of the memory bank 2A is input from the bus 4A to the memory bus interface unit 3A, the memory bus interface unit 3A sends these commands to the address / command control unit 5A. And output the address. In addition, bus 4
When write data to be written to the main storage unit 2 is input from A, this write data is output to the data input / output unit 9A.

The address / command control section 5A holds the input command and address, and determines which memory bank the command corresponds to based on the input address. In this case, it is determined that the memory bank 2A is the corresponding memory bank, and the access request signal 26A1 according to the input command is output to the memory bank controller 12A.

At this time, when the received command is a write command, a data holding signal is output to the data input / output unit 9A, and a data output from the memory bus interface unit 3A in response to the command is performed. Is held in the data input / output unit 9A.

When receiving the access request signal 26A1, the memory bank control unit 12A stores the access request signal 26A1 together with the order of the request. For example, an access end signal 35A1 is output to the address / command control unit 5A. Upon receiving the access end signal 35A1, the address / command control unit 5A outputs the address 25A, and if the command is a write command, outputs the data output signal 30A to the data input / output unit 9A and holds the data output signal 30A until then. The written write data is output from the data input / output unit 9A to the memory data input / output unit 15A as write data 31A.

If the content of the command is a read command, the address / command control section 5A transmits a read data selection signal 29A designating selection of the read data 32A from the memory data input / output section 15A. And outputs the selected read data to the memory bus interface 3A.

When the content of the access request signal 26A1 is a write command, the memory bank control unit 12A sends a write data selection signal 33A specifying the write data 31A from the corresponding data input / output unit 9A to the memory data input / output unit 15A. And output it as write data 22A from the memory data input / output unit 15A.
An address 25A output from the command control unit 5A is selected, and the memory bank 2 specified by the address 25A is selected.
The write data 22A is stored at the address A.

When the content of the access request signal 26A1 is a read command, the memory bank control unit 12A selects the address 25A output from the address / command control unit 5A and stores the address at the corresponding address in the memory bank 2A. The data is input to the memory data input / output unit 15A as read read data 22A, and the input read data is output to the data input unit 9A as read data 32A.

If, during execution of such an access, for example, a command for reading out an address and data specifying the memory bank 2A from the bus 4B is applied to the memory bus interface unit 3B, these addresses and commands are transmitted. The data is output from the memory / bus interface unit 3B to the address / command control unit 5B.

The address / command control unit 5B holds this command and address, and the corresponding memory bank is 2A.
And outputs an access request signal 26B1 to the memory bank controller 12A.

The memory bank control unit 12A accepts the access request signal 26B1, but does not output the access end signal 35B1 until the access relating to the access request 26A1 issued from the address / command control unit 5A that has already been accessed is completed. When the preceding access is completed, an access end signal 35B1 is output to the address / command control unit 5B. At this time,
The memory bank control unit 12A selects the address 25B output from the address / command control unit 5B and outputs it to the memory bank 2A.

The access end signal 35B is sent to the address /
When the command control unit 5B receives the data, the address / command control unit 5B outputs a read data selection signal to the data input / output unit 9B, and reads the read data 32A output from the memory data input / output unit 15A to the memory bus interface. Output to the bus 4B via the unit 3B.

If data is written to or read from the main storage unit 2 as described above, any one of the buses 4A to 4M may be used to read data from any of the memory banks 2A to 2N. Is executed, there is a command from any of the remaining buses 4A to 4M to the remaining memory banks other than the above-mentioned access being performed among the above-mentioned memory banks. At times, an access corresponding to a new command can be performed in parallel with an access that has already been performed.

[0040]

As described above, in the multiple input / output memory of the present invention, even if there are access requests from a plurality of buses, when the memory banks in the main memory to be accessed are different, these access requests are simultaneously made. Since the processing can be performed, there is an effect that even when the number of connected buses becomes large and the frequency of access becomes large, it is possible to efficiently execute access to the main storage unit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a multiple input / output memory of the present invention.

FIG. 2 is a detailed block diagram showing an address / command control unit 5A and a data input / output unit 9A in FIG.

FIG. 3 is a detailed block diagram showing a memory bank control unit 12A and a memory data input / output unit 15A in FIG. 1;

[Explanation of symbols]

 Reference Signs List 1 control unit 2 main storage unit 2A to 2N memory bank 3A to 3M memory bus interface unit 5A to 5M address / command control unit 9A to 9M data input / output unit 12A to 12N memory bank control unit 15A to 15N memory data input / output unit

Claims (1)

(57) [Claims] 1. A main storage unit composed of a plurality of data bank memories and a command including addresses and write data connected to the plurality of data buses one by one and applied via the data buses. A plurality of memory bus interface sections for outputting data read out from the main storage section to the data bus, and a pair of the memory bus interface sections on a side opposite to the bus connection side with respect to the memory bus interface section. An address / command control unit connected to the memory bus interface unit 1 for receiving an address and a command; a data input / output unit connected to the memory bus interface unit on a one-to-one basis on the opposite side to the bus; Memory banks connected one-by-one selected one by one from commands and addresses output from the plurality of address / command control units connected one-to-one A memory bank control unit for outputting an address and a command to the memory bank;
And a memory data input / output unit for outputting write data to the connected memory bank and outputting read data from the data bank to the data input / output unit. When an address and a command are received from the memory bus interface unit, a corresponding memory bank is selected from the plurality of memory banks, an access request signal is output to the memory bank control unit connected to the selected memory bank, and the address is output. Holding and sending out the same, and outputs a data holding signal to the data input unit connected to the same memory bus interface unit and receives the end signal until the end signal is received from the corresponding memory bank control unit. When the command is a write command, a data output signal is output. Above when the command is a read command, and outputs the read data selection signal for selecting the read data from the corresponding database, the data input-output unit the memory and receiving the data hold signal
The write data latch which holds the write data received from the bus interface unit and outputs the held data when receiving the data output signal, and selects the corresponding read data when receiving the read selection signal, and sends the read data to the data input / output unit. A read data selector for outputting to the connected memory bus interface unit, and when the memory bank control unit receives the access request signal, the memory bank control unit receives the access request signal on a first-come, first-served basis and does not perform writing or reading to the corresponding memory bank. Alternatively, the memory outputs the end signal to the address / command control unit that has output the address request signal when the operation is completed, and selects and connects an address and a command from the corresponding address / command control unit. Write or read to bank When the access is performed and the selected command is a write command, a write data selection signal for selecting write data from a corresponding data input / output unit among the plurality of data input / output units is applied to the corresponding memory data input / output unit. And the memory data input / output unit receives a read data buffer for outputting read data read from a corresponding memory bank to the data input unit and the write data selection signal. A write data selector for selecting write data specified by the write data selection signal from the write data to be output and outputting the selected write data to the connected memory bank.