JP2933030B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus employing the VLIW method, and more particularly, to an information processing apparatus capable of reducing the number of NOP instructions inserted for instruction pipeline scheduling.

[0002]

2. Description of the Related Art One of parallel processing techniques in an information processing apparatus.
One is a fine-grain parallel processing method. This method searches for instructions that can be executed in parallel at a fine instruction level and executes those instructions in parallel. There are a hardware method and a software method.

As a method of dynamically performing instruction execution by hardware, there is a superscalar method. This method is widely used in commercially available microprocessors, and is a technology with a considerable track record at the product level. The advantage is that it is easy to get performance without a very advanced optimization technique for the compiler. On the other hand, the disadvantages are that the hardware such as products, parts, and circuits increases, which causes the use of the limited area of the LSI and the increase of the critical path which is a hindrance for realizing a high-speed clock. It is easy to invite.

As a method of scheduling instruction execution by software, VLIW (very
Long Instruction set Wor
d) There is a method. The advantage of this method is that, contrary to the superscalar method, the compiler takes over the instruction scheduling function, so that the hardware is simplified and a high-speed clock is easily realized. On the other hand, the disadvantages are that advanced optimization technology is required for the compiler, and depending on the type of application program, no matter how much the optimization technology of the compiler is used, performance may not be achieved. However, the advantage of the VLIW system that the hardware is simple is unavoidable and will be adopted in a commercial microprocessor in the future.

[0005] In the VLIW system, when a compiler performs instruction scheduling on an instruction pipeline, first, a register reference relationship between short instructions is analyzed. And if there is a register reference relationship between short instructions,
The timing at which the subsequent instruction waiting for the result of the preceding short instruction should be issued is determined. After the issuance of a short instruction, the time until the result is obtained is fixed depending on the type of the short instruction, so that the issuance timing of the subsequent instruction can be easily obtained. Then, by inserting a short instruction group unrelated to the preceding short instruction until the result of the preceding short instruction is obtained, scheduling is performed so that the instructions can flow without disturbance in the instruction pipeline.

[0006]

However, there is actually no short instruction irrelevant to the preceding short instruction so that the instruction is executed without interruption, and the compiler inserts a NOP (No Operation) instruction at the vacant timing. I do.
As described above, the NOP instruction plays a large role when scheduling is performed by the compiler.

[0007] However, depending on the type of program, the number of NOP instructions generated by the compiler may be larger than that of ordinary short instructions. In such a case,
Since a large number of NOP instructions generated by the scheduling of the compiler are fetched from the main storage device, the short instructions to be executed are not sufficiently supplied to the instruction execution unit.
There is a problem that parallel processing at the instruction level, which is the lifeline of the LIW method, may not be performed sufficiently. Japanese Patent Application Laid-Open No. 4-275603 discloses a technique for reducing the number of NOP instructions by adding the number of executions to the NOP instruction itself. In the information processing apparatus, the number of NOP instructions cannot be reduced so much.

SUMMARY OF THE INVENTION An object of the present invention is to provide a VLIW type information processing apparatus which can reduce the number of NOP instructions inserted for scheduling an instruction pipeline.

[0009]

According to the present invention, in order to achieve the above object, in an information processing apparatus employing a VLIW system, a plurality of short instructions which are simultaneously shifted to a decode stage are decoded, and the plurality of short instructions are decoded. If the instruction includes a NOP instruction including designation of a short instruction to shift to the issue stage at the same time and the number of cycles for delaying the shift to the issue stage, information indicating the NOP instruction and the NOP instruction
Indicates a short instruction to shift to the issuance stage at the same time as the instruction
Information and cycle to postpone transition to the publishing stage
A decoder for outputting the Le number, at the timing when valid instruction is no longer present in the issue stage, the de
NOP instruction indicated by information output from coder
And the short instruction are transferred to the issue stage, and the decoding
And a combination circuit for transferring the unmigrated short instruction existing in the decode stage to the issue stage at the timing when the number of cycles output from the decoder has elapsed.

[0010] In the above-mentioned configuration, of a plurality of short instructions which have simultaneously shifted to the decode stage, the designation of the short instruction to shift to the issue stage and the number of cycles for delaying the shift to the issue stage at the same time are specified. If there is a NOP instruction including the NOP instruction, the decoder outputs information indicating the NOP instruction.
And shift to the issuing stage simultaneously with the NOP instruction
Information indicating short instructions and postponing the transition to the issue stage
And the combinational circuit outputs
Instruction and short-lived indicated by information output from
Command to the issue stage and output from the decoder.
At the timing when a certain number of cycles have elapsed, the unmigrated short instruction existing in the decode stage is shifted to the issue stage.

Further, the present invention provides a decoding method for preventing the occurrence of disturbance in an instruction pipeline even when the time required for completing a preceding short instruction is not known.
(C) decoding a plurality of short instructions that have simultaneously shifted to the decode stage, and delaying the issuance of the plurality of short instructions until all of the short instructions preceding the short instructions are completed. Advance off designation
If there are NOP instructions including said decoding stay
There is a NOP instruction including advance off designation
Having a configuration for outputting information indicating that the combination
Circuitry is added from the decoder to the decode stage.
Indicates that there is a NOP instruction that includes the specification of bounce off.
If the information is output, it is valid for the publishing stage.
At the timing when there are no more instructions
After the plurality of short instructions in the code stage are shifted to the issue stage, the issuance of each short instruction shifted to the issue stage is delayed until the system busy signal becomes inactive.

In the above configuration, among a plurality of short instructions which have simultaneously shifted to the decode stage, it is instructed to postpone the issue until all short instructions preceding the short instructions are completed. Advanced off designation
If NOP instructions including the presence, decoder, decoding
NOP instruction including advance off designation exists in the stage
Is output, and the combinational circuit outputs
Issuing multiple short instructions that have shifted to the code stage
To delay the issuance of short instructions that are in the issue stage while the system busy signal is active,
When the system busy signal becomes inactive, a short instruction existing in the issue stage is issued .

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. An instruction cache 1, an address array 2, an entry valid bit 3, an address register (ICRA) 4
, IC valid bit 5, comparator 6, and AND gate 7
, An instruction register 8 in the decode stage, an instruction register 9 in the issue stage, and an instruction pipeline control unit 10.

Each entry of the instruction cache 1 stores a copy of a long instruction stored in a main storage device (not shown). When storing a long instruction existing at a certain address on the main storage device in the instruction cache 1, the long instruction is:
It is stored in the entry of the instruction cache 1 indicated by the lower N bits of the address. For example, an instruction whose long N bits of the address are all "0" is stored in the instruction cache 1
When storing an instruction in which only the least significant bit of the lower N bits of the address is “1” in the instruction cache 1, the instruction is stored in the first entry of the instruction cache 1. Store it in the second entry of cache 1. By providing such an instruction cache 1, even if a branch instruction jumps from a previous execution control flow to a completely different address, if the instruction at the jump destination is stored in the instruction cache 1, the main cache is always executed. There is no need to send a fetch request to the storage device.

The address array 2 has an instruction cache 1
There are as many entries as there are, and each entry has
The address of the long instruction stored in the corresponding entry of the instruction cache 1 on the main memory is stored.

The entry valid bit 3 is provided for each entry of the instruction cache 1,
Displays whether or not a valid long instruction is stored in the corresponding entry of.

The address register 4 stores an instruction read address by a system control unit (not shown). The IC valid bit 5 is a bit indicating whether or not the read operation for the instruction cache 1 is valid.

The comparator 6 compares an address stored in the address register 4 with an address read from an entry of the address array 2 indicated by the lower N bits of the address, and outputs a comparison result. That is,
If the comparison result of the comparator 6 is a comparison match, the target long instruction exists in the instruction cache 1. If the comparison result does not match, the target long instruction does not exist in the instruction cache 1.

The AND gate 7 generates an IC hit signal indicating whether or not a target long instruction exists in the instruction cache 1 based on the comparison result of the comparator 6 and the IC valid bit 5. If the IC hit signal indicates that the long instruction of interest is not present in instruction cache 1,
A cache control unit (not shown) transfers a target instruction from the main storage device to the instruction cache 1.

In the instruction register 8 of the decode stage,
A long instruction is supplied from the instruction cache 1. This long instruction is composed of four short instructions, and each short instruction is stored in the da, db, dc, dd portion of the instruction register 8, respectively. In this embodiment, it is assumed that each short instruction has a 32-bit configuration.

In the issue stage, isa,
In the isb, isc, and isd parts, d
Instructions stored in a, db, dc, and dd portions are supplied.

The instruction pipeline control unit 10 has a V-bit control function, an instruction issue control function, a hold function, and an instruction pipeline synchronization control function based on a NOP instruction.

The V bit control function is performed by the instruction registers 8 and 9
Da, db, dc, dd, isa, isb, isc,
This function manages a control flag called a V bit indicating whether or not a valid instruction exists in the isd portion.

The instruction issuance control function is a function for literally controlling the issuance of an instruction. Here, issuance is an act of outputting an execution instruction to an instruction execution unit corresponding to the short instruction. For example, in the case of an operation instruction, an operation execution instruction is output to the operation unit when the instruction is issued.

The hold function is used when an instruction cannot be transferred from the instruction register 8 in the decode stage to the instruction register 9 in the issue stage for any reason, or when the instruction cannot be issued from the instruction register 9 in the issue stage. In the next cycle (next clock), it is a function to stay in the instruction register of the stage and postpone the execution.

Finally, the instruction pipeline synchronization control function based on the NOP instruction is a function unique to the present invention, and is a function for controlling the instruction pipeline according to a NOP instruction unique to the present invention described later.

FIG. 2 is a diagram showing the format of the NOP instruction used in the present embodiment.

The NOP instruction shown in FIG. 2 is one of short instructions of the VLIW system, and has a 32-bit configuration. The first 8 bits are an operation code indicating a NOP instruction. Of the remaining 24 bits, predetermined 2 bits and 3 bits are fields A and B.

The field A indicates the type of the NOP instruction. In this embodiment, the contents of the field A are "00", "01", "10", and "11". NOP3, NO
It shall be called a P4 NOP instruction.

Field B is a field for designating the number of cycles for advance-off or postponement. In the present embodiment, “000” indicates advance off, and “0”
01 ”to“ 111 ”indicate the cycle numbers 1 to 7, respectively. Here, the advance-off instruction indicates the postponement of the issuance of the long instruction until execution of all short instructions preceding the long instruction including the instruction is completed.

Next, the four types NOP1, N
The NOP instruction of OP2, NOP3, NOP4 will be described.

For the NOP instruction of the type NOP1 (NOP1 instruction), of the short instructions that have been dropped to the decode stage at the same time, only the short instruction on the leading side of itself has no valid short instruction in the issue stage. At the timing, it is assumed that the instruction is a short instruction that can shift to the issue stage at the same time as the instruction itself, and the short instruction existing in the decode stage at the timing when the instruction shifts to the issue stage is the instruction to be delayed.

A NOP instruction of the type NOP2 (NOP2 instruction) is a short instruction which has been sent to the decode stage at the same time. A short instruction that can shift to the issue stage at the same time as the instruction no longer exists, and a short instruction that exists in the decode stage at the timing when the instruction shifts to the issue stage is a short instruction to be postponed. .

The NOP instruction of the type NOP3 (NOP3 instruction) is one of the short instructions that have fallen into the decode stage at the same time, the short instruction preceding the self, the short instruction next to the self, and the next short instruction. At the timing when there is no longer a valid short instruction in the issue stage, it is a short instruction that can shift to the issue stage at the same time as it itself, and the short instruction existing in the decode stage is delayed when it shifts to the issue stage. The target short instruction.

A NOP instruction of type NOP4 (NOP4 instruction) is similar to a normal NOP instruction, and has no function of delaying the transition to the issue stage of another short instruction that has simultaneously fallen into the decode stage.

FIG. 3 is a diagram for explaining the function of the field A of the above four types of NOP instructions.

In FIG. 3A, the NOP1 instruction, the instruction X, the instruction Y, and the instruction Z are simultaneously dropped in the da, db, dc, and dd portions of the instruction register 8 in the decode stage. If this state is defined as T, after one cycle (T + 1), only the NOP1 instruction moves to the isa portion of the instruction register 9 in the issue stage.

In FIG. 3B, the NOP2 instruction, the instruction X, the instruction Y, and the instruction Z are simultaneously dropped in the da, db, dc, and dd portions of the instruction register 8 at T, respectively.
One cycle later (T + 1), the NOP2 instruction and the instruction X are respectively stored in the instruction register 9 of the issue stage.
Shift to a and isb parts.

In FIG. 3C, the NOP3 instruction, the instruction X, the instruction Y, and the instruction Z are simultaneously dropped in the da, db, dc, and dd portions of the instruction register 8 at T, respectively.
At (T + 1) one cycle later, the NOP3 instruction, the instruction X, and the instruction Y are respectively stored in the instruction register 9 in the issue stage.
To the isa, isb, and isc parts of

As shown in FIG. 3D, when at T, NOP4 instruction, instruction X, instruction Y, and instruction Z simultaneously fall in the da, db, dc, and dd portions of the instruction register 8, respectively. At (T + 1) after one cycle, all the instructions are in the isa, is
Shift to b, isc, isd parts. As a result, a new subsequent long instruction is dropped in the instruction register 8 of the decode stage.

In FIG. 3 (5), at T, the instructions X, N are stored in the da, db, dc, dd portions of the instruction register 8, respectively.
The OP1 instruction, the instruction Y, and the instruction Z have dropped, and at (T + 1) one cycle later, only the instructions X and NOP1 shift to the isa and isb portions of the instruction register 9 in the issue stage.

In FIG. 3 (6), at T, the instructions X and N are stored in the da, db, dc and dd portions of the instruction register 8, respectively.
The OP2 instruction, the instruction Y, and the instruction Z have dropped, and at (T + 1) one cycle later, the instruction X, the NOP2 instruction,
Only instruction Y isa, in instruction register 9 in the issue stage
Shift to isb and isc parts.

In FIG. 3 (7), at T, the instructions X, N are stored in the da, db, dc, dd portions of the instruction register 8, respectively.
The OP3 instruction, the instruction Y, and the instruction Z have dropped, and all the instructions shift to the instruction register 9 in the issue stage at (T + 1) one cycle later. As a result, the following long instruction falls into the instruction register 8 of the decode stage.

In FIG. 3 (8), the instruction X, the instruction Y, the NOP1 instruction, and the instruction Z are respectively dropped in the da, db, dc, and dd portions of the instruction register 8 at T. T + 1), instruction X, instruction Y, NOP
Only one instruction moves to the isa, isb, and isc portions of the issue stage.

In FIG. 3 (9), the instruction X, the instruction Y, the NOP2 instruction, and the instruction Z are dropped in the da, db, dc, and dd portions of the instruction register 8 at T, respectively, and after one cycle ( At (T + 1), all instructions move to the instruction register 9 in the issue stage. As a result, the following long instruction falls into the instruction register 8 of the decode stage.

In FIG. 3 (10), at time T, the instructions X and X are respectively stored in the da, db, dc and dd portions of the instruction register 8.
The instructions Y, Z, and NOP1 instructions have dropped, and all the instructions move to the instruction register 9 in the issue stage at (T + 1) one cycle later. As a result, the following long instruction falls into the instruction register 8 of the decode stage.

FIGS. 4 and 5 show field B of the NOP instruction.
5 is a time chart for explaining the function of FIG. In this time chart, the leading side (da,
The short instruction on the side closer to isa is shorter than the short instruction on the subsequent side (closer to dd, isd) in the register 9 of the issue stage.
It is assumed that an instruction will be issued or an instruction will be issued.

First, FIG. 4 will be described.

At timing t1, four short instructions ADD, NOP1 (the number of wait cycles specified by field B is one) constituting the long instruction, and SU
B and FDV fall on the da, db, dc and dd portions of the instruction register 8 in the decode stage, respectively. The short instruction SUB is the short instruction ADD written to the register S8.
Is used.

At timing t2, which is the next cycle, the short instructions ADD and NOP1 are transferred to the isa and isb portions of the instruction register 9 in the issue stage and are issued.

At timing t3, the short instruction SU
B, FDV issu of instruction register 9 in the issue stage,
It is moved to the isd part and issued. That is, NOP1
The short instructions SUB and FDV on the subsequent side of the instruction are NOP1
Move to the issue stage one cycle later than the instruction,
publish. The hold control of this pipeline is NO
This can be realized by setting the number of wait cycles “1” at the timing t2 in the P wait counter. When the value set in the NOP wait counter is other than "0", the value is decremented by one every cycle. Note that N
The OP wait counter will be described later in detail. At the timing t3, the short instruction ADD is executed. Further, at timing t3, the subsequent long instruction falls into the instruction register 8 in the decode stage. The subsequent long instruction is composed of four short instructions NOP1 (the number of waiting cycles specified by the field B is four), FIX, FAD, and NOP1. still,
The short instructions FIX and FAD are stored in the register S2.
The execution result written to 0 is used.

At timing t4, of the four short instructions constituting the long instruction existing in the decode stage,
Only the NOP1 instruction is the i of the instruction register 9 in the issue stage.
It is shifted to the sa part and issued. The timing t
In No. 4, the number of wait cycles designated by the field B of the NOP1 instruction is "4" in the NOP wait counter.
Is set, and the other short instructions FIX, FAD, and NOP1 wait for four cycles at timings t4 to t7 in the decode stage. Further, at the timing t4, the execution result of the short instruction ADD is written, and the short instruction SUB using the execution result of the short instruction ADD and the short instruction FDV are executed.

At timing t8, the value of the NOP wait counter becomes "0", so that the short instructions FIX, F
AD, NOP1 is the issu of instruction register 9 in the issue stage.
It is shifted to the b, isc, and isd parts and issued.

At timing t9, the short instruction FDV
Is written, and short instructions FIX and FAD using the execution result are executed.

Next, FIG. 5 will be described.

At timing t1, the four short instructions FDV, FMP, ADD, and SUB constituting the long instruction are stored in the instruction registers 8 of the decode stage by da, db, dc, and d.
It is falling in the d part.

At timing t2, the short instructions FDV, FMP, ADD, and SUB described above are transferred to the isa, isb, isc, and isd portions of the instruction register 9 in the issue stage and are issued. At timing t2, the subsequent long instruction falls into the instruction register 8 in the decode stage. This long instruction has four short instructions NOP1
(It is assumed that advance-off is designated in the field B), ADD, SUB, and MPS. Each short instruction NOP1, ADD, SUB, and MPS is respectively da, db, dc, and dd of the instruction register 8 of the decode stage.
Stored in the part.

At timing t3, the short instruction FD
Since V, FMP, ADD, and SUB are executed, the system busy signal becomes active. At timing t3, short instructions NOP1, ADD, SUB, M
PS isa, is of instruction register 9 in issue stage
Transferred to b, isc, isd parts. But isa
In the part, there is a NOP1 instruction whose advance-off is specified in the field B, and since the system busy signal is active, they are not issued.

At timing t9, when the system busy signal becomes inactive, four short instructions NOP1, ADD, SUB, and MPS whose issuance has been postponed are issued.

FIG. 6 is a block diagram showing an example of the configuration of the instruction pipeline control unit 10, and the decoders 11a to 11d
, A NOP wait counter 12, a combinational circuit 13,
14, V bit management circuits 15a to 15d, flip-flops 16a to 16d, selector 17, and subtractor 1
8.

The V bit management circuits 15a to 15d have a function of managing V bits Vda to Vdd indicating whether a valid short instruction is stored in the da to dd portion of the instruction register 8 in the decode stage, respectively. The V bit management circuit 15a includes a set priority flip-flop FF that holds a V bit Vda indicating whether a valid instruction is stored in the da portion of the instruction register 8, an inverter I, gate circuits G1 and G2, It is composed of
The output of the gate circuit G2 becomes "1" at the timing when the short instruction existing in the da part of the instruction register 8 in the decode stage shifts to the isa part of the instruction register 9 in the issue stage. The other V bit management circuits 15b to 15c have the same configuration as the V bit management circuit 15a.

Each of flip-flops 16a to 16d has a V bit Vi indicating whether a valid short instruction exists in the isa to isd portion of the instruction register 9 in the issue stage.
This is a set-priority flip-flop that holds sa to Visd.

The decoders 11a to 11d correspond to the da to dd portions of the instruction register 8 in the decode stage, respectively. Each of the decoders 11a to 11d decodes a short instruction stored in the da to dd portion of the instruction register 8, and outputs a decoding result. that time,
Each of the decoders 11a to 11d is provided with
The short instruction stored in the dd part is a NOP instruction,
If the number of waiting cycles is set in the field B, the signals DEa to DEd indicating the type of the NOP instruction stored in the da to dd portions of the instruction register 8 are output to the combination circuit 14, and the instruction A NOP-NOPd signal indicating that a NOP instruction instructing to wait for a cycle is stored in the da-dd portion of the register 8 is output to the combinational circuit 13 and the d
It outputs to the selector 17 signals Sa to Sd indicating the number of wait cycles indicated by the NOP instruction stored in the a to dd portions. In addition, d of the instruction register 8
If the short instruction stored in the a to dd part is a NOP instruction and the content of the field B is "000" (in the case of advance-off), the da to
It outputs DEa to DEd signals indicating that a NOP instruction including advance-off designation is stored in the dd portion.

The combinational circuit 13 includes the decoders 11a to 11a
Among the NOPa to NOPd signals output from 11d,
If there is an instruction indicating that a NOP instruction instructing a cycle wait is stored in the instruction register 8, the selector 17 is controlled at the timing when the NOP instruction corresponding to the signal is transferred to the instruction register 9 in the issue stage. , S
out of the number of waiting cycles indicated by the signals a to Sd,
The function of presetting the number of wait cycles corresponding to the NOP instruction shifted to the issue stage to the NOP wait counter 12 or the count value of the NOP wait counter 12 is “0”
If not, it has a function of controlling the selector 17 so that the output of the subtracter 18 that decrements the count value of the NOP wait counter 12 by 1 every cycle is input to the NOP wait counter 12. The instruction register 8 of the decode stage
, The timing at which the short instruction is transferred to the instruction register 9 in the issue stage can be known from the output signals of the V bit management circuits 15a to 15d.

The combinational circuit 14 includes the decoders 11a to 11a.
If it is determined based on the DEa to DEd signals output from the register 11d that there is an NOP instruction instructing the instruction register 8 to wait for a cycle, the NOP instruction and the NO
There is no short instruction instructed to be transferred to the instruction register 9 in the issue stage at the same time as the P instruction, and no effective short instruction exists in the instruction register 9 in the issue stage for the short instruction preceding the NOP instruction. The instruction is transferred to the instruction register 9 on condition that the NOP instruction is shifted to the instruction register 9 in the issue stage until the next timing when the count value of the NOP wait counter 12 becomes “1”. D for register 8
It has a function of outputting an HLD signal and preventing its contents from changing. In the case where a plurality of signals indicating that a NOP instruction indicating a cycle wait is stored in the instruction register 8 are present in the DEa to DEd signals output from the decoders 11a to 11d, the most preceding instruction The above-described processing is performed sequentially from the corresponding decode signal (the decode signal closest to the DEa signal side). Whether there is a valid short instruction in the isa-isd portion of the instruction register 9 in the issue stage is determined by the flip-flops 16a-16d.
Can be known based on the V bits Visa to Visd held by.

Further, the combinational circuit 14 includes the decoder 1
NOP for instructing the instruction register 8 to advance off based on the DEa to DEd signals output from 1a to 11d
If it is determined that an instruction exists, the short instruction stored in the instruction register 8 of the decode stage is transferred to the instruction register 9 on condition that there is no valid short instruction in the instruction register 9 of the issue stage. After that, while the system busy signal is active, an ISHLD signal is output to the instruction register 9 to hold its contents. When the system busy signal becomes inactive, I
The output of the SHLD signal is stopped, and the ISSUEda to ISSUEdd signals are output to an instruction execution unit (not shown) to instruct execution of the short instruction stored in the instruction register 9.

The combination circuit 14 sets the DAHLD to DDHLD signals to "id" when transferring the short instruction existing in the da to dd part of the instruction register 8 in the decode stage to the isa to isd part of the instruction register 9 in the issue stage. 0 "to reset all the flip-flops FF in the V bit management circuits 15a to 15d to V bits Vda to Vdd held by them to indicate that there is no valid short instruction. And the V bits Visa to Visd held by them to indicate that a valid short instruction is present. The DHLD signal output from the combination circuit 14 is DA
The logical sum of the HLD to DDHLD signals is obtained.
The system busy signal is activated when an instruction is being executed by the instruction execution unit. When a DHLD signal becomes "0", that is, when a valid short instruction is stored in the instruction register 8 of the decode stage, a system control unit (not shown) that performs a setting operation for the address register 4 and the IC valid bit 5 is executed. When the data does not exist at all, the setting operation for the address register 4 and the IC valid bit 5 is performed.

FIG. 7 is a diagram for explaining the operation of this embodiment. The operation of this embodiment will be described below with reference to the drawings. still,
In the example of FIG. 7, a long instruction including four short instructions NOP1 (waiting for two cycles), FAD (floating point addition instruction), NOP2 (waiting for one cycle), and FDV (floating point division instruction) has a timing t2. 2 shows the operation when the data falls into the instruction register 8 in the decode stage.

First, at a timing t1, an address is set in the address register 4 and an IC valid bit 5 is set in order to transfer a target long instruction from the instruction cache 1 to the instruction register 8 in the decode stage. If the target long instruction is present in the instruction cache 1, the AND hit 7 outputs an IC hit signal, and the target four short instructions are stored in the instruction register da of the decode stage at the timing t2. ~
Move to dd section.

When the IC hit signal is output from the AND gate 7, the flip-flop FF in each of the V bit management circuits 15a to 15d is set at a timing t2, corresponding to the da to dd portions of the instruction register 8. The V bits Vda to Vdd indicate that a valid short instruction exists.

At timing t2, when the above four short instructions are transferred to the da to dd portions of the instruction register 8 in the decode stage, the decoders 11a to 11d
d decodes it, and outputs the DEa to DEd signals, NOP
a to NOPd signals and Sa to Sd signals are output.

At this time, since the combination signal 14 indicates that the DEa signal output from the decoder 11a is a NOP1 instruction, only the DAHLD signal of the DAHLD to DDHLD signals is set to "0" and the flip-flop is set to "0". Flip-flop 16 of flip-flops 16a to 16d
Only a is set. Thereby, the timing t3
At this time, the NOP1 instruction (waiting for two cycles) existing in the da portion of the instruction register 8 in the decode stage shifts to the isa portion of the instruction register 9 in the issue stage and is issued (the ISSUEda signal is output). .

The timing at which the NOP1 instruction (waiting for two cycles) shifts to the issue stage (timing t3)
In this case, the combinational circuit 13 controls the selector 17 and presets the number of wait cycles (in this case, “2”) indicated by the Sa signal output from the decoder 11 a in the NOP wait counter 12.

At the timing t4, the count value of the NOP wait counter 12 becomes "1".

At timing t5, at timing t5
In step 4, since the count value of the NOP wait counter 12 is "1", the combinational circuit 14 sets the DBHLD to DDHLD signals still "1" to "0" and resets the signals to the reset state. Are set to the set state. As a result, db〜 of the instruction register 8 in the decode stage
The short instruction FAD, NOP2 (waiting for one cycle), and the FDV that existed in the dd portion are stored in the instruction register 9 in the issue stage.
And issuance (ISSUEdb to ISSUEd)
d signal is output). At the timing (timing t5) when the NOP2 instruction (waiting for one cycle) shifts to the issue stage (timing t5), the combinational circuit 13 controls the selector 17 and sets the number of waiting cycles indicated by the Sc signal output from the decoder 11c ( "1" in this case)
Is preset in the NOP wait counter 12.

Next, referring to FIG. 8, “FAD S8 ← S
5, S4 "," FSB S9 ← S8, S4 "," FDV
A case where an instruction sequence having an operand dependency such as “S10 ← S9, S4” will be described.

At timing t1, (1-a) to
The four short instructions FAD, NOP1 (waiting for two cycles), FSB, NOP1 (waiting for two cycles) indicated by (1-d) shift from the instruction cache 1 to the da to dd portions of the instruction register 8 in the decode stage.

At the next timing t2, (1-
The short instructions FAD and NOP1 shown in (a) and (1-b) shift to the isa and isb portions of the instruction register 9 in the issue stage. Short instructions FSB, N indicated by (1-c) and (1-d)
OP1 stays in the decode stage because the NOP1 instruction of (1-b) does not indicate that it should shift to the issue stage at the same time. In addition, N of (1-b)
At timing t2 when the OP1 instruction shifts to the issue stage, the number of wait cycles “2” specified by the instruction is preset in the NOP wait counter 12.

At timing t3, the short instruction FAD of (1-a) is executed, and the count value of the NOP wait counter 12 is set to "1".

At the timing t4, (1-c),
Since the short instruction FSB, NOP1 shown in (1-d) shifts to the isc, isd portion of the instruction register 9 in the issue stage and is issued, the NOP wait counter is issued because the NOP1 instruction shown in (1-d) shifts to the issue stage. At 12, the number of waiting cycles “2” is preset. Also, at timing t4
In this case, a long instruction composed of four short instructions FDV, SUB, FDV, and FAD indicated by (2-a) to (2-d) falls into the da to dd portions of the instruction register 8 in the decode stage. come. These four short instructions shift to the instruction register 9 in the issue stage at the timing t6 when the count value of the NOP wait counter 12 becomes “0”.

FIG. 9 shows an example in which “FAD S8 ← S5, SAD S8” is used by using a NOP instruction (a NOP instruction to which the number of executions is added) disclosed in Japanese Patent Laid-Open No. 4-275603.
4, "FSB S9 ← S8, S4", "FDV S1
This shows a case where an instruction sequence having an operand dependency such as “0 ← S9, S4” is executed.

At timing t1, (1-a) to
Four short instructions FAD, NOP instruction (2
Cycle wait), NOP instruction (2 cycle wait), NO
The P instruction (waiting for two cycles) falls to the da to dd portion of the instruction register 8 in the decode stage.

At the next timing t2, (1-a)
-(1-d) are transferred to the isa-isd portion of the instruction register 9 in the issue stage,
Four short instructions FSB, N shown in (2-a) to (2-d)
The OP instruction (waiting for two cycles), the NOP instruction (waiting for two cycles), and the NOP instruction (waiting for two cycles) fall into the da to dd portion of the decode stage. At timing t2, the number of wait cycles “2” is preset in the NOP wait counter 12.

At timing t3, since the count value of the NOP wait counter 12 is "1", it exists in the da-dd portion of the decode stage (2-a)-(2
The transition to the issue stage of the four short instructions indicated by -d) is postponed.

At timing t4, (2-a) to
The four short instructions indicated by (2-d) are da to
At the same time as shifting to the dd portion, the four short instructions FDV, SUB, FDV, and FAD shown in (3-a) to (3-d) fall to the da to dd portions of the decode stage. Also,
At the timing t4, the waiting cycle number “2” is preset in the NOP waiting counter 12.

At timing t5, since the count value of the NOP wait counter 12 is "1", it exists in the da to dd portion of the decode stage (3-a) to (3).
The transition to the issue stage of the four short instructions indicated by -d) is postponed.

At timing t6, the count value of the NOP wait counter 12 becomes "0", and therefore exists in the decoding stages da to dd (3-a) to (3-a).
The four short instructions shown in d) are the isa-is of the issue stage.
It moves to d part and is issued.

As can be seen from FIGS. 8 and 9, when performing the same arithmetic processing, two NOP instructions need only be inserted in the present invention, whereas six NOP instructions are required in the prior art.

[0090]

As described above, according to the present invention, among a plurality of short instructions which have simultaneously shifted to the decode stage,
At the same time, if there is a NOP instruction including designation of a short instruction to shift to the issue stage and the number of cycles to delay the shift to the issue stage, the NOP instruction and the NOP instruction instruct to shift to the issue stage at the same time. After moving the short instruction to the issue stage,
It has a combinational circuit that delays the transition of the unmigrated short instructions that are present in the decode stage to the issue stage until the specified number of cycles have elapsed, so they must be inserted for instruction pipeline scheduling The number of NOP instructions can be reduced as compared with the prior art. As a result, the data path for instruction fetch can be used efficiently, and the capacity of the executable file of the program can be reduced.

[0091] Further, the present invention is in a plurality of short instructions has moved simultaneously decode stage, advanced all the short instructions preceding than those of the short instructions for instructing to defer issuing them to completion When there is a NOP instruction including OFF designation, after shifting the plurality of short instructions that have shifted to the decode stage to the issue stage, the shift is made to the issue stage until the system busy signal becomes inactive. Since a combinational circuit having a configuration to postpone the issuance of each short instruction is provided, even if the time until the preceding short instruction is completed is not known, no disturbance occurs in the instruction pipeline. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a format of a NOP instruction used in an embodiment of the present invention.

FIG. 3 is a diagram for explaining a function of a field A of a NOP instruction;

FIG. 4 is a diagram for explaining a function of a field B of a NOP instruction.

FIG. 5 is a diagram for explaining a function of a field B of a NOP instruction.

FIG. 6 is a block diagram illustrating a configuration example of an instruction pipeline control unit 10;

FIG. 7 is a time chart for explaining the operation of the embodiment of the present invention.

FIG. 8 is a time chart showing the effect of the present embodiment.

FIG. 9 is a time chart showing that the number of NOP instructions increases in the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Instruction cache 2 ... Address array 3 ... Entry valid bit 4 ... Address register 5 ... IC valid bit 6 ... Comparator 7 ... AND gate 8 ... Decode stage instruction register 9 ... Issue stage instruction register 10 ... Instruction pipeline control Units 11a to 11d Decoder 12 NOP wait counter 13 Combination circuit 14 Combination circuit 15a to 15b V bit management circuit 16a to 16d Flip-flop 17 Selector 18 Subtractor

Claims (3)

(57) [Claims] 1. An information processing apparatus employing a VLIW method.
Multiple short instructions that have simultaneously moved to the decode stageTo
Decrypting, and in the plurality of short instructions,At the same time,
Specify the short instruction to be transferred to the
There is a NOP instruction including the number of cycles to delay the transition
If you doInformation indicating the NOP instruction,
Information indicating a short instruction to shift to the issuing stage at the same time
And the number of cycles to delay the transition to the publishing stage
And a decoder for outputting  Thai no longer has a valid instruction in the issue stage
In the mining, According to information output from the decoder.
NOP instruction and short instructionThe issuing stage
ToOutput from the decoderThe number of cycles
In the decode stage,
Move existing unmigrated short instructions to the issue stage
Combinational circuit andInformation processing apparatus characterized by comprising
Place. (2)The decoder comprises:  Multiple short-lived shifts to the decode stage at the same time
CommandAnd among the plurality of short instructions,Those short orders
Until all preceding short orders have been completed.
Instruct to postponeIncluding advance off designation
If there is a NOP instruction,The decode stage
Confirm that there is a NOP instruction including designation of advanced
Having a configuration for outputting information indicating The combination circuit, Advance from the decoder to the decode stage
Information indicating that there is a NOP instruction containing
If it is output, a valid instruction is
At the timing when it no longer exists, the decoding
Multiple short instructions Move to the issuing stage
The system busy signal is no longer active
Until the issuance of each short instruction
2. The system according to claim 1, further comprising a configuration for postponing the line.
An information processing apparatus according to claim 1. (3)DepartureTo postpone the transition to the row stage
NOP instruction including the number of vehicles has moved to the issue stage
The timing included in the NOP instruction
The number of vehicles is preset, then one cycle passes
Equipped with a NOP wait counter that decrements the number of cycles by one,
and, The combination circuit, Cow of the NOP wait counter
Based on the event value, the
Controls postponement of transition of the transition short instruction to the issue stage
2. The information processing apparatus according to claim 1, further comprising:
Equipment.