JP2934690B2 - Inverter device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an inverter device, and more particularly to a pulse width modulation type inverter device used for a portable AC power supply or the like.

(Prior Art) In recent years, an inverter device has been increasingly used in a portable AC power supply device to stabilize an output frequency. For example, an AC generator driven by an engine has a commercial frequency. In a portable power supply device that outputs AC power, a high-power AC current is obtained from a generator by operating an engine in a high rotational speed region, and this AC current is temporarily converted to DC, and then commercialized by an inverter device. A device that converts the frequency into AC and outputs it is
This is known from JP-A-59-132398.

By the way, in such an AC power supply device, there is a demand that the output waveform be approximated to a sine wave as much as possible depending on the use application. In order to meet this demand, a pulse width modulation (PWM) method is adopted for the inverter device. AC power supplies have also been studied (Japanese Patent Application Laid-Open No. 60-1985).
82098).

In such an AC power supply device, when an inverter device is configured by a bridge circuit or the like including FETs, since the source potential of each FET is not the same, a pulse transformer or the like is required when adding a gate signal that is a gate-source voltage. The transmission of the gate signal in a form insulated from the power supply voltage is performed by using the power supply voltage.

In a method of adding a gate signal using such a pulse transformer, a low-frequency component cutting capacitor is provided on the primary side of the pulse transformer, and a demodulation capacitor is provided on the secondary side, so that the carrier frequency is increased. An inverter device that does not cause magnetic saturation of the pulse transformer and can switch the FET appropriately in response to the PWM signal,
The applicant has already filed an application on November 16, 1990.

(Problems to be Solved by the Invention) However, when a large charging current based on the PWM signal suddenly flows through the low frequency component cut capacitor or the demodulation capacitor at the start of the inverter device, particularly at the start of the start, the signal transmission becomes unstable. In that case, there is a problem that the switching operation in the inverter device is not stable.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an inverter device that suppresses instability of a switching operation at the time of starting.

According to the present invention, there is provided a switching device comprising a plurality of FETs connected in series, which alternately controls the output of a DC power supply circuit, and a sine wave-shaped switching device. A pulse width modulation circuit that outputs a PWM signal by pulse width modulation of an input signal in accordance with the amplitude thereof, and a gate of each of the FETs of the switching device through a pulse transformer that outputs a PWM signal output from the pulse width modulation circuit. A gate control circuit that supplies a switching operation of the FETs to a terminal and an output circuit that outputs a sine-wave AC power based on a switching operation of the switching device; Connected to the primary side of the pulse transformer, removing the low frequency components from the input PWM signal to the primary side of the pulse transformer. A low frequency component cutting capacitor to be supplied, and a demodulating capacitor connected to the secondary side of the pulse transformer and demodulating a PWM signal output from the pulse width modulation circuit, and demodulated by the demodulating capacitor. By alternately switching the FETs based on a PWM signal, the output circuit outputs a sine-wave AC power from the output circuit.At the start of starting, the amplitude of the sine-wave input signal is reduced to a small value. And a sine-wave amplitude control circuit that gradually increases the amplitude to the amplitude in the steady operation state.

(Operation) A PWM signal is formed by pulse width modulation of a sinusoidal input signal in accordance with its amplitude, and a low frequency component cutting capacitor removes the low frequency component from the PWM signal and supplies it to the primary side of a pulse transformer. On the secondary side of the pulse transformer, the PWM signal is demodulated by the demodulating capacitor, and the FET is switched based on the demodulated PWM signal.
Based on this switching operation, sinusoidal AC power is output.

At the start of the start of the inverter device, the amplitude of the sinusoidal input signal is gradually increased from a small value by a sine wave amplitude control circuit to reach an amplitude in a steady operation state. Therefore, a large charging current does not suddenly flow to the low-frequency component cutting capacitor or the demodulating capacitor, and an unstable switching operation of the inverter circuit due to a sudden inflow of the charging current can be suppressed.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is an overall configuration diagram of an engine generator including an inverter device according to the present invention. In the drawing, reference numerals 1 and 2 denote output windings wound independently on a stator of an AC generator, respectively. 1 is a three-phase output winding, and 2 is a single-phase auxiliary winding. Further, a rotor (not shown) is formed with magnetic poles of a multi-pole permanent magnet, and is configured to be rotationally driven by an engine (not shown). The output terminal of the three-phase output winding 1 is
The output terminal of the bridge rectifier circuit 3 is connected to the smoothing circuit 4. The bridge rectifier circuit 3 includes three thyristors and three diodes.

The output terminal of the single-phase auxiliary winding 2 is connected to a constant voltage supply device 5 having positive and negative bipolar output terminals E and F. The constant voltage supply device 5 includes two sets of rectifier circuits, a smoothing circuit, and a constant voltage circuit 5a. With respect to the current in the direction, each circuit of the other set works, whereby positive and negative constant voltages are output to the output terminals E and F, respectively.

Reference numeral 6 denotes a thyristor control circuit. One end on the power input side is connected to the positive output terminal E of the constant voltage supply device 5, and the other end is grounded together with the positive terminal on the smoothing circuit 4. The signal input terminal of the thyristor control circuit 6 is a capacitor C1 and resistors R1 to R3.
One end of the capacitor C1 is connected to the positive output terminal E of the constant voltage supply device 5, and the other end of the resistor R3 is connected to the negative terminal of the smoothing circuit 4. The connection point between the resistors R1 and R2 is connected to the base of the transistor Q1, the collector of the transistor Q1 is connected to the base of the transistor Q2, and the collector of the transistor Q2 is connected to the gate input circuit of each thyristor of the bridge rectifier circuit 3. R1 and resistance
It is configured to control the input signal of the gate input circuit according to the potential of the connection point with R2.
Since it is disclosed in 230908, it is omitted here).

The output side of the transient suppression circuit 7 is connected to a connection point K between the capacitor C1 and the resistor R1. According to the transient suppression circuit 7, the cathode side of the Zener diode D1 is connected to the input side (G) of the constant voltage circuit 5a provided on the positive electrode output terminal E side of the constant voltage supply device 5, and the anode side of the Zener diode D1 is connected to a resistor. Is connected to the negative output terminal F of the constant voltage supply device 5 through the inverter, and is connected to the inverting terminal (−) of the inverting comparator 701 composed of an operational amplifier. Grounded. The output side of the inverting comparator 701 is connected to the input side of the NOR circuit 702, while the NOR circuit 7
The other terminal on the input side of 02 is connected with a protection device 8 for detecting that protection is required, such as an overcurrent state of the engine generator, and has detected a state that requires protection. Sometimes a high level signal is supplied to the NOR circuit 702. NO
The output side of R circuit 702 is connected to the base of transistor Q3 via inverter 703 and a resistor. The emitter of the transistor Q3 is connected to the negative output terminal F of the constant voltage supply device 5,
On the other hand, the collector is connected to the positive output terminal E of the constant voltage supply device 5 via the resistor R4 and to the negative output terminal F of the constant voltage supply device 5 via the capacitor C2. The positive terminal of the capacitor C2 is connected to the base of the transistor Q4, and the collector of the transistor Q4 is connected to the constant voltage supply 5
The emitter is connected to the anode of the diode D2 and to the connection point K between the capacitor C1 of the thyristor control circuit 6 and the resistor R1. The cathode of the diode D2 is connected to the positive terminal of the capacitor C2.

The output side of the smoothing circuit 4 is connected to an inverter circuit 9 (switching device). Inverter circuit 9 has four FETs
(Field effect transistor) It is composed of a bridge circuit composed of Q5 to Q8. The drive signal circuits connected to the gate terminals of the FETs Q5 to Q8 will be described later.

The output side of the inverter circuit 9 is connected to output terminals 11 and 12 to which a load (not shown) is connected via an output circuit 10 composed of a low-pass filter. The output circuit 10 includes a low-pass filter including coils L1 and L2 connected in series to the load, and a capacitor C3 connected in parallel to the load,
A current transformer CT is connected between the coil L1 and the capacitor C3 in series with the load.

Both ends of the output terminals 11 and 12 (both ends H of the capacitor constituting the low-pass filter) are connected to a distortion detection circuit 13 including a divided resistor and a differential amplifier. The distortion detection circuit 13 detects a waveform distortion or an offset component of the output by directly comparing the waveforms of the output voltages appearing at the output terminals 11 and 12, and outputs a detection signal.

Reference numeral 14 denotes a sine wave oscillator that generates a sine wave of a commercial frequency, for example, 50 Hz or 60 Hz. The output side of the sine wave oscillator 14 is connected to the inverting input terminal (-) of the operational amplifier of the differential amplifier 15 via a resistor. The output side of the peak detection circuit 16 is connected to the non-inverting input terminal (+) of the operational amplifier of the differential amplifier 15.

The peak detection circuit 16 is connected to the secondary side of the current transformer CT, inverts and amplifies the AC output current detected by the current transformer CT, an output of the inverting amplifier 161 and this output are within a reference amplitude range. Offset amplifiers 162 and 163 that compare the output of the upper / lower limit value setting circuit 164 that supplies the upper and lower limit voltage values to determine whether the output is lower or not, and amplify the portion where the output of the inverting amplifier 161 exceeds the reference amplitude range. And the non-inverting amplifier 165 supplied with the outputs of the offset amplifiers 162 and 163 via the diodes D3 and D4 and amplifying the combined signal.

The differential amplifier 15 differentially amplifies the output of the peak detection circuit 16 and the sine wave output from the sine wave oscillator 14 and outputs
The feedback signal according to the AC output current of
This is for correcting a sine wave signal output from the sine wave oscillator 14.

The output side of the differential amplifier 15 is connected to the inverting input terminal (-) of the operational amplifier of the differential amplifier 17, and the non-inverting input terminal (+) of the operational amplifier of the differential amplifier 17 is connected to the output side of the distortion detection circuit 13. You. The differential amplifier 17 detects the amplitude reference level of the corrected sine wave output from the differential amplifier 15 by using a distortion detection circuit.
The sine wave signal is further corrected by the detection signal output from 13 and is output.

Reference numeral 18 denotes a rectangular wave oscillator, which is set to a value that is significantly higher than the frequency of the sine wave output from the sine wave oscillator 14 having the frequency of the rectangular wave oscillated by the rectangular wave oscillator 18. The output side of the rectangular wave oscillator 18 is connected to an integrating circuit 19, which integrates the rectangular wave and converts it into a triangular wave signal.

The corrected sine wave signal output from the differential amplifier 17 and the triangular wave signal output from the integration circuit 19 are superimposed and supplied to an inverter buffer 20 (pulse width modulation circuit). Inverter buffer 20 has a predetermined threshold (threshold level), and outputs a low-level signal when a signal having a level exceeding the threshold is input, while outputting a signal having a level lower than the threshold. Outputs a high-level signal when it is input, and forms a so-called pulse width modulation (PWM) signal. For example, a C-MOS gate IC having a fixed threshold value for an input signal to a gate terminal It consists of.

The output side of the inverter buffer 20 is input to one input terminal of the NAND circuit 22 via the inverter 21 and is also input directly to one input terminal of the NAND circuit 23 as it is. The output terminal J of the NOR circuit 702 of the transient suppression circuit 7 is connected to the other input terminal of the NAND circuit 22 and the other input terminal of the NAND circuit 23.

The output terminal of the NAND circuit 22 is connected to a push-pull amplifier 24 including transistors Q9 and Q10. Push-pull amplifier
The collector of the transistor Q9 is connected to the positive output terminal E of the constant voltage supply device 5, and the collector of the transistor Q10 is connected to the negative output terminal F of the constant voltage supply device 5.

Output terminal of push-pull amplifier 24 (transistors Q9, Q10
Are connected to the connection point between the anode of the diode D7 and the cathode of the diode D8. The cathode of the diode D7 is connected to the positive output terminal E of the constant voltage supply device 5, and the anode of the diode D8 is connected to the negative output terminal F of the constant voltage supply device 5. The diodes D7 and D8 are for absorbing a surge generated by a pulse transformer described later.

The connection point between the anode of the diode D7 and the cathode of the diode D8 is connected to one end of each of primary coils L3, L4 of the pulse transformers A, C via a capacitor C4 for cutting low frequency components. The other ends of these primary coils L3, L4 are connected to the negative output terminal F of the constant voltage supply device 5. Capacitor
C4 is set to a constant value that allows only high-frequency PWM carrier frequency signals to pass, but not low-frequency components.

The output terminal of the NAND circuit 23 is connected to the transistor Q1 in the same manner as described above.
The output terminal of the push-pull amplifier 25 is connected to a connection point between the anode of the diode D9 and the cathode of the diode D10. This connection point, like the capacitor C4 described above, passes only the PWM carrier frequency signal and does not pass low frequency components.
Of the primary coils L5 and L6.

Returning to FIG. 1A, a drive signal circuit connected to each gate terminal of the FETs Q5 to Q8 will be described. One end of the secondary side of the pulse transformer A is a resistor R5 and a capacitor for demodulation.
The other end of the pulse transformer A on the secondary side is connected to the source terminal of the FET Q5 via a parallel circuit of C6, a resistor R6 and a diode D11. Capacitor C
A connection point between the pulse transformer A and the parallel circuit including the resistor R6 and the diode D11 is connected to the other end on the secondary side of the pulse transformer A via zener diodes D5 and D6. Diode D11
Is connected so that the anode is on the gate terminal side of the FET Q5, and the Zener diodes D5 and D6 are connected such that the anodes face each other.

The secondary side of each pulse transformer B, C, D and the corresponding FET Q6
A circuit exactly the same as the circuit provided between the secondary side of the pulse transformer A and the gate terminal of the FET Q5 is also provided between the gate terminal of Q8 and the gate terminal of Q8.

The output side (M) of the inverter 703 constituting the transient suppression circuit 7 is connected to the sine wave amplitude control circuit 26 according to the present invention, and the output side of the sine wave amplitude control circuit 26 is connected to the sine wave oscillator 14.
Output terminal. The input side of the sine wave amplitude control circuit 26 is configured by a series connection circuit of a resistor R7, a diode D12, and a resistor R8, the resistor R8 side is connected to the base of a transistor Q13, and a connection point between the diode D12 and the resistor R8 is a capacitor C7.
Is connected to the negative output terminal F of the constant voltage supply circuit 5 via The emitter of the transistor Q13 is connected to the negative output terminal F of the constant voltage supply circuit 5, and the collector is a sine wave oscillator 14.
Output terminal.

Next, the operation of the engine generator including the inverter device configured as described above will be described.

The three-phase AC power output from the three-phase output winding 1 with the driving of the engine is rectified by the bridge rectifier circuit 3, smoothed by the subsequent smoothing circuit 4 and converted to DC power,
Fluctuations in the DC voltage in the smoothing circuit 4 are detected by the thyristor control circuit 6 via the resistors R2 and R3, and the conduction angle of each thyristor of the bridge rectifier circuit 3 is controlled based on the detection signal to thereby control the smoothing circuit 4 Feedback control is performed such that the output voltage is stably maintained at a predetermined DC voltage. The output signal from the transient suppression circuit 7 is also input to the thyristor control circuit 6, and the operation of the thyristor control circuit 6 and the bridge rectification circuit 3 based on this signal will be described later.

The gates of the FETs Q5 and Q7 and the FETs Q6 and Q8 of the inverter circuit 9 receive a pulse width modulation signal (PWM) signal described later,
By switching the FETs Q5 and Q7 and the FETs Q6 and Q8 alternately in response to the PWM signal, the DC output of the smoothing circuit 4 is switching-controlled and output to the output circuit 10. The output circuit 10 cuts high frequency components and outputs AC power of the commercial frequency to the output terminal 1.
Supply the load from 1,12.

The waveform of the output voltage appearing at the output terminal 11 and the waveform of the output voltage appearing at the output terminal 12 are compared by a distortion detection circuit 13, and the difference, that is, the distortion or offset component of the output voltage waveform is detected. Output to the differential amplifier 17.

Further, the AC output current is detected by the current transformer CT of the output circuit 10, and the detected AC output current is inverted and amplified by the inverting amplifier 161 of the peak detection circuit 16, and is output to the offset amplifiers 162 and 163, respectively. The offset amplifier 162 compares the amplitude of the output from the inverting amplifier 161 with a predetermined upper limit voltage value input from the upper / lower limit value setting circuit 164 to the inverting terminal (−) of the operational amplifier, and exceeds the predetermined upper limit voltage value. Amplify only the minute (offset amplification). In the offset amplifier 163, the amplitude of the output waveform from the inverting amplifier 161 is
Inverting terminal (-) of operational amplifier from upper / lower limit value setting circuit 164
Is compared with a predetermined lower-limit voltage value input to the control unit, and only the voltage that falls below the predetermined lower-limit voltage value is amplified (offset amplification). The output of offset amplifiers 162 and 163 is diode D3,
It passes through D4 and is superimposed. Therefore, the signal after the superposition is a signal in which only the portion where the amplified AC output current exceeds the predetermined upper limit voltage value or only the portion where the amplified AC output current falls below the lower limit voltage value is synthesized. If the upper and lower limit voltage values are not exceeded, this composite signal will maintain the zero level.

This synthesized signal is amplified by the non-inverting amplifier 165,
The signal is input to the non-inverting terminal (+) of the operational amplifier of the differential amplifier 15. In the differential amplifier 15, this combined signal is
The sine wave from 14 is compared and differentially amplified. That is, when the AC output current exceeds the predetermined upper and lower limit voltage values, feedback correction is performed in accordance with the amount of the excess, the peak portion of the corresponding sine wave is crushed, and this peak portion is corrected. Is output to the next differential amplifier 17.

The differential amplifier 17 compares the corrected sine wave signal output from the differential amplifier 15 with the DC feedback signal output from the distortion detection circuit 13, and corrects the amplitude reference level of the corrected sine wave signal by the feedback signal. Then, the sine wave signal corrected again is output.

The square wave signal output from the square wave oscillator 18 is integrated by an integrating circuit.
It is integrated at 19 and converted into a triangular wave signal (FIG. 2b).
The triangular wave signal and the corrected sine wave signal (FIG. 2A) from the differential amplifier 17 are superimposed to form a superimposed signal (FIG. 2C), which is input to the inverter buffer 20. The inverter buffer 20 outputs a low-level signal when the superimposed signal exceeds the threshold value, and outputs a high-level signal when the superimposed signal is less than the threshold value. As a result, a PWM signal (FIG. 2d) subjected to pulse width modulation is output. Since the PWM signal is formed based on the corrected sine wave signal, the peak value of the AC output current is corrected, and the distortion and the offset component of the output voltage can be reduced. Time comparator (about 1
μsec), which is much faster than the inverter buffer (about 50nse
Since c) can be used to form a PWM signal, it is possible to increase the frequency of the carrier wave, thereby making it possible to supply higher quality AC power with a more approximate sine wave output waveform. .

One of the PWM signals output from the inverter buffer 20 is inverted by the inverter 21 and input to the NAND circuit 22, and the other is input to the NAND circuit 23 as it is. A low-level signal is supplied from the transient suppression circuit 7 to the NAND circuits 22 and 23 when a state requiring protection such as a leakage overcurrent state is detected or a low rotation state such as when starting the engine is detected. At this time NA
The outputs of the ND circuits 22 and 23 become high level signals regardless of the PWM signal, and the PWM signal is not transmitted because this state is continued. On the other hand, when the state requiring protection is not detected and the engine speed is not low, the transient suppression circuit 7
Supplies a high-level signal from the NAND circuits 22 and 2 at this time.
3 outputs a signal obtained by inverting the inverted or non-inverted PWM signal according to the input inverted or non-inverted PWM signal, respectively.The PWM signal is output to the push-pull amplifier 24, and the inverted PWM signal is output to the push-pull amplifier 25. Is supplied.

The PWM signal output from the NAND circuit 22 is subjected to push-pull amplification by the push-pull amplifier 24, and then supplied to the low frequency component cutting capacitor C4. This capacitor C4
The signal just before passing through is a PW with a constant amplitude relative to the reference level.
Although the signal is an M signal, the average voltage (integrated value) of this signal changes in the same cycle as the sine wave from the sine wave oscillator 14, and therefore, the PWM signal has the same frequency (commercial frequency) as the sine wave. ) Components.

The capacitor C4 does not pass the low frequency signal, that is, the commercial frequency signal in this embodiment, but passes only the PWM carrier frequency signal which is the high frequency signal. Therefore, after the PWM signal passes through the capacitor C4, as shown in FIG. The whole pulse train goes up and down in phase opposite to the commercial frequency component, and is converted into a pulse signal train whose average voltage is always zero. The pulse signal train whose average voltage is always zero is supplied to the primary coils L3 and L4 of the pulse transformers A and C. Therefore, the transformer cores constituting the pulse transformers A and C are hardly affected by magnetic saturation due to the commercial frequency component, and can be configured with a small size that does not cause magnetic saturation at the PWM carrier frequency.

The pulse signal (substantially the same as the signal shown in FIG. 2e) output from the secondary coil of the pulse transformer A is compared with the breakdown voltages of the Zener diodes D5 and D6, which are bidirectional voltage regulating circuits, and the output pulse signal is output. When the voltage exceeds each of these breakdown voltages in the positive or negative direction, the Zener diode D5 or D6 conducts to regulate the voltage of the output pulse signal, and the capacitor C6 is charged and discharged, and the capacitor C6 is charged and discharged.
At both ends of C6, an average voltage (which has a commercial frequency) due to the output pulse signal exceeding each breakdown voltage in the positive direction or the negative direction appears. Therefore, between the gate and source of the FET Q5, a signal obtained by superimposing the voltage between both ends of the capacitor C6 having the commercial frequency and the pulse signal output from the secondary coil of the pulse transformer A, that is, the PWM signal before passing through the capacitor C4 ( FIG. 2d) is demodulated. FETQ5 is PW
It conducts correspondingly while the positive pulse signal of the M signal is being input to the gate terminal.

The constant of the capacitor C6 is set to a value sufficiently larger than the gate capacitance of the FET Q5, and the constant of the resistor R5 is set to a value that can be suppressed to Q at which the secondary coil of the pulse transformer A and the capacitor C6 do not resonate. Resistor R6 regulates the switching speed of FET Q5 and diode D11
The purpose is to rapidly discharge the electric charge stored in the gate capacitance of the FET Q5 when the voltage applied to the gate terminal of the FET Q5 is reduced, and immediately turn off the FET Q5. In addition, the Zener diode D6 has a function of preventing the pulse transformer A from increasing the reference potential of the FET Q5 generated by the kickback voltage from the secondary coil.

The pulse signal output from the secondary coil of the pulse transformer C is processed in exactly the same way as the pulse signal output from the secondary coil of the pulse transformer A, and therefore the switching of the FET Q7 is performed at the same timing as the FET Q5. Therefore, when the positive pulse of the PWM signal is input, the FETs Q5 and Q7 become conductive, and a DC current is supplied from the smoothing circuit 4 to the output circuit 10.

Next, the inverted PWM signal output from the NAND circuit 23 is subjected to the same signal processing as that of the signal circuit from the push-pull amplifier 24 to the FETs Q5 and Q7, and the FETs Q6 and Q8 perform switching control in accordance with the inverted PWM signal. Is done. However, since a PWM signal whose phase is inverted is input to the PWM signal applied to the circuits from the push-pull amplifier 24 to the FETs Q5 and Q7, the FETs Q5 and Q7
When FET 7 is on, FETs Q6 and Q8 are off and FET
When Q5 and Q7 are off, switching control is performed so that FETs Q6 and Q8 are on.

As described above, the commercial frequency sine wave feedback-corrected based on the output waveform and the output current is pulse-width-modulated by the high-frequency triangular wave, and the inverter circuit 9 performs switching control based on the pulse-width modulated signal. The carrier frequency component is cut off by the circuit 10, and AC power of a commercial frequency that approximates a sine wave is supplied from the output terminals 11 and 12 to the load.

 Next, the operation of the transient suppression circuit 7 will be described.

Immediately after the start of the engine, the output voltage of the alternator is low, so the voltage at the input terminal of the constant voltage circuit 5a constituting the constant voltage supply device 5 is low.
(Corresponding to the set value of the engine speed set to a value lower than the speed at the time of rated operation), and the Zener diode D1 is non-conductive. Therefore, the inverting terminal (-) of the inverting comparator 701 is at a low level, and the output of the inverting comparator 701 is at a high level.

The NOR circuit 702 outputs a low-level signal when a high-level signal is input to at least one of the input sides.
Is at a low level by the high level output of the inverting comparator 701 or the high level output of the protection device 8.

This low-level signal is inverted by the inverter 703 to become a high-level signal, and conducts the transistor Q3 to turn on the capacitor.
Discharge C2. Therefore, the transistor Q4 is turned off, and the potential at the connection point K between the capacitor C1 and the resistor R1 becomes low.

Therefore, the transistor Q1 of the thyristor control circuit 6 is turned off, the transistor Q2 is turned on, and a low level signal is supplied to the gate of each thyristor of the bridge rectifier circuit 3. Thus, each thyristor does not conduct, and the bridge rectifier circuit 3 does not supply a rectified output. That is, when the engine speed is equal to or less than the set value or when a state requiring protection is detected, the bridge rectifier circuit 3 does not supply a rectified output. Is suppressed, and the output supply when a state requiring protection such as an overcurrent state due to an overload is detected is also stopped.

Next, after the engine is started, the output voltage of the alternator gradually increases, the voltage at the input terminal of the constant voltage circuit 5a increases, and exceeds the breakdown voltage of the Zener diode D1, that is, the engine speed decreases to the set value. When it exceeds, the Zener diode D1 becomes conductive, the inverting terminal (-) of the inverting comparator 701 turns to high level, and the output of the inverting comparator 701 goes to low level.

At this time, if a condition requiring protection has not been detected,
The output of the NOR circuit 702 changes to a high level, and the output of the inverter 703 changes to a low level. Therefore, the transistor Q3 is turned off, and the capacitor C2 is charged via the resistor R7. By this charging, the positive side potential of the capacitor C2 becomes
It gradually increases based on the time constant determined by the capacitance of C2 and the resistance value of resistor R7. Transistor Q4 conducts due to an increase in the positive electrode potential of capacitor C2, but transistor Q4 is non-conductive if the emitter potential of transistor Q4 rises due to the conduction of transistor Q4 and becomes higher than the base potential of transistor Q4. Therefore, the potential at the point K is always maintained at a value slightly lower than the potential on the positive electrode side of the capacitor C2. Therefore, the potential at the point K gradually increases based on the time constant determined by the capacitance of the capacitor C2 and the resistance value of the resistor R7 after the engine speed exceeds the set value.

Accordingly, the base-emitter voltage of the transistor Q1 gradually rises, the transistor Q1 gradually conducts, the transistor Q2 gradually turns off, and the gate voltage input to each thyristor of the bridge rectifier circuit 3 gradually rises. The conduction angle is gradually increased. Finally, the potential at the point K substantially reaches the positive output potential of the constant voltage supply device 5, and the gate voltage of each thyristor is controlled by a predetermined feedback control for maintaining the potential at the connection point between the resistors R1 and R2 at a predetermined value. Leads to the input value.

Thus, even when the engine is started, the output terminals 11, 12
It is possible to prevent a sudden current from entering each thyristor of the bridge rectifier circuit 3 even when the load remains connected to the thyristor. At the same time, by controlling the gate voltage input to each thyristor of the bridge rectifier circuit 3 to gradually increase, the DC output of the smoothing circuit 4 gradually increases after the start of the engine, whereby each of the inverter circuits 9 A sudden voltage change is prevented from being applied to the FET. The effect of such prevention increases as the load connected to the output terminals 11 and 12 increases when the engine starts.
Particularly when the load is in a short-circuit state, the effect of suppressing the adverse effect on the thyristor and the FET is extremely large.

Next, the operation of the sine wave amplitude control control 26 will be described.

As described in the operation of the transient suppression circuit 7, the output of the inverter 703 of the transient suppression circuit 7 becomes high immediately after the start of the engine in which the engine speed is lower than the set value. Therefore, a high level signal is supplied to the sine wave amplitude control circuit 26, whereby the capacitor C7 is charged and the transistor Q13 is turned on. With the conduction of the transistor Q13, the output side of the sine wave oscillator 14 becomes a constant voltage supply circuit 5
Of the differential amplifier 15
Is not supplied with a sine wave signal. Therefore, the low-frequency component cutting capacitors C4 and C5 and the demodulating capacitors (C6 and the like) are charged and discharged with the average current being zero, so that the switching output of the inverter circuit 9 is totally zero and the output terminal 11 , 12 are not supplied with AC output.

Next, when the engine speed exceeds the set value, the output of the inverter 703 of the transient suppression circuit 7 becomes low. Therefore, a low level signal is supplied to the sine wave amplitude control circuit 26,
The capacitor C7 discharges through the resistor R8. Therefore, the transistor Q13 turns off after a predetermined time determined by the time constant determined by the capacitance of the capacitor C7 and the resistance value of the resistor R8. In the unsaturated region of transistor Q13 during the transition of transistor Q13 from conduction to non-conduction, transistor Q13
The collector potential of 13 gradually rises, and therefore the sinusoidal oscillator
The potential on the output side of 14 also gradually rises, and the differential amplifier 15
, The amplitude of the sine wave signal from the sine wave oscillator 14 is gradually increased. Therefore, according to the change of the pulse width modulation signal accompanying this, the low frequency component cut capacitors C4, C5
And the waveform of the average current of charging / discharging in the demodulating capacitor (C6 etc.) gradually becomes an AC waveform having a large amplitude. Switching control is performed in the inverter circuit 9 in accordance with the sine wave signal whose amplitude is gradually increased in this manner, and the gradually increased AC output is supplied to the output terminals 11 and 12.

As described above, the amplitude of the reference sine wave signal supplied to the PWM signal forming unit after the differential amplifier 15 is gradually increased from zero immediately after the engine is started. Always, low frequency component cut capacitors C4 and C5 and demodulation capacitor C6 (pulse transformer B,
The current flowing into the demodulation capacitors connected to the secondary coils of C and D) starts from the state where the average current is zero, so that the current is suppressed from flowing rapidly, and the FET Q5
-The collapse and unbalance of the drive signal supplied to each gate of Q8 are reduced, and the switching operation due to the disturbance of the drive signal is unstable even if the supply of the PWM signal starts from any waveform position of the reference sine wave Can be suppressed.

That is, since the phase state of the reference sine wave when the PWM signal starts to be generated is not constant, if the amplitude of the reference sine wave signal is immediately increased to a high level at the time of starting the engine, depending on the phase state of the reference sine wave. The charging and discharging of the low-frequency component cutting capacitor and the demodulating capacitor may not be balanced, and a current may suddenly flow into these capacitors. In that case, the drive signals supplied to the gates of the FETs Q5 to Q8 may be collapsed, and the FETs that should not be simultaneously turned on may be turned on at the same time.

However, by gradually increasing the amplitude of the reference sine wave signal from zero immediately after the start of the engine at the time of starting the engine, the charging and discharging of the low-frequency component cutting capacitor and the demodulating capacitor can be balanced, and these capacitors can be rapidly reduced. Current is prevented from flowing, and as a result, the inverter device with stable switching operation can be started.

(Effects of the Invention) As described in detail above, the present invention provides a plurality of serially connected
A switching device composed of FETs for alternately controlling the output of the DC power supply circuit, a pulse width modulation circuit for pulse width modulation of a sine wave input signal according to its amplitude and outputting a PWM signal, and this pulse width modulation A gate control circuit that supplies a PWM signal output from the circuit to a gate terminal of each of the FETs of the switching device via a pulse transformer to perform a switching operation of each of the FETs; and a sine wave based on the switching operation of the switching device. An output circuit that outputs the AC power of the pulse transformer, the gate control circuit is connected to the primary side of the pulse transformer, and removes low frequency components from the input PWM signal to the primary side of the pulse transformer. A low-frequency component-cutting capacitor to be supplied, and a pulse connected to a secondary side of the pulse transformer; Output from the modulation circuit
A demodulation capacitor for demodulating a PWM signal, and the FETs are alternately switched based on the PWM signal demodulated by the demodulation capacitor,
A sinusoidal wave configured to output a sinusoidal AC power from the output circuit, and at the start of starting, gradually increasing the amplitude of the sinusoidal input signal from a small value to an amplitude in a steady operation state. Since the amplitude control circuit is provided, it is possible to suppress the instability of the switching operation at the time of starting, and thus it is possible to stably start the inverter device. Moreover, even if the load is started while the load is still connected, the amount of current supplied to the load will gradually increase, so that a large current will not flow to the inverter circuit in an unstable state at the time of start. It is also possible to do.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an engine generator including an inverter device according to the present invention, and FIG. 2 is a time chart diagram of signal waveforms at various parts of the inverter device. 9: Inverter circuit (switching device), 10: Output circuit, 20: Inverter buffer (pulse width modulation circuit), 26: Sine wave amplitude control circuit, C4, C5: Capacitor for cutting low frequency components, C6 …… Capacitor for demodulation.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H02M 7/537 H02M 7/537 C 7/5387 7/5387 Z 7/5395 7/5395 (58) Fields surveyed (Int.Cl. . ⁶ , DB name) H02M 7/42-7/98 H02M 1/08

Claims (2)

(57) [Claims] 1. A switching device comprising a plurality of FETs connected in series, which alternately controls the output of a DC power supply circuit, and outputs a PWM signal by pulse width modulating a sine wave input signal according to its amplitude. And a PWM signal output from the pulse width modulation circuit via a pulse transformer.
A gate control circuit that supplies a gate terminal of T to perform a switching operation of each of the FETs, and an output device that outputs a sine-wave AC power based on a switching operation of the switching device, wherein the gate control circuit Is connected to the primary side of the pulse transformer, connected to the secondary side of the pulse transformer, and to a low frequency component cut capacitor supplied to the primary side of the pulse transformer by removing a low frequency component from the input PWM signal. A demodulation capacitor for demodulating a PWM signal output from the pulse width modulation circuit, and the FETs are alternately switched based on the PWM signal demodulated by the demodulation capacitor, thereby providing the output. The circuit is configured to output a sinusoidal AC power from the circuit, and at the start of starting, the sinusoidal AC power is output. And a sine wave amplitude control circuit for gradually increasing the amplitude of the input signal from a small value to an amplitude in a steady operation state. 2. The FET according to claim 1, wherein said gate control circuit is connected to a series circuit of an attenuation resistor and said demodulating capacitor connected to a secondary side of said pulse transformer, and connected between said series circuit and said FET. A bidirectional voltage regulating circuit for stabilizing the gate-source voltage, and charging / discharging the demodulating capacitor with a voltage exceeding the voltage regulated by the bidirectional voltage regulating circuit, so that the pulse width modulation circuit The inverter device according to claim 1, wherein the output PWM signal is demodulated.