JP2935280B2 - Thin film transistor matrix - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor matrix. In recent years, liquid crystal displays (LCD),
A thin film transistor (TFT) matrix has been used as a driving element for electroluminescence or the like. Such a TFT matrix includes hundreds of thousands of TFTs, and there is a strong demand for improved display quality.

[0002]

2. Description of the Related Art FIGS. 4A and 4B show a conventional inverted stagger type TF.
FIG. 5A is a diagram showing a T matrix. FIG. 5A is a top view, and FIG.
1A is a sectional view, wherein 1 is a substrate, 2 is a gate bus line, 2a
Is a gate electrode, 3 is a gate insulating film, 6 is an amorphous silicon (a-Si) operation semiconductor layer, 7 is a channel protection layer, 8 is a contact layer, 9 is a source electrode, 10 is a drain electrode, 11
Denotes a display electrode, and 12 denotes a drain bus line.

[0003] L using such a TFT matrix
There are various capacities in CD panels. FIG. 5 shows an electrical equivalent circuit of the LCD panel. As shown in this figure, the display electrode 11 or the source electrode 9 has C _GS between _itself and the gate bus line 2, C _TFT between the gate electrode 2 a of the TFT part, and C _DS between the drain bus line 12. It has a coupling capacitance of C _LC between the counter electrode (earth electrode) and the other ground or fixed potential electrode C _FIX between the liquid crystal layer and the counter electrode (earth electrode).

FIG. 6 shows n of such a TFT matrix.
7 shows an applied voltage waveform and a response waveform when writing a data voltage V _DATA to a display pixel connected to a th gate bus line and an m th drain bus line.

[0005] V _G is the voltage applied to the gate electrode 2a, V
_D is the voltage written to the display electrode 11 or the drain electrode 10, and V _COM is the potential of the counter electrode. Incidentally, when the drain voltage V _D is the gate voltage V _G suddenly changes, causing a reduction of only the data voltage [Delta] V _D represented by the following formula by the capacitive coupling with the gate.

[0006] _{ΔV D = ΔV G · (C} GS + C TFT) / (C GS + C TFT +
Decrease amount of _{C DS + C LC + C FIX} ) ΔV D is the data voltage V _DATA in the display electrode 11 and the drain electrode 10 (DC level shift), [Delta] V _G is the swing width of the gate voltage. This DC level shift is T
This causes the display quality of the FT-LCD to deteriorate significantly.

[0007]

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a TFT matrix having a structure in which ΔV _D is reduced.

[0008]

1 (a), 1 (b) and 1 (c) are views showing a thin film transistor matrix according to the present invention.
(a) is a top view, (b) is an AA sectional view, and (c) is a BB sectional view.

The above problem is solved by a thin film transistor matrix having a transparent conductive layer shield 4 covering a gate bus line 2 via an insulating layer 3. Further, the gate bus line 2 is covered via the insulating layers 3 and 5 , and
This is solved by a thin film transistor matrix having a continuous transparent conductive layer shield 4 overlapping a part of the display electrode 11.

[0010]

According to the present invention, the shield 4 of the conductive layer is provided between the display electrode 11 or the source electrode 9 and the gate bus line 2, and the shield 4 is maintained at a constant potential or a ground potential, thereby providing a display. Electrode 11 or source electrode 9
It is possible to erase the C _GS that existed between the gate bus line 2. Instead, by keeping the shield 4 at the ground potential, the amount of C _FIX increases by a certain amount C _S. Therefore, ΔV _D is as follows.

[0011] _{ΔV D = ΔV G · C TFT} / (C GS + C TFT
+ C _DS + C _LC + C _FIX + C _S ) The ratio of this ΔV _D to the conventional ΔV _D is C _TFT / (C _GS +
C _TFT ) or less, so that the DC level shift can be kept low.

Further, if the shield 4 is extended above the display electrode 11 so as to overlap a part of the display electrode 11, the effect of suppressing the DC level shift is further increased. However, if the shield 4 is opaque, the display area is impaired, so the shield 4 needs to be formed of a transparent conductor.

[0013]

1 (a), 1 (b) and 1 (c) are diagrams showing a thin film transistor matrix of the present invention, wherein FIG. 1 (a) is a plan view and FIG.
1A is a glass substrate, 2 is a gate bus line, 2a is a gate electrode, and 3 is a first cross-sectional view.
, A gate insulating layer; 4, a shield; 5, a second insulating layer, a gate insulating layer; 6, an a-Si operating semiconductor layer; 7, a protective insulating layer, a channel protective layer; Is a contact layer, 9 is a source electrode, 10 is a drain electrode, 11
Denotes a display electrode, and 12 denotes a drain bus line.

FIGS. 2 (a) to 2 (c) and FIGS. 3 (d) and 3 (e) are step-by-step plan views showing an embodiment for manufacturing the thin film transistor matrix shown in FIG. Hereinafter, the outline of the process will be described with reference to FIGS.

Referring to FIGS. 1 and 2 (a), Ti is sputtered to a thickness of 1000 ° on a glass substrate 1 and the sputtered film is patterned to form a gate bus line 2 having a width of 10 to 20 μm and a gate electrode 2a having a width of 5 μm. To form The center interval between the gate bus lines 2 is, for example, 0.37
5 mm.

SiN _x is deposited on the entire surface by a plasma CVD method to form a first insulating layer 3 having a thickness of 1000 °. First
The insulating layer 3 becomes a gate insulating layer. An ITO conductive layer having a thickness of 500 形成 is formed on the first insulating layer 3 by sputtering, and the conductive layer is patterned to form a gate bus line 2.
Is formed of a shield 4 of a conductive layer which covers the substrate. The shield 4 also extends to the portion where the display electrode is formed, and is formed so as to overlap the display electrode in the future. The width of the portion where the shield 4 protrudes on both sides of the gate bus line 2 is about 5 μm, and the width of the portion where the shield 4 overlaps a display electrode to be formed in the future is 1 μm.
It is about 0 μm.

FIG. 1, see FIG. 2 (b) the entire surface in the second insulating layer 5 (gate insulating layer) of SiN _x having a thickness of 2000Å by plasma CVD, the thickness 500 Å of a-S
An i-operation semiconductor layer 6 and a protective insulating layer 7 of SiO _{2 having} a thickness of 1500 ° are continuously formed.

A resist is applied, and the resist is left on predetermined portions on the gate bus line 2 and the gate electrode 2a by back exposure from the glass substrate 1 side and exposure to expose a part of the gate electrode 2a from the front side. Using the resist as a mask, the protective insulating layer 7 is etched to leave the protective insulating layer 7 only at a predetermined portion on the gate electrode 2a. This protective insulating layer 7 becomes a channel protective layer.

See FIG. 1 and FIG. 2 (c). An n ⁺ type a-
After continuously depositing Si and Ti having a thickness of 1000 °, n ⁺ -type a-Si and Ti on the resist are removed by a lift-off method, and the source and drain are separated by a protective insulating layer 7.

Thereafter, the Ti layer, the n ⁺ -type a-Si layer, and the a-Si layer are removed by etching using a resist mask patterned so as to leave regions for forming the source electrode and the drain electrode. An n ⁺ -type a-Si contact layer 8, a-S
A TFT element having an i-operation semiconductor layer 6 and a channel protection layer 7 for separating a source and a drain is formed.

Referring to FIGS. 1 and 3 (d), an ITO film having a thickness of 1000.degree. Is formed on the entire surface by sputtering, and the ITO film is patterned by a resist process to form a display electrode 11 connected to the source electrode 9. A part of the display electrode 11 is shielded through the second insulating layer 5.
And the width of the part overlapping with the shield 4 is 10
It is about μm.

Referring to FIGS. 1 and 3E, an Al film having a thickness of 6000.degree. Is formed on the entire surface by sputtering, and the Al film is patterned to form a drain bus line 12 connected to the drain electrode 10. The center interval between the drain bus lines 12 is, for example, 0.125 mm.

In this manner, an inverted stagger type TFT matrix for driving an LCD including 240 rows × 960 columns of TFT elements was completed. The TFT matrix is loaded into the LCD panel were running evaluated [Delta] V _G as 25V. As a result, the DC level shift ΔV _D was 0.7 V. In the conventional inverted stagger type TFT matrix without a shield, the DC level shift ΔV _D was 1.5 V. Thus, the shield 4 covering the gate bus line 2
The DC level shift can be suppressed significantly by providing.

The shield 4 is effective if it is formed so as to cover the gate bus line 2. However, if it is formed so as to extend over the display electrode, the effect of suppressing the DC level shift is increased. However, if the shield 4 is formed of an opaque conductive layer, the area of the pixel is reduced and display quality is deteriorated. In this case, it is necessary to form a shield of a transparent conductive layer.

In this embodiment, the inverted stagger type TFT matrix has been described. However, even in the stagger type TFT matrix, providing a shield of a conductive layer covering the gate bus line is effective in suppressing the DC level shift.

[0026]

As described above, according to the present invention, the DC level shift due to the gate voltage change can be suppressed, the display quality of the TFT driven LCD can be improved, and the yield of the LCD panel can be reduced. Can be improved.

[Brief description of the drawings]

1A to 1C are diagrams showing a thin film transistor matrix of the present invention, wherein FIG. 1A is a top view, FIG. 1B is an AA cross-sectional view, and FIG. 1C is a BB cross-sectional view. .

FIGS. 2 (a) to 2 (c) are top views (part 1) in the order of steps showing an embodiment.

FIGS. 3 (d) and 3 (e) are top views (part 2) in a process order showing an example.

4A and 4B are diagrams showing a conventional thin film transistor matrix, FIG. 4A is a top view, and FIG. 4B is a cross-sectional view along AA.

FIG. 5 is an electrical equivalent circuit of the LCD panel.

FIG. 6 shows an applied voltage waveform and a response waveform.

[Explanation of symbols]

 1 is a substrate, a glass substrate, 2 is a gate bus line, 2a is a gate electrode, 3 is an insulating layer, 1st insulating layer, a gate insulating layer, 4 is a shield, 5 is an insulating layer, and 2nd insulating layer. The gate insulating layer 6 is an a-Si operating semiconductor layer 7 is a protective insulating layer, and the channel protective layer 8 is a contact layer 9 is a source electrode 10 is a drain electrode 11 is a display electrode 12 is a drain bus line.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-175430 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02F 1/136 500 G02F 1/1343

Claims (2)

(57) [Claims] 1. A gate bus line is covered via an insulating layer.
A thin film transistor matrix having a transparent conductive layer shield. 2. The gate bus line is covered with an insulating layer.
And a shield of a continuous transparent conductive layer overlapping a part of the display electrode.