JP2935293B2 - Line processor control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control system for a line processor on a line in a switching system for accommodating an interoffice line.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional technique in this field. In the figure, reference numeral 1 denotes a digital line multiplexer (Digital Ci
rcuit Multiplication Equipment (hereinafter abbreviated as "DCME"), 2 is a transmission synchronization terminal equipment, 3 is an echo canceller device including an echo canceller 3a, an A / μ converter 3b, etc., and 4 is an exchange that handles various communication types. system,
Reference numerals 4a and 4b denote a DCME control unit and an echo canceller device control unit in the switching system 4 corresponding to the DCME control transmission highway path III and the echo canceller device control path IV, respectively, and Ia to Id denote the DCME 1 and the transmission synchronization terminal equipment 2. II is a transmission highway between the transmission synchronization terminal equipment 2 and the echo canceller device 3, and III is a DCME between the echo canceler device 3 and the switching system 4.
A control transmission highway path, IV is a control path between the echo canceller device 3 and the switching system 4 for controlling the echo canceller device 3, and V is a transmission line for inputting and outputting the DCME1 to and from the outside.

As shown in FIG. 4, in the conventional line processing device control system, the International Telegraph and Telephone Consultative Committee (hereinafter referred to as "C
It is necessary to separately set a control information path IV for the echo canceller device 3 including the echo canceller 3a, the A / μ converter 3b, etc., in addition to the DCME1 control path III defined in the recommendation. there were.

[0004]

In the conventional line processing apparatus control system as described above, the switching system 4
Since it is necessary to have independent control functions corresponding to each control path such as the ME1 control path III and the echo canceller device 3 control path IV, the configuration of the switching system 4 becomes complicated, and its hardware scale is reduced. There was a problem of increasing.

[0005]

The above object can be attained by the present invention employing the following novel characteristic configuration system. That is, a feature of the present invention is that when a switching system accommodating an interoffice line controls various line processing devices such as a digital line multiplexer, an echo canceller, and an A / μ converter on the line, the CCITT Recommendation Q . 50 ANNE
A line processing device control method for transferring a control signal using bits on a specific time slot on the same transmission line conforming to XA and uniformly controlling the various line processing devices using the same transmission line. It is.

[0006]

According to the present invention, by adopting the above-mentioned method, a unified control unit provided in the switching system uses a bit on a specific time slot on the same transmission line to unify a unified control unit for various line processing devices. Since a control signal is transmitted and various line processing devices are controlled by the transmission signal, there is no need to provide a transmission control path or a control function in the switching system for each line processing device as in the related art.

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration connection example to which the present embodiment is applied, and FIG.
FIG. 3 is a table showing the configuration of the C and D bits assigned for controlling the echo canceller device. In the figure, reference numeral 4c denotes a unified control unit for the DCME 1 and the echo canceller device 3 provided in the switching system 4, and VI denotes a unified DCME and a transmission highway path for controlling the echo canceller device. Note that the same elements as those of the related art are denoted by the same reference numerals.

This embodiment will be described with reference to FIG. FIG.
, The switching system 4 is a switching system that handles various types of communication, and according to the type of communication from the user, the DCM
When controlling a line processor such as the E1 and the echo canceller 3, the switching system 4 transmits the transmission highway VI (8.4) corresponding to the 2 Mbit / s transmission line time slot 16.
The control signal S1 is transferred onto the time slots 67 to 70 of megabit / s). The echo canceller device 3 controls enable / disable of the echo canceller 3a and the A / μ converter 3b by using a signal related to the own device among the transferred control signals S1. Further, the control signal S1 is transparently transferred from the transmission highway II (8.4 Mbit / s) through the transmission synchronous terminal equipment 2, and the transmission paths Ia to Id are transmitted.
(2 megabits / s) to DCME1. D
Like the echo canceller device 3, the CME 1 performs control such as acquisition of a transmission path corresponding to various types of communication at the request of the user, using a signal related to the own device.

The format shown in FIG. 2 is defined as bits on a specific time slot adopted by the present embodiment. This is the same as the frame format for DCME control shown in 50 ANNEX A. First, an outline of the present frame format will be described. In the frame format shown in FIG.
bit / s 16 frames constitute one multiframe, frame 0 is a multiframe synchronization signal (bits B1 to B4 are all “0”) and bearer resource status information and maintenance information in units of 2 megabit / s (30 channels) , And bearer setup / release information and transmission path failure information (control bits: A, B, C, D) are transferred for the lines in frames 1 to 15. According to CCITT recommendation, A,
Since two bits B, C and D are used, in this embodiment, the A and B bits are
The C and D bits are assigned to the control of the echo canceller device 3 for the DCME1 control based on the T recommendation.

Next, the details of the A, B, C, and D bits assigned for each device control will be described. As described above, the A and B bits assigned to the DCME1 control are
The description is omitted because it conforms to the TT recommendation. In FIG. 3, with respect to the signal S1 from the switching system 4 to the echo canceller device 3, "0" of the C bit is the enable of the echo canceller 3a, "1" is disable,
"0" of the D bit indicates that the A / μ converter 3b is disabled,
"1" is associated with the enable state, and there is a logical combination of C bit = "0" (echo canceller 3a = enable) and D bit = "0" (A / μ converter 3b = disable). Since this is not done, it is possible to prevent the generation of the "00" bit associated with the pseudo synchronization signal. Similarly, as a signal from the echo canceller device 3 to the switching system 4, an alarm (abnormal) state is indicated at [C, D bits = "01" or "10"], and an echo canceller is indicated at [C, D bits = "11"]. A signal indicating a normal state of the A / μ converter 3a and the A / μ converter 3b is assigned, and the [C, D bits = “00”] is not used, thereby preventing generation of a pseudo synchronization signal.

[0011]

As described above, according to the method of the present invention, DCME and an echo canceller connected on a line,
A control path for an echo canceller device including an A / μ converter can be shared, and a data path for control signal transfer of various line processing devices connected to the switching system and a line to be controlled are on the same transmission line. There is no need to set up a new data path, and the line processing unit can be controlled from the switching system without being affected by the installation location of the line processing unit, and the hardware configuration of the switching system is simplified. Demonstrate usefulness.

[Brief description of the drawings]

FIG. 1 is an example of connection of a line processing device to which an embodiment of the present invention is applied.

FIG. 2 is a frame format of a signal corresponding to a 2 megabits / s transmission line time slot 16 in the control method according to the above.

FIG. 3 is a table showing a configuration of C and D bits allocated for controlling the echo canceller device in the above.

FIG. 4 is a connection configuration example of a conventional line processing device control system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... DCME 2 ... Transmission synchronous terminal equipment 3 ... Echo canceller 3a ... Echo canceller 3b ... A / mu converter 4 ... Switching system 4a ... DCME controller 4b ... Echo canceller controller 4c ... DCME / echo canceller controller Units Ia to Id: Transmission path between DCME and transmission synchronization terminal equipment II: Transmission highway path between transmission synchronization terminal equipment and echo canceller device III: Transmission highway path for DCME control IV: Echo canceller device control Path V: Transmission path to / from external input / output to / from DCME VI: Transmission highway path for controlling DCME and echo canceller device

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04Q 11/04 H04M 3/00 H04M 7/00

Claims (1)

(57) [Claims] A switching system accommodating an interoffice line, a digital line multiplexer on the line, an echo canceller, an A / A
When controlling various line processing devices such as μ converters, CCITT Recommendation Q. A line for transmitting a control signal using bits on a specific time slot on the same transmission line conforming to 50 ANNEX A, and uniformly controlling the various line processing devices using the same transmission line. Processing unit control method