JP2936901B2 - Control information setting method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control information for inhibiting control by protect information asynchronous with control information, receiving control information in a package different from the controlled circuit, and distributing the control information to each controlled circuit. Regarding the setting method.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional control information setting method includes a protection information transmission package 20 for generating and distributing protection information at the time of protection, and a control information transmission circuit 11 for generating and transmitting control information. A control package 10 having a response information receiving circuit 12 for receiving response information to the control information;
Control data and control type information based on the
A control information receiving circuit 31 to be formed , a prohibition circuit 32 for invalidating the control type information output from the control information receiving circuit 31 at the time of protection by the protect information, and a control type information output from the prohibition circuit 32 at the time of non-protection. A latch pulse generating circuit 33 for generating a latch pulse for latching control data from the control information receiving circuit 31 into a control data memory circuit 34; and further, the data latched by the control data memory circuit 34 to the control package 10. control information reception package 30 composed of the response information transmitting circuit 35 which responds, and the output of the latch pulse generation circuit 33, to disable the protection information when protected, during unprotected latch pulse inhibit circuit 113~1n3 outputs , This latch pulse prohibition circuit
The control data memory circuit 34 according to the outputs of 113 to 1n3
, And a plurality of controlled packages 110 to 1n0 having latch circuits 111 to 1n1 for latching the output of the control circuit 112 and outputting control data to the controlled circuits 112 to 1n2.

In this configuration, the control information transmitted from the control package 10 is latched in the control data memory circuit 34 in the control information receiving package 30, and the latched data is latched in each of the controlled packages 110 to 1n0 to be controlled. In addition to controlling the circuits 112 to 1n2, the data latched in the control data memory circuit 34 is returned to the control package 10 to recognize whether or not the settings in the control package 10 have been normally performed.

[0004]

In this conventional control information setting method, a latch of a controlled package is set after data is set in a control data memory circuit for determining whether control information has been set normally. Data is latched in the circuit. Also, since the protection information is asynchronous with the control, the control data is latched in the control data memory circuit,
If data is protected before the data is latched by the latch circuit in the controlled package, the data recognized by the control package and the data in the control data memory circuit match, However, there is a problem that the data of the latch circuit differs.

The present invention solves such a problem in the prior art, and provides a control information setting method for preventing the control data recognized by each package from being inconsistent with the timing of protect information. With the goal.

[0006]

In order to achieve the above object, a control information setting method according to the present invention is based on protection information transmitting means for generating and distributing protect information, and control information received from the control means. , generates the control data
And, at the time of protection by the protection information prohibits the generation of the latch pulse by disabling the output of some of the control data, the control de during unprotected
Generates a latch pulse latches the other part of the control data by a portion of the chromatography data, and a control information receiving means for another portion of the control data latched to respond to the control means, the non At the time of protection, a latch pulse from the control information receiving means is input, another part of the control data from the control information receiving means is latched and output to the controlled circuit, and at the time of protection, the protect information is delayed. And a controlled means for invalidating the latch pulse from the control information receiving means.

The control means has a control information transmitting circuit for generating and transmitting control information, and a response information receiving circuit for receiving response information to the control information. a control information reception circuit for receiving control information from the transmitting circuit, the control de during protected
A part of the control data is invalidated by the protection information, and when the protection is not performed, a part of the control data is output , and another part of the control data from the control information receiving circuit is output by the prohibition circuit. A latch pulse generating circuit for generating a latch pulse for latching in the control data memory circuit; and a response information transmitting circuit for responding to the control means another part of the control data latched in the control data memory circuit. A controlled means for disabling a latch pulse from the latch pulse generation circuit according to the protection information during protection, and outputting a latch pulse from the latch pulse generation circuit during non-protection; the output of the circuit, another part of the control data from the control data memory circuit Latched, it is configured to include a latch circuit for output to the controlled circuit, and a delay circuit for delaying the protection information when protected is inputted to the latch pulse suppression circuit.

[0008]

According to the control information setting method of the present invention having the above configuration, the delay amount in the delay circuit in the controlled means is such that the latch pulse generated in the control information receiving package is converted by the latch pulse inhibiting circuit in the controlled package. The value is not invalidated . As a result, the control data recognized by the protect information transmitting means, the control means, the control information receiving means and the controlled means does not cause a mismatch at the timing of the protect information.

[0009]

Next, an embodiment of a control information setting method according to the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of the embodiment. In the following text, in the drawings, FIG.
The same components as those in the middle are denoted by the same reference numerals, and duplicate description thereof will be omitted.

In FIG . 1, this example is schematically constituted by a control package 10, a protection information transmission package 20, and a control information reception package 30. A control information transmitting circuit 11 and a response information receiving circuit 12 are provided in the control package 10, and the protect information transmitting package 20 stores protect information at the time of protection.
A protection information generation circuit 21 for generating is provided. In the control information receiving package 30, a control information receiving circuit 31, a prohibition circuit 32, a latch pulse generation circuit 33 ,
A control data memory circuit 34 and a response information transmitting circuit 35 are provided.

Further, the latch circuit 111~1n1 the controlled package 110～1N0, the control circuit 112-1
n2, latch pulse prohibition circuits 113 to 1n3, and delay circuits 114 to 1n4.

[0012] Next, the operation in the configuration of this embodiment. In the control package 10, the control information transmitting circuit 11
Then, the control information is generated and transmitted, and the response information receiving circuit 12 receives the response information corresponding to the control information. In the protection information transmission package 20, the protection information generation circuit 21
Generates and sends protect information. Control information reception
In the package 30, the protection is controlled by the prohibition circuit 32 at the time of protection.
The control type information from the information receiving circuit 31 is protected information.
Is invalidated by the latch pulse generation circuit 33.
Prohibits pulse generation and receives control information when not protected.
Control data from the communication circuit 31 to the control data memory circuit 3
Generate a latch pulse to latch to 4
Generated by the circuit 33. Further, the control data memory circuit 34
The response data transmission circuit 35 responds to the control package 10 with the data latched by.

The controlled packages 110,..., 1n0
In the latch circuits 111 to 1n1, the output of the latch pulse generation circuit 33 in the control information receiving package 30 is input to the latch pulse prohibition circuits 113 to 1n3. And
Generated by the control information receiving package 30 during non-protection
When the protection information is issued
The protection information is delayed by the delay circuits 114-1n4 so as not to be invalidated by the latch pulse prohibition circuits 113-1n3.

[0014] In this way, the control package 110-1
The delay circuits 114 to 1n4 are provided in n0, and the delay amount is
Generated in control information receiving package 30 when not protected
The controlled latches 110 to 1n0
It is invalid and Sina <br/> have value in latch pulse inhibit circuit 113~1n3 internal. This prevents the control data recognized by each package from being inconsistent due to the timing of the protection information.

[0015]

As described above, according to the control information setting method of the present invention, the amount of delay in the delay circuit in the controlled means is controlled by the non-protection method.
No latch pulse generated by the control information receiving package when transfected with the latch pulse inhibit circuit in the control package
Since the value is set to be invalid, the control data recognized by the protect information transmitting means, the control means, the control information receiving means, and the controlled means does not cause a mismatch at the timing of the protect information.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a control information setting method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration in a conventional control information setting method.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 control package 11 control information transmitting circuit 12 response information receiving circuit 20 protect information transmitting package 21 protect information generating circuit 30 control information receiving package 31 control information receiving circuit 32 inhibit circuit 33 latch pulse generating circuit 34 control data memory circuit 35 response information transmitting Circuits 110 to 1n0 Controlled packages 111 to 1n1 Latch circuits 112 to 1n2 Controlled circuits 113 to 1n3 Latch pulse inhibit circuits 114 to 1n4 Delay circuits 114 to 1n4 Delay circuits for latch pulses

Claims (2)

(57) [Claims] 1. A and protect information transmitting means for distributing to generate protected information, based on the control information received from the control unit generates control data, at the time of protection by the protection information of a portion of the control data output It prohibits the generation of the latch pulse by a void, above during unprotected
By a part of the serial control data to generate a latch pulse latches the other part of the control data, and control the other part of <br/> SL control data on latched to respond to the control means The information receiving means receives the latch pulse from the control information receiving means at the time of non-protection, and receives another signal from the control information receiving means.
The control data of the section is latched and output to the controlled circuit, and at the time of protection, the protection information is input with a delay,
A control means for invalidating a latch pulse from the control information receiving means. 2. The control means includes a control information transmitting circuit for generating and transmitting control information, and a response information receiving circuit for receiving response information to the control information. A control information receiving circuit for receiving control information from an information transmitting circuit, a prohibiting circuit for invalidating a part of the control data by the protect information when protected, and outputting a part of the control data when not protected, another latch pulse generating circuit for generating a latch pulse to latch the control data memory circuit part, control data latched by the control data memory circuit of the control data from the control information reception circuit by the output of and a response information transmitting circuit to respond to the other control part means, the control means, the protected information at the time of protection A latch pulse prohibition circuit that outputs a latch pulse from the latch pulse generation circuit when the protection is not protected, and an output from the latch pulse prohibition circuit. A latch circuit that latches another part of the control data from and outputs it to the controlled circuit, and a delay circuit that delays the protect information and inputs the same to the latch pulse prohibiting circuit during protection. The control information setting method according to claim 1, wherein