JP2937097B2 - Parity check circuit method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity check system suitable for digital communication and the like, and more particularly to a parity monitoring system for inserting a parity operation result into a predetermined time slot of a next frame.

[0002]

2. Description of the Related Art A conventional technique of this kind will be described below with reference to FIG. Note that FIG.
FIG. 1 is a block diagram showing a configuration of a conventional parity monitoring method for inserting a parity calculation result calculated over a frame into a predetermined time slot of a next frame.

As shown in FIG. 4, in a conventional parity check circuit, digital data transmitted on a transmission signal path is input to a parity operation unit 21 to calculate a parity, and the operation result is stored in an operation result holding unit 22. By 1
It is held until the calculation for the frame is completed.

The output of the operation result holding unit 21 is input to one input terminal of a parity bit comparison unit 23, and the other input terminal of the parity bit comparison unit 23 is supplied with a parity bit transmitted at a predetermined timing on a transmission signal path. Is entered.

The parity bit comparing section 23 compares these two inputs and outputs a comparison result of the parity check.

FIG. 5 is a diagram showing an example of a circuit configuration of a 1-bit transmission signal path in the conventional parity check circuit shown in FIG.

Referring to FIG. 5, a parity operation unit inputs exclusive transmission gate 52 to input transmission signal DATA to one input terminal and input the output of AND gate 51 to another input terminal.
And the first flip-flop 53 which receives the output of the exclusive OR gate 52 and feeds back the output to the AND gate 51. The AND gate 51 receives the frame synchronization signal FP.

The second flip-flop 54 functions as an operation result holding unit, and latches a parity operation result for one frame (the output Q of the first flip-flop 53) using the frame synchronization signal FP as a latch timing signal.

[0009] The parity bit comparison unit is provided with a transmission signal DAT.
A second exclusive OR that inputs the parity bit of the frame transmitted as A to one input terminal and inputs the output Q of the second flip-flop 54 constituting the operation result holding unit to the other input terminal It comprises a gate 55 and a third flip-flop 56 which holds the parity bit comparison result output from the second exclusive OR gate 55.

[0010]

In the above-mentioned conventional system shown in FIGS. 4 and 5, a portion for holding a parity operation result (operation result holding section 22) and a parity bit comparing section 23 for comparing parity bits are provided. In two places, it is necessary to hold the operation result. More specifically,
Referring to FIG. 5, a second flip-flop 54 forming an operation result holding unit and a third flip-flop 56 holding a parity bit comparison result are required.
For this reason, in the case of a transmission signal path configuration of a plurality of bits (for example, a 16-bit configuration, etc.), the circuit scale is increased, and the reduction in the number of circuit elements and the circuit scale is impeded.

Accordingly, the present invention has been made in view of the above-mentioned problems, and a holding circuit which functions only for adjusting timing is reduced by using a portion for holding an operation result for an operation and a comparison. Accordingly, it is an object of the present invention to provide a parity check circuit system that achieves a reduction in circuit scale.

[0012]

According to the present invention, one frame of a transmission signal is composed of n time slots.
The parity calculation result calculated over n-1 time slots consisting of lots is used to calculate the next n-th time slot.
In the parity check circuit system, which is compared with the parity bit inserted and transmitted as a result and outputs the result as a parity check result, the transmission signal is input in parallel to perform two types of parity operation and parity bit comparison. A selector for inputting an output of a means for performing a parity operation and a parity bit comparison of a system, selecting one of the outputs and outputting the result as a parity check result, wherein the means for performing the parity calculation and the parity bit comparison of the two systems includes: Frame pulse signal and previous time
Of the holding circuit that holds the parity operation result up to the slot
Output and when the frame sync signal is active
AND circuit for transmitting and outputting the output of the holding circuit to an output terminal
And the input of the output of the AND circuit and the transmission path signal.
It includes an exclusive OR circuit for comparing the these, wherein the holding
The output terminal of the exclusive OR circuit is connected to the input terminal of the circuit
When one system performs a parity operation in one frame period, the holding circuit of the one system is provided with a time slot every time slot.
A bit clock is supplied to the exclusive OR circuit.
Latches the output is fed back this to the AND circuit, the
In another system during one frame period, the transmission path signal
No. in synchronization with the time lot of the parity bit of the signal
Paris up to the last time slot held in the circuit
Ratio between the parity calculation result and the parity bit of the transmission path signal
Bit comparison performed by the exclusive-OR circuit
The holding circuit holds and outputs the result and outputs the result via the selecting means.
A parity operation process and a parity bit comparison process are alternately performed between the two systems for each output frame.

In the present invention, preferably, the means for performing the parity calculation and the parity bit comparison holds a parity calculation result up to a previous time slot used by the calculation circuit for calculating the parity of the transmission signal for the parity calculation. The same holding circuit shares a holding circuit and a holding circuit for holding a comparison result output from a circuit that compares the parity operation result with the parity bit transmitted to the transmission signal. I do.

In the present invention, preferably, the means for performing the parity calculation and the parity bit comparison includes a calculation circuit for calculating the parity of the transmission signal, a parity calculation result by the calculation circuit, and a transmission of the parity calculation result and the transmission signal. And a comparison circuit for performing comparison with the parity bit thus set is shared by the same arithmetic circuit.

According to the present invention, since the parity operation and the parity bit comparison are performed by the same circuit, the number of flip-flops for holding the operation result and comparing with the parity bit is reduced, and the circuit scale is reduced. When applied to a parity check circuit of a transmission line with multiple bits,
The effect of reducing the circuit scale becomes particularly remarkable.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

Referring to FIG. 1, in the present embodiment,
Two parity calculation / parity bit comparison circuits 11 and 12 to which signals are input in parallel from the transmission signal, and the outputs of the parity calculation / parity bit comparison circuits 11 and 12 are input and one of the outputs is selected to check the parity. And a selector 13 for outputting the result.

The two parity calculation / parity bit comparison circuits 11 and 12 perform a parity calculation process when one performs a parity calculation process, and perform a parity calculation between two systems for each frame. And the parity bit comparison process are alternately switched.

That is, in this embodiment, in order to effectively use the operation result holding unit 22 functioning only as a holding unit of the parity operation result for adjusting the timing in the conventional example shown in FIG. Arithmetic unit 21
In addition, a circuit configuration having functions of a parity operation and a parity bit comparison is provided, and as shown in FIG.
Two systems of parity bit comparison circuits 11 and 12 are provided.

The two systems of parity operation / parity bit comparison circuits 11 and 12 alternately perform parity operation and parity bit comparison, thereby reducing a circuit portion for holding only the parity operation result.

Further, in order to continue to output the comparison result of the parity bit, a selector 13 is provided for outputting a comparison between the parity bit and the operation result from one of the parity operation / parity bit comparison circuits.

FIG. 2 shows an example of a suitable circuit configuration of the parity check circuit system according to the present embodiment with respect to the configuration of a 1-bit transmission signal path. Referring to FIG.
This embodiment will be described below based on a more specific circuit configuration.

Referring to FIG. 2, a transmission signal is input to one input terminal of first and second exclusive OR gates 32 and 35, and is transmitted to first and second exclusive OR gates 32 and 35. The output of the first and second AND gates 31 and 34 controlled by the frame synchronization signal FP is input to the other input terminal 35.

First and second AND gates 31, 34
Outputs the outputs of the first and second flip-flops 33 and 36 (for example, composed of D-type flip-flops) to exclusive OR gates 32 and 35 using the frame synchronization signal FP as a gate signal.

The selector 37, which receives the outputs of the first and second flip-flops 33 and 36 as inputs, selects the parity operation and parity bit comparator of the second system on the second flip-flop 36 side. In this case, the output of the second flip-flop 36 holds and outputs the parity bit comparison result of the immediately preceding frame flowing as a transmission signal by the clock signal CLK2 input to the control terminal.

At this time, the parity calculation and parity bit comparison unit of the first system on the side of the first flip-flop 33 performs the parity calculation of the frame currently flowing on the transmission path.

When the first system performs the parity operation, the output of the first flip-flop 33 indicates the result of the parity operation, and the result of the operation and the bit data of the next time slot are converted into the first exclusive logic. The output of the first flip-flop 33 is fed back to the first AND gate 31 in order to perform the addition operation in the sum gate 32.

When the addition is completed for one frame, the first AND gate 31 to the first exclusive OR gate 32 constituting the adding section are cleared by the frame synchronization signal FP, and the output of the first flip-flop 33 is output. Is output and held by the clock signal CLK1, and the selector 37 outputs the parity bit comparison result to the first flip-flop 3
Select 3 side. Conversely, the parity calculation and parity bit comparison unit on the second flip-flop 36 side (second system) that has output the parity bit comparison result until that time starts the parity calculation.

The operation of the present embodiment will be described in detail with reference to the timing diagram of FIG. In the timing diagram shown in FIG. 3, for convenience, one frame is composed of six time slots, and 5-bit data (for example, t
It is assumed that the parity bit P1 of the one frame is inserted into the time slot following 2 to t6) and transmitted.

Referring to FIG. 3, in the first frame, selector 37 selects the second system (the signal path of second exclusive OR gate 35 and second flip-flop 36 in FIG. 2). Then, the second flip-flop 36 (FF3
6) Parity bit comparison result from output QB (Q7)
Is output, and the parity operation is performed by the first system (the path of the first first exclusive OR gate 32 and the first flip-flop 33 in FIG. 2).

In the first system, transmission signals (t2 to t6)
At the first exclusive OR gate 32 and sequentially adds the result of the operation held in the first flip-flop 33 up to that time. That is, the second exclusive OR gate 35 adds the transmission signal to the output of the first AND gate 31 to which the output QA of the first flip-flop 33 holding the operation result up to that time is fed back. Then, the addition result is latched by the first flip-flop 33 by the clock signal CLK1 (the output QA of the first flip-flop 33 changes to Q1,..., Q6 for each time slot in synchronization with the clock CLK1). The first flip-flop 33 is cleared to zero at the timing of the clock signal CLK1 based on the frame synchronization signal FP before the start of the parity calculation of the frame.

At the time of the parity operation, the output QA of the first flip-flop 33 of the n-th clock is transmitted signals t2 to tn.
(Where n is 2 to 6) is a cumulative addition value (see the following equation (1)), and the addition is performed for one frame.

Qn = t2 +... + Tn (1)

In the first system, when the parity operation for one frame is completed, the first exclusive OR gate 32 sets the parity bit P1 inserted in the transmitted frame and the first flip-flop 33 (See the following equation (2)), and outputs a parity bit comparison result Q7. The first flip-flop 33 synchronizes the parity bit with the clock signal CLK1. The result Q7 is held and output, and is selectively output from the selection unit 37.

Q7 = Q6 + P1 (2)

In the next frame, in the second system (the second exclusive OR gate 35 and the second flip-flop 36), the parity operation is performed in the same manner as in the first system. , The parity bit comparison result Q7 output from the first flip-flop 33 is selected and output.

A clock (bit clock signal) indicating 1-bit data is used for a frame for which a parity operation is performed, and a timing signal indicating the position of a parity bit is used for a frame for comparing parity bits. The clock is input to the flip-flops 33 and 36.

The selecting section 37 alternately performs parity calculation and comparison for each frame for each frame.
And the side that holds the parity bit comparison result (the side that does not perform parity operation) among the second flip-flops 33 and 36 is selected and output.

Although the present invention has been described with reference to the above embodiments, the above circuit configuration is for describing the embodiments, and the present invention is not limited to only the above embodiments, but is based on the principle of the present invention. It is needless to say that various forms corresponding thereto are included.

[0041]

As described above, according to the present invention, by performing the parity operation and the parity bit comparison in the same circuit, the number of flip-flops for holding the operation result and comparing with the parity bit is reduced. In particular, in a parity monitoring method for a plurality of transmission signal paths, there is a remarkable effect that the circuit scale is particularly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a parity check circuit system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a circuit configuration of a parity check circuit system according to an embodiment of the present invention.

FIG. 3 is a timing diagram schematically illustrating an operation of a parity check circuit system according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional parity check circuit system.

FIG. 5 is a diagram illustrating an example of a circuit configuration of a conventional parity check circuit.

[Explanation of symbols]

11, 12 parity operation circuit / parity bit comparison circuit 13 selection unit 21 parity operation circuit 22 operation result holding unit 23 parity bit comparison circuit 31, 34 AND gate 32, 35 exclusive OR gate 33, 36 flip-flop 37 selection unit 51 AND gate 52, 55 Exclusive OR gate 53, 54, 56 Flip-flop CLK Clock signal CLK1 Clock signal of flip-flop 33 CLK2 Clock signal of flip-flop 36 D Input data (transmission signal) DATA Transmission signal FP Frame pulse P1 Parity bit of previous frame QA Output of flip-flop 33 Output of QB flip-flop 36 t1 to t6, T1 to T6 Transmission signal (bit data)

Claims (1)

(57) [Claims] 1. One frame of a transmission signal is composed of n time slots.
The parity calculation result calculated over n-1 time slots consisting of the following n-th time slot
In the parity check circuit method, which is compared with a parity bit inserted and transmitted as a result and output as a parity check result, the transmission signal is input in parallel, and two systems are provided for performing parity calculation and parity bit comparison. receives the output of the parity operation and means for performing a parity bit comparator, and selects either a selection means for outputting a parity check result, means for performing a parity calculation and parity bit comparator of the two systems, frame The pulse signal and the time until the last time slot
And the output of the holding circuit that holds the result of the
When the frame synchronization signal is active, the output of the holding circuit is output.
An AND circuit for transmitting and outputting a force to an output terminal; and an input of the output of the AND circuit and the transmission line signal, and
And a exclusive-OR circuit for comparing, to the input terminal of the holding circuit output of the exclusive OR circuit
End connected, when one of the system performs a parity operation in one frame period
Means that the holding circuit of one system is
And the output of the exclusive OR circuit is supplied.
And feeds it back to the AND circuit, and in the other system during the one frame period, the transmission
In synchronization with the time lot of the parity bit of the
Up to the previous time slot held in the holding circuit
Parity operation result and parity bit of the transmission path signal
Parity bit obtained by comparing the data with the exclusive OR circuit
The holding circuit holds and outputs the comparison result and outputs the result through the selecting means.
To be outputted, the parity check circuit system and performs parity calculation process and the parity bit comparison process alternates between the two systems for each frame.